JPH0334076B2 - - Google Patents

Description

[Detailed Description of the Invention] Technical Field of the Invention The present invention provides a display control device equipped with a unique display RAM in which a display control signal is created from two signals sent from a CPU.
Regarding RAM control method.

Technical Background of the Invention Conventionally, when RAM is used for display purposes, the number of selection signals (common signals) is determined according to the duty.
A display control method was used that required .

Problems with the Background Art This type of system does not pose a problem in a one-chip system, but when the display functions become multi-functional and a display-only chip becomes necessary, the selection signal sent between the CPU and the display-only chip becomes The disadvantage is that the number of lines increases and the interface becomes complicated.

Purpose of the invention This invention has been made in view of the above points,
Its purpose is to create a display control signal from two signals sent from the CPU in a display control device equipped with its own display RAM.
The objective is to provide a control method.

Summary of the Invention A clear signal for an n-ary counter is created from two signals (clock signal φ _A and frame signal FR) sent from the CPU, and the above frame signal
Frame signal synchronized with common signal from FR
A timing signal generation circuit for generating FR' is provided.

Embodiment of the Invention An embodiment of the invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a display control device equipped with a display RAM. In the figure, 11 is an n-ary counter. A clock signal φ _A sent from a CPU (not shown) is input to a clock terminal CP of the n-ary counter 11 . Also, CPU
The frame signal FR sent out is input to the timing signal generation circuit 12. This timing signal generation circuit 12 includes clocked inverters 121 to 121.
126, inverters 127 to 129, and an AND circuit 13. The output signal of the inverter 127 (point signal) and the output signal of the clocked inverter 123 (point signal) are input to the AND circuit 13, respectively. be done. The output of this AND circuit 13 is then fed to the n-ary counter 11.
is input to the clear terminal CL. Further, the output signal of the inverter 129 is output as a frame signal FR'. The signals output from the n-ary counter 11 are input to AND circuits 141-14j via signal lines _x1 -xj. Also, CPU
The chip select signal CS sent from
is input. Therefore, the row address signals X ₁ to Xj sent from the CPU are output from the AND circuits 161 to 1.
6j. Here, the AND circuit 16
A chip select signal CS is input to 1 to 16j. And the AND circuits 141 and 161
output signal or the AND circuits 14j and 16
The output signal of j is input to a row decoder (ROW DECORER) 18 via OR circuits 171 to 17j. This row decoder specifies the row address of the display RAM 19. In addition, data D ₁ to Dl sent from the CPU are sent to the data control section (DATA
CONTROL) 20. A chip select signal CS sent from the CPU is input to this data control section 20. Further, the chip select signal CS and the continuous output/write signal R/W sent from the CPU are input to the data control section 20. Furthermore, the column address signals Y ₁ to Ym sent from the CPU are sent to the column decoder (COLUMN
DECODER) 21. The column decoder 21 then specifies the column address of the display RAM 19. Thus, the display data output from the display RAM 19 is input to the display LATCH/LEVEL conversion circuit 22. This display LATCH/
The frame signal FR' outputted from the timing signal generation circuit 12 is input to the LEVEL conversion circuit 22. And the above display LATCH/LEVEL
The conversion circuit 22 outputs segment signals SEG ₁ to SEGk to a display section (not shown).

Next, the operation of the present invention configured as described above will be explained. First, the common signal COM1 sent from the CPU, the clock signal φ _A , and the frame signal FR
are shown in Figure 2 A to C, and
The frame signal FR sent from the CPU is input to the timing signal generation circuit 12. In the timing signal generating circuit 12, the input frame signal FR is synchronized with the clock signal _A , and a signal having a waveform as shown in FIG. 2D appears at a point. Next, the signal at a point as shown in FIG. 2D has a waveform as shown in FIG. E in synchronization with the clock signal φ _A. Since the signals at the above points and points are input to the AND circuit 13, the AND circuit 13 outputs a clear signal as shown in FIG.
CL is output. The n-ary counter 11 is reset by this clear signal CL. The n-ary counter 11 is incremented in synchronization with the input clock signal _φA as shown in G to I in the figure.
In this case, the case where j=3 (octal counter) is explained. Furthermore, the signal at the point shown in FIG. 2E is synchronized with the clock signal _A and is displayed as a frame signal FR' as shown in FIG.
It is output to the LEVEL conversion circuit 22. As a result, the frame signal FR' is synchronized with the common signal COM1 shown in FIG.

By the way, when the chip select signal CS sent from the CPU is at the "0" level, the AND circuit 1
Since the gates 41 to 14j (j=3) are open, the count values "0" to "7" of the n-ary counter 11 are output to the AND circuits 141 to 14j (j=3) and the OR circuit 1.
71 to 17j (j=3) to the row decoder 18
is input. Then, the row decoder 18 specifies the address of the "0" to "7" rows of the display RAM 19. Due to this, the above display
The display data stored in the “0” line to “7” line of RAM19 is displayed at LATCH/LEVEL.
It is output to the conversion circuit 22. That is, the display
The display data (that is, point data) input to the LATCH/LEVEL conversion circuit 22 is row data having the same value as the count value of the n-ary counter 11, as shown in FIG. 2J. Furthermore, the above display
One line of display data input to the LATCH/LEVEL conversion circuit 22 is delayed by one clock and output as segment signals SEG1 to SEGk (k=32) to a display section (not shown). As a result, the frame signal FR' input to the display LATCH/LEVEL conversion circuit 22 and the display RAM 19 output from the display LATCH/LEVEL conversion circuit 22 become "0".
Segment signal SEG1 corresponding to rows to “7” rows
~SEGk (k=32) is synchronized. here,
Eight pieces of data are stored in each row of the display RAM 19, and if each data is composed of 4 bits, the number of segment signals for one row is 4×8=32.

Therefore, when writing display data to the display RAM 19, the write signal is set to "1" by the CPU.
state, the chip select signal CS is set to "1" state, and the row address signals _X1 to Xj and column address signals
Specify the address with Y ₁ ~ Ym and send data D ₁ ~ Dl
This is done by sending the .

Effects of the Invention As detailed above, according to the present invention, even when display functions become multi-functional and a display-only chip becomes necessary, two signals (clock signal φ _A , frame signal FR) alone can provide segment outputs corresponding to a large number of duties.

[Brief explanation of the drawing]

Figure 1 shows a display RAM showing one embodiment of this invention.
FIGS. 2A to 2L are timing charts for explaining the operation. 11...N-ary counter, 12...Timing signal generation circuit, 18...Row decoder, 19...Display
RAM, 20...Data control unit, 21...Column decoder, 22...Display LATCH/LEVEL conversion circuit.

Claims (1)

[Claims] 1. In an electronic device having a display unit whose display is driven by the first to kth segment signals and the first to jth common signals output from the CPU,
A display RAM that stores j rows of display data, an n-ary counter that is incremented by a clock signal φ _A output from the CPU and specifies the row address of the display RAM, and a a display latch unit that latches display data for a row and outputs the first to k-th segment signals after delaying the display data by one clock signal φ _A ; and the CPU;
The clear signal _{CL which clears the count value of the n-ary counter synchronized with the falling edge of the clock signal φ A from} the frame signal FR output from and a timing signal generating section that generates a frame signal FR' to be output to the display latch section.
A display RAM control method characterized in that the rising edge of FR rises earlier than the rising edge of the first common signal by one clock signal _φA .