JPH0334149U

JPH0334149U -

Info

Publication number: JPH0334149U
Application number: JP9558789U
Authority: JP
Priority date: 1989-08-14
Filing date: 1989-08-14
Publication date: 1991-04-03

Description

[Brief explanation of drawings]

第１図は本考案の第１の実施例を示すブロツク
図、第２図は第１図に示された実施例のバスサイ
ジング・レジスタのデータフオーマツト図、第３
図は本考案の第２の実施例のバスサイジング・レ
ジスタの内部のブロツク図である。１Ａ〜１Ｈ……データバス、２，２Ａ……バス
サイジング・レジスタ、３……バスコントロール
・ユニツト、４……バスサイジング・コントロー
ルロジツク部、５Ａ〜５Ｈ……エータバスバツフ
ア、２１……メモリ・バスサイジング・レジスタ
、２２……Ｉ／Ｏ・バスサイジング・レジスタ、
２３Ａ〜２３Ｈ……メモリ・ベースレジスタ、２
４Ａ〜２４Ｈ……メモリ・マスクレジスタ、２５
Ａ〜２５Ｈ……Ｉ／Ｏ・ベースレジスタ、２６Ａ
〜２６Ｈ……Ｉ／Ｏ・マスクレジスタ、Ｉ／Ｏ０
〜Ｉ／Ｏ１５，ＭＯ〜Ｍ１５……ブロツクバス幅
記憶部。 FIG. 1 is a block diagram showing a first embodiment of the present invention, FIG. 2 is a data format diagram of the bus sizing register of the embodiment shown in FIG. 1, and FIG.
The figure is an internal block diagram of a bus sizing register according to a second embodiment of the present invention. 1A to 1H...Data bus, 2, 2A...Bus sizing register, 3...Bus control unit, 4...Bus sizing control logic section, 5A to 5H...Etabus buffer, 21... Memory bus sizing register, 22...I/O bus sizing register,
23A to 23H...Memory base register, 2
4A to 24H...Memory mask register, 25
A~25H...I/O/base register, 26A
~26H...I/O/mask register, I/O0
~I/O15, MO~M15...Block bus width storage section.

補正平２．１０．１８図面の簡単な説明を次のように補正する。明細書第８頁第１行の「２３Ｈ」を「２３Ｐ」
とする。明細書第８頁第２行の「２４Ｈ」を「２４Ｐ」
とする。明細書第８頁第３行の「５Ｈ」を「５Ｐ」とす
る。明細書第８頁第３行の「２６Ｈ」を「２６Ｐ」
とそれぞれ補正する。Amendment October 18, 1992 The brief description of the drawing is amended as follows. "23H" in the first line of page 8 of the specification is replaced with "23P"
shall be. “24H” on page 8, line 2 of the specification is replaced with “24P”
shall be. "5H" on page 8, line 3 of the specification is replaced with "5P". Replace “26H” on page 8, line 3 of the specification with “26P”
and correct them respectively.

Claims

[Scope of utility model registration request]

A multi-bit data bus that connects to an external device with a predetermined address range, and a bus that divides the available address space into multiple blocks and stores the address range of each block and the bus width of the data bus of the external device. a sizing register;
A bus sizing method that reads the bus width of the block containing the specified address from the bus sizing register and sets the bus width of the data bus connected to the external device corresponding to this address according to the read bus width. A bus sizing device characterized by having a control logic section.
processor.