JPH0334151U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention;
1 is a timing chart for explaining the operation of FIG. 1, FIG. 3 is a state transition diagram of the arbitration circuit of the present invention, and FIGS. 4a and 4b are timing charts for explaining conventional arbitration. 1...Memory controller, 2...Request arbitration circuit, 3...Arbitration result save register, 4...Address counter, 5...Address path, 6...Multiplexer.

Claims (1)

[Claim for Utility Model Registration] In a shared memory arbitration circuit that permits execution of any one microprocessor by memory access to the shared memory from multiple microprocessors, a request from any one of the multiple microprocessors a memory controller having a memory control signal output that executes memory access of the microprocessor in response to input of a request confirmation signal indicating whether the request confirmation signal has been accepted; an interrupt enable signal output; and an access completion signal output indicating the completion of one access. , When a plurality of memory access request signals are input, even if the access end signal from the memory controller does not indicate completion, if the interrupt enable signal is valid, the priority order in which requests are accepted among the plurality of memory access request signals is determined. the request confirmation signal that outputs a higher-order request, an arbitration result that outputs a lower-order request that does not approve the request, and an evacuation flag that indicates the existence of an interrupted lower-order request, and while the evacuation flag is being displayed. a request arbitration circuit that inputs the arbitration result upon input of an access completion signal from the memory controller indicating completion of memory access for the request with the higher priority; and a request arbitration circuit that temporarily saves the arbitration result from the request arbitration circuit and executes the request arbitration. An arbitration result save register that outputs to the circuit, an address counter that generates an address for memory access, and when a memory access for a request with a higher priority occurs, the address generation of the address counter is interrupted and the address of the request is generated. 1. An arbitration circuit for a shared memory, comprising: an address path that is generated; and a multiplexer that switches the address counter or the address path to obtain an address path.