JPH0334155B2 - - Google Patents

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to a unit of memory circuit, that is, a memory cell, which is necessary when constructing a Josephson memory circuit, and in particular relates to a Josephson memory circuit that can be selected by two-line matching. This invention relates to improvements in the structure of storage cells.

<Prior art> Similar to existing semiconductor memory circuits, the Josefson memory circuit also uses a plurality of unit memory cells.
By arranging them in an X-Y matrix, it is possible to selectively specify one memory cell using a two-line matching method using the Y line or word line and the X line or bit line. It is desirable to be able to selectively write and read data.

Conventional Josefson memory cells that meet these demands include those that form an inductance part in a superconducting closed loop, and depending on whether or not magnetic flux quanta are stored in the closed loop, the information content is selectively "1", It represented "0".

<Problems to be Solved by the Invention> The conventional Josefson memory cell as described above requires an inductance greater than a certain value within the cell.

Therefore, there is a limit to the size of the memory cell itself, and even if there is a technology that can achieve further miniaturization or miniaturization in manufacturing, the cell size or occupied area can only be reduced to a certain extent. Can not do it.

This is never desirable. This type of Josefson memory circuit is expected to become one of the main memory circuits in future information processing technology, and it is not difficult to imagine that it will be required to have an extremely high degree of integration. It is.

Furthermore, the presence of inductance in the signal transmission/reception path is also undesirable from the viewpoint of operational functionality. This is because it causes a delay in signal propagation time and becomes an obstacle to speeding up information processing.

In view of these conventional circumstances, the present invention provides physical,
The main objective is to provide a Josefson memory cell that can be selected by two-line matching without using inductances that are undesirable both dimensionally and functionally. Therefore, it is an object of the present invention to provide a Josephson memory cell which can be expected to operate at high speed.

<Means for Solving the Problems> In order to achieve the above object, the present invention includes: a Josephson junction whose one end is connected to a common reference potential; and two junctions whose respective ends are connected to the other end of the Josephson junction. A Josephson memory cell comprising: a resistor; the other end of one of the two resistors is connected to a word line, and the other end of the other resistor is connected to a bit line. .

<Operation> In the Josefson memory cell of the present invention configured as described above, by appropriately setting the value of each resistor and appropriately controlling each potential of the word line and bit line, logic " 1” to logic “0”
It becomes possible to write and read data.

For example, when the word line and bit line potentials are both changed from a first potential under steady state conditions to a second potential, the Josephson junction transitions to a voltage state and one logic value, e.g. Logic “1”
A state corresponding to occurs, and the latching function of the Josefson junction causes the voltage state to be maintained even if the second potential is subsequently returned to the first potential, and similarly the word line and bit line If the potentials are both changed to a third potential, the Josephson junction is held or brought to a zero voltage state, and this is changed to the other logical value,
For example, it is possible to create a relationship in which the contents are not changed even if the word line and bit line potentials are respectively returned to the first potentials after corresponding to logic "0".

In the above, each of the first, second, and third potentials is
Although the word lines and bit lines may have different voltages, it is generally easier to set them to the same voltage in terms of design. Similarly, although in principle the resistance values of the first and second resistors may be different from each other as long as the above operations are satisfied, it is more practical to make them the same.

Generally, in absolute value, the second potential required to write a logic "1" is higher than the first potential in a steady state, and the third potential used to write a logic "0" or erase a stored logic value is lower. In particular, the third potential is generally zero.

Regarding reading of stored information, for example, if X selection is made by disconnecting the bit line potential from the bit line, and then a voltage changed from the first potential to the second potential is applied to the corresponding word line as Y selection,
Depending on whether the X-Y selected storage cell is storing a logic "1" or a logic "0", different magnitudes of current can be obtained on the corresponding bit line. Therefore, the storage logic information embodied in the current value can be read out using an appropriate detection circuit, and can be performed non-destructively on the storage contents of the storage cell.

<Embodiment> FIG. 1 shows an equivalent circuit of a basic embodiment of the Josefson memory cell of the present invention.

The memory cell of the present invention has a Josephson junction 1 represented by a single Josephson junction in terms of an equivalent circuit, and two resistors 2 and 3.

One end of Josephson junction 1 has a common reference potential,
Generally connected to ground potential, one end of each of the two resistors 2, 3 is connected to the other end of the Josephson junction 1.

The other end of one or the first resistor 2 is connected to the word line 4,
The other end of the second resistor 3 is connected to the bit line 5, and the word line 4 and bit line 5 are connected to a voltage source capable of applying appropriate potentials Vw and Vb to the corresponding lines, as described later. , preferably a constant voltage source 6,
7 is connected.

The static properties of Josephson junction 1 as a unit are:
As is already known, the history paths a, b, c, and d shown in FIG. 2 are followed.

That is, until the current flowing through the Josefson junction 1 exceeds the critical current value Io, no significant voltage appears across the junction, as shown by path a along the current axis Ij, and a zero voltage state is maintained. , when the critical current value Io is exceeded, the transition moves to a point Pg where a gap voltage Vg is generated, which is determined by the material forming the junction, as shown by path b.

Once the junction transitions to these voltage states,
After that, even if the supply current is reduced below the critical current value Io, a latching operation occurs in which the voltage state is maintained as shown by path c, and as the supply current is further reduced, the voltage state moves from the knee point Pk to zero voltage state. route d
occurs. However, the voltage state is still maintained on the path d.

In response to such static characteristics, as in the present invention, constant voltage sources 6, which generate voltages Vw and Vb, respectively, are used.
When resistors 2 and 3 are connected in series with 7, the resistors 2 and 3 become load resistances, and a load line Lo can be drawn on the static characteristics in FIG.

For simplicity, assuming that both resistances 2 and 3 have the same value R, the slope of the load line Lo is -R/2, the intercept Pi on the current axis Ij is (Vw + Vb)/R, and the voltage axis Vj The intersection point Pv is (Vw+Vb)/2.

Therefore, the Josefson junction 1 in this memory cell operates to selectively take only one state, with the two intersections P1 and P2 between the load line Lo and the static characteristics as stable points. Note that one intersection point P1 is the current axis intercept Pi.

In the case shown in the second diagram, the load line Lo has its current axis intercept Pi to the first intersection Pl, which is the critical current value Io of the junction.
shown as lower than.

However, if we consider this in reverse, FIG. 2 shows that the constant voltage sources 6,
It is suggested that by appropriately determining the respective voltage values Vw and Vb of 7, it is possible to draw a load line in which the current axis intercept Pi exceeds the critical current value Io.

Also, as a special case, if the voltage values Vw and Vb of the constant voltage sources 6 and 7 are both zero or approximately zero, the only stable point of the junction is the origin O, which is in a zero voltage state. I also understand.

Based on these findings, the Josefson storage cell according to the present invention shown in FIG. 1 may enable selection by two-line matching and writing and reading to the selected storage cell.

As shown by the load line Lo shown in Figure 2,
As a steady state, the current axis intercept Pj, that is, one intersection point
P1 is the critical current value Io of the Josephson junction used
The voltage values Vw and Vb of both constant voltage power supplies 6 and 7 are set so that a load line that does not reach . In this case, in order to simplify the design, just as the values of both resistors are set to be the same as R, the voltage values of both are set to the same value V1.

In such a case, the load line Lo in the steady state of the Josefson memory cell shown in FIG. 1 becomes the load line Lo rewritten and shown in FIG. 3 for explaining the operation of the memory cell.

That is, the value of the first intersection point P1 corresponding to the current axis intercept is 2·V1/R, the value of the voltage axis intercept is V1, and a load line Lo having a slope of -R/2 can be drawn.

Therefore, the load line Lo that defines the steady state
When setting the voltage value V1 to subtract
For example, when twice the voltage value 2·V1 is applied from each constant voltage source 6, 7 to the corresponding word line 4, bit line 5, the current axis intercept P3 of the load line L1 at that time is the Josephson junction used. Critical current value of
If the voltage exceeds Io and the potential of only one of the constant voltage sources for the word line or bit line becomes 2·V1, while the other remains at V1, as shown by the virtual load line L2. In addition, the current axis intercept P5 is designed to satisfy the condition that the current axis intercept P5 does not exceed the critical current value Io.

With the voltage value relationship set in this manner, logical value information can be written or rewritten into a memory cell selected by two-line coincidence in the following manner.

Here, Josephson junction 1 is connected to the load line
Under the steady state according to Lo, it is assumed that logic information "0" is stored in this Josefson memory cell if it is in the zero voltage state indicated by the intersection P1, and if the junction 1 is in the voltage state indicated by the intersection P2. For example, assuming that logic information "1" is stored in this memory cell, first, to write or rewrite logic "1" into this cell,
For example, the voltage values of the constant voltage sources 6 and 7 connected to the word line 4 and the bit line 5 are both changed from the previous V1 to 2·V1.

Then, from the load line Lo under the steady state up to that point, the load line at this time is a load whose current axis intercept P3 is larger than the critical current value Io of the Josephson junction 1 used. Line L1
Changes to

Therefore, the Josefson junction 1 transitions to a voltage state, and its electrical state moves to a second stable point P4, which is the intersection of the load line L1 and the static characteristic.

After writing or rewriting is completed in this way, when the potentials of the word line and bit line are returned to the potential V1 under the steady state, the voltage state represented by the above-mentioned intersection P4 changes to the path on the static characteristic. Along the same line, we move to the intersection point P2 between the load line Lo and the static characteristic under steady state conditions, but this point P2 is still in the voltage state, so logic "1" information is stored in this Josephson memory cell. That means that.

Regarding this write or rewrite operation, it is also necessary to consider what is generally called a half-selected state. That is, only one line is at the write potential 2.V1.

Even under this half-selected state, if a logic "1" is written to a memory cell that was a logic "0", or conversely, a memory cell that had stored a logic "1" becomes a logic "0". If it is changed to , the two-line matching selection method is not satisfied. In other words, in a two-line coincidence selection scheme, a single word line and a single bit line must be specified and only the single Josephson storage cell at their intersection must be addressed.

However, in the Josephson storage cell of the present invention,
As mentioned above, by appropriately selecting the voltage value V1 of the constant voltage source under steady state conditions, only one of the voltages becomes 2·V1, as shown in FIG. It can be designed so that the current axis intercept P5 of the load line L2 at that time does not exceed the critical current value Io.

Therefore, a memory cell that stores a logic "0" will not change to a logic "1" due to half selection, and a memory cell that was a logic "1" will not change to a logic "1".
Under the half-selected state, the stable point P under the steady state
2 to a stable point P6 in the voltage state on the virtual load line L2, the stored contents do not change in the same way.

Next, the case of writing a logic "0" or rewriting a logic "0" will be explained.

At this time, the voltage values Vw and Vb of both constant voltage sources 6 and 7 connected to the word line and the bit line are both lowered from the voltage value V1 under the steady state to approximately zero. This voltage value 0v can be considered as a third potential, but if this is done, the load line at that time will be concentrated only at the origin O on the current Ij-voltage Vj characteristic in FIG.

Therefore, regardless of whether the Josephson memory cell stores "1" or "0" under steady state, the Josephson junction of the memory cell is only in the zero voltage state. It becomes stable.

Therefore, even if both constant voltage sources 6 and 7 are returned to the voltage value V1 under the steady state, only a deviation from the origin O along the current axis Ij based on the static characteristics occurs, so that the voltage in the Josefson memory cell concerned Josephson junction 1 maintains a state in which logic "0" is written.

Furthermore, even if you are in a half-selected state at this time, there is no need to worry at all. For example, even if only the voltage value of one constant voltage source 6 or 7 becomes Ov, the load line at that time becomes the virtual load line indicated by the symbol L3 in FIG. 3, and the load line in the steady state
If the logic "0" is held on Lo as shown by the current axis intercept P1, that point simply changes to the intersection P7 of the load line L3 and the current axis Ij, and the logic "0" is changed. Even if the logic "1" is stored as indicated by the intersection P2 on the load line Lo, the logic will be retained by simply moving temporarily to the intersection P8 on the load line L3. There is no change in the fact that "1" continues to be held.

Thus, it can be seen that in the Josephson memory cell of the present invention, selective writing to the memory cell based on two-line coincidence is possible by simply adopting a simple design measure.

Next, an example of a reading method will be described.

FIG. 4 shows whether the Josefson junction 1 is in a logic "1" state, that is, a voltage state, or a logic "0" state, that is, a zero voltage state, at the output terminal 1.
Sensor part 1 for extracting voltage changes on 8
0 is shown.

The bit line 5 is connected to the primary winding 12 of a superconducting transformer 13 in the sensor section 10, and a Josephson switching element 11 used as a kind of analog switch is interposed in the line.

This is to open the line under the steady state and write mode mentioned above and prevent it from affecting the readout sensor section, and in the case shown in the figure, the voltage is Although shown as a single-type Josephson junction that transitions between states, the present invention is not limited to this, and may be a SUQID type element that can be controlled from the outside or other devices.

The equivalent inductance of the superconducting transformer 13 and the resistor 14 connected in series constitute a high-pass LC filter, and the Josephson element 17 for detection connected in parallel with these is connected to the bias power supply 16 A bias current is applied through the resistor 15 in synchronization with the read operation,
When the bias current is supplied, the superconducting transformer is placed in a state where it can transition to a voltage state with a minute current input pulse from the superconducting transformer side.

In the read operation, first, the bit line constant voltage source 7
The process begins by disconnecting the bit line 5 from the bit line 5, as schematically indicated by switch 19. This action is
Corresponds to selection.

At this time, the switch 11 interposed between the bit line 5 and the sensor section 10 is closed, and a plurality of Josephson junctions 1 are connected to the bit line 5 (for simplicity, only one is shown). (only shown), current flows only from the constant voltage source 6 for the word line corresponding to the one that is transitioning to a voltage state, that is, the one that stores logic "1", to the primary winding of the superconducting transformer 13. It flows into line 12.

However, at this point, since the timing is different from the next read signal, the state of the output terminal 18 is not monitored or no bias current is applied from the bias power supply, and in any case, no meaningful read result is output. Never.

Under these conditions, if one memory cell is selected by selecting one word line and the voltage value of only that word line is set to 2.V1, if the selected memory cell is in the zero voltage state, the corresponding Since a change corresponding to the change in voltage does not cause any change in the readout sensor 10, the output terminal 18
A read result of logic "0", which is approximately ground potential, is obtained regarding the voltage value, but if the selected memory cell is in the voltage state and stores logic "1", the read result of the logic "0" of the selected word line is obtained. The change in current value caused by setting only the voltage value to 2·V1 is detected as a current pulse from the superconducting transformer 13 via a high-pass filter, and is superimposed on the bias current of the Josefson junction 17 to convert it into a voltage state. This causes a significant voltage value to be displayed at the output terminal 18.

As described above, it can be seen that according to the Josephson memory cell of the present invention, reading is also possible by the two-line matching method, but it is also a desirable advantage that the reading can be performed non-destructively. be.

Of course, those skilled in the art can also modify the known existing Josefson circuit technology to detect the difference in the current value output depending on the memory content of the selected memory cell using other methods. In this sense, the illustrated case is merely an example.

<Effects of the Invention> As detailed above, according to the present invention, selection based on two-line matching is possible due to the extremely simple and compact configuration that requires only one Josephson junction and two resistors. This makes it possible to provide Josephson memory cells, which can greatly contribute to future improvements in the degree of integration and signal processing speed in Josephson integrated circuits.

[Brief explanation of drawings]

FIG. 1 is a schematic equivalent circuit diagram of a basic embodiment of the Josephson memory cell of the present invention, FIG. 2 is an explanatory diagram of the operation of the Josephson junction used in the Josephson memory cell of the present invention, and FIG. 3 is an implementation of the present invention. FIG. 4 is an explanatory diagram of the write operation in the example, and FIG. 4 is a schematic configuration diagram of an example of the configuration of the read sensor section for the read operation in the embodiment of the present invention. In the figure, 1 is a Josefson junction, 2 and 3 are resistances,
4 is a word line, 5 is a bit line, 6 is a word line voltage source, 7 is a bit line voltage source, 10 is a read sensor section, 11 is a Josephson switching element,
13 is a superconducting transformer, 14 is a resistor for forming a high-pass filter, 16 is a bias power supply, 17 is a Josefson element, and 18 is an output terminal.

Claims (1)

[Claims] 1 Consists of: a Josephson junction whose one end is connected to a common reference potential; and two resistors whose respective ends are connected to the other end of the Josephson junction; A Josephson memory cell characterized in that the other end of the resistor is connected to a word line, and the other end of the other resistor is connected to a bit line.