JPH0334156B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a magnetic flux quantum memory memory cell comprising a superconducting closed loop including a Josephson element.

[Conventional technology]

There are various types of this type of magnetic flux quantum memory memory cell, but among them, one that can be accessed with two wires,
A conventional example shown in FIG. 5 has excellent features such as the fact that the driving pulse can be unipolar.

The present applicant filed a patent application for this patent as Japanese Patent Application No. 1981-81314, and it was disclosed in Japanese Patent Application Laid-open No. 199492-1988, and the publication was decided on January 14, 1985.

The memory cell shown in FIG. 5 has two Josephson switch sections 3 and 4 in the superconducting closed loop 2, and the two Josephson switch sections 3 and 4 are distributed to left and right branch circuits 2L and 2R. The circuit current lines 1 and 6 are connected to the superconducting closed loop 2, and the inductances of both branch circuits 2L and 2R are made different, and the branch circuit 2L is provided with a relatively small inductance. The control line 5 for controlling the critical current value is inductively coupled to the switch section 3.

In particular, in the illustrated example, the inductance in the left branch circuit 2L is shown as not significantly present, whereas the right branch circuit 2R has a sufficiently large inductance, which is inserted in series. is represented by an inductor 8.

A resistor 9 placed in parallel with this inductor 8 and a resistor 9' placed in parallel with the cell itself are damping resistances that adjust the dynamic characteristics of this memory cell.

Further, one Josephson switch section 3 may be a single junction Josephson element or a SQUID (magnetic flux quantum interference device) depending on the design. Therefore, in FIG. 5, regarding this Josephson switch portion 3, the Josephson single junction notation, which is normally indicated by an "x" mark, is shown surrounded by a square.

[Problem that the invention seeks to solve]

The operation of the conventional magnetic flux quantum memory memory cell shown in _FIG . , Therefore, as shown by the virtual line in FIG. 5, the logical value "1" or "0" is selectively expressed as the memory content depending on whether the associated persistent current i is flowing or not. It is.

However, what we would like to improve in the present invention is the operational timing relationship in the cell shown in FIG.

That is, in this cell, the application timing relationship of the applied currents Ix and Iy is different during write operation and read operation, and for example, if persistent current i flows in the superconducting closed loop, it corresponds to logical "1". , to write the logical value "1", after flowing a current Ix of a specific value or more to the control line 5,
The sequence is such that the current Iy in a specific value range is passed from the circuit current line 1 to the line 6. Conversely, in the case of reading, the current Iy in the specific value range is first applied.
After Iy is flowing, a current higher than a specific current value
This is the order in which Ix is given.

However, this conventional example was created with one major purpose of reducing the number of wires around the cell, and as a result of achieving this purpose, it was possible to reduce the number of wires around the cell to just two wires. As a result of this successful reduction, it became necessary to use different timings for writing and reading, and in this sense, the need for different current application timings for writing and reading is also Also, it is unavoidable.

However, from the standpoint of increasing the speed of memory operation and simplifying the peripheral circuit system, the fact that two different timings are required as described above means that
It will only become a hindrance, not an advantage. If possible, eliminate the concept of timing (current
I want either Ix or Iy to come first), or I want to always have a constant relationship.

In addition to such timing problems, the conventional example shown in FIG. 5 still has room for improvement from other viewpoints.

That is, in the memory cell, the second Josephson switch unit 4 must operate in a contradictory relationship, such as not switching during writing and switching during reading. In order to be satisfied, we have no choice but to sacrifice operating margin.

The present invention has been made in view of these points,
By improving or modifying the conventional example shown in FIG. 5, which essentially has many advantages, and eliminating its drawbacks, we aim to provide a magnetic flux quantum memory memory cell with fewer timing-related constraints and a large operating margin. It is something to do.

[Means for solving problems]

In order to achieve the above object, the present invention provides the following configuration.

Two Josephson switch sections are provided in the superconducting closed loop; circuit current lines are connected to the superconducting closed loop so that the two Josephson switch sections are distributed to left and right branch circuits; In addition to making the inductance different; Among the two Josephson switch sections, a control line that controls the critical current value is inductively coupled to the Josephson switch section in a branch circuit with a relatively small inductance. A magnetic flux quantum memory memory cell characterized in that: a control line for controlling the critical current value is also inductively coupled to a Josephson switch part in a branch circuit with a relatively large inductance; .

[Effect]

According to the above configuration, it is possible to determine in advance whether or not to flow a control current to the control line inductively coupled to the Josephson switch section provided in a branch circuit with relatively large inductance, or to determine in advance the value of the control current. By selecting one of the two predetermined values, the critical current value of the Josephson switch section can be made variable between the write mode and the read mode.

That is, if the critical current value of the Josephson switch part in the branch circuit corresponding to the relatively large inductance is set to a relatively large critical current value in the write mode and a relatively small critical current value in the read mode, The timing relationship between the control current for the other Josephson switch section and the circuit current applied to the superconducting closed loop is not limited to a specific one, and writing and reading can be performed at any timing relationship or depending on the circuit configuration. It can be done in a well-defined and fixed timing relationship.

Therefore, the control current for making the critical current value variable between writing and reading can be called a mode specifying current, and the control line for flowing this current can be called a mode specifying line.

In other words, according to the present invention, by adding only one control line to the memory cell of the conventional example shown in FIG. 5, the drawbacks of the conventional example can be overcome. It can be said that the operating margin was also improved.

Furthermore, in the memory cells of the present invention, when a two-dimensional memory space is constructed using a plurality of memory cells, the presence of the mode designation line can be used to set other half-selected memory cells to read mode at the time of writing. , it is also possible to easily adopt a matching selection method for only cells with specific bits.

〔Example〕

FIG. 1 shows a schematic configuration of a preferred embodiment of a magnetic flux quantum memory memory cell according to the present invention. In contrast to the conventional memory cell described above,
Components that do not require any particular modification are given the same reference numerals as in FIG.

First, to explain the structure of this memory cell 10, the Josephson switch parts 3 and 4 have a switching function similar to that of a single-junction Josephson device.
For the superconducting closed loop 2 including
For the connection points 1a and 6a defined on the superconducting closed loop 2, the circuit current lines 1 and 1 on the input side and the output side are respectively distributed to
6 is connected.

Of the left and right branch circuits 2L and 2R, in the case shown in the figure, a relatively large inductance is provided to the right branch circuit 2R, as shown by an inductor 8.

On the other hand, the left branch circuit 2L preferably has no significant inductance in its line. In practice, as will be explained in detail later,
This is suppressed to such an extent that only the equivalent inductance of the Josefson switch section 3 is present.

Note that the branch circuit is also called a branch in this type of technical field.

Each Josephson switch section 3, 4 may be composed of only a single-junction Josephson device as described above, but it is preferable to use a three-junction or two-junction SQIUD as shown in FIG. 2 or 3. It is preferable to have a skid (magnetic flux quantum interference device) configuration or a multi-junction skid configuration.

Therefore, in the drawing, the Josephson switch parts 3 and 4 are shown by surrounding the usual Josephson single junction notation indicated by an "x" in a square, as in the description of the conventional example above. This indicates that the element may be a single-junction Josephson element or a skid element including multiple junctions.

For example, the threshold characteristic of a three-junction skid having three Josefson junctions J1, J2, and J3 as shown in FIG. 2A is as shown in FIG. 2B.

When the control current Ic is not flowing, the critical current value Io regarding the gate current or circuit current Ig is the maximum value Iomax, and if the value of the control current Ic is increased positively or negatively within a certain range, it will eventually reach the minimum critical value. The current value reaches Iomin.

First, let us consider an embodiment in which the three-junction skid shown in FIG. 2 is used to construct Josephson switch sections 3 and 4 in FIG. 1.

In the present invention, as in the conventional example shown in FIG. ,
Right branch circuit 2R with relatively large inductance
A dedicated control line 15 is also inductively coupled to the Josefson switch section 4 inside.

For convenience of explanation, hereinafter, the Josephson switch section 3 in the left branch circuit 2L will be referred to as the first Josephson switch section 3, and the Josephson switch section 4 in the right branch circuit 2R will be referred to as the second Josephson switch section 4. called,
Similarly, the corresponding control lines are called a first control line 5 and a second control line 15.

Then, in the threshold characteristic shown in FIG.
Regarding the second Josephson switch section 4, the control current flowing through the control line 15 can be replaced with Iy', and the critical current value Io of the first Josephson switch section 3 is Io1. In other words, that of the second Josephson switch section 4 can be read as Io2.

Of course, the circuit current Ig is the current flowing through each Josefson switch section, that is, the current flowing through the circuit current lines 1 and 6.

Therefore, when a sufficiently large X control current Ix is applied to the first control line 5, the first Josephson switch section 3
The critical current value is the maximum critical current value when the control current Ix is not flowing, that is, when Ix = 0, based on the explanation regarding Fig. 2B.
It decreases from Io1max and shifts to the minimum critical current value Io1min when the control current value Ix=X is greater than or equal to a specific value.

Similarly, when a sufficiently large Y control current Iy'=Y' is passed through the second control line 15, the critical current value Io2 of the second Josephson switch section 4 becomes the maximum critical value when Iy'=0. The current value decreases from the current value Io2max and shifts to the minimum critical current value Io2min.

However, the minimum critical current value Io1min for the first Josephson switch section 3 and the minimum critical current value Io2min for the second Josephson switch section 4 are as follows.
They are not necessarily the same value. Rather, it may be more common to make them different, as in the design example described later.

The damping resistor 9 that is placed in parallel with the inductor 8 and the damping resistor 9' that is placed in parallel with the cell 10 itself adjust the dynamic characteristics of the memory cell 10 of this embodiment. Although it is not an essential constructor, in an actual design example, an advantageous range for its value should be considered.

Moreover, the difference in inductance between the left branch circuit 2L and the right branch circuit 2R is that the connection point 1a where the circuit current lines 1 and 6 are connected to the superconducting closed loop 2,
Although it can be adjusted or changed depending on the geometrical position of 6a, in this embodiment, as mentioned earlier, the asymmetry is strengthened so that the difference in inductance between the left and right branch circuits is as large as possible. It is arranged as follows. If I had to say so, the degree is such that almost all the inductance L as the superconducting closed loop 2 is absorbed by the inductor 8 shown in the right branch circuit 2R.

The operation of the magnetic flux quantum memory memory cell 10 will be explained below with reference to an example of a design policy.
4, among the maximum and minimum critical current values that can be considered individually as mentioned above, the important ones for design are the minimum critical current values Io1min and Io2min, and the maximum critical current values Io1max and Io2max. It is better if it is larger than a certain level.

From the previous promise, each minimum critical current value Io1min,
The values of each control current Ix and Iy' giving Io2min are X and Y', respectively.

Here, the inductance of superconducting closed loop 2 is L
Then, one magnetic flux quantum is set to Φ ₀ , and in relation to these, L Io2min=0.5~2Φ ₀ ...1) is designed. Here, for example, L Io2min=Φ ₀ ...2) is selected.

On the other hand, the minimum critical current value Io1min for the first Josephson switch section 3 is selected to be Io1min=0.1 to 1.0Io2min...3). Similarly, here, for example, it is assumed that Io1min=0.4Io2min...4).

However, during the write operation, the control current Iy' is not passed through the control line 15, so Iy'=0, and the critical current value of the second Josephson switch section 4 is set at the maximum critical current value Io2max.

As mentioned earlier, this maximum critical current value
If the second Josephson switch section 4 is designed and manufactured so that the value of Io2max is sufficiently large,
During the write operation described below, it is possible to create a condition in which the second Josephson switch section 4 does not change to the voltage state at any time, and therefore, the present memory cell 10 also does not change to the voltage state. It can be made so that there is no such thing.

To write a logical value of "0" under such a condition, the value of the circuit current Iy supplied to the first Josephson switch section 3 in the left branch circuit 2L is set to zero (Iy=0), and the control line 5 is written. The value of the control current Ix to be flown is assumed to be the previously mentioned X (Ix=X).

However, the timing of adding the circuit current Iy where Iy=0 and the control current Ix where Ix=X is not specified, and either one may be added first.

In this way, from equations 2) and 4) mentioned above, L Io1min = 0.4Φ ₀ ...5), and the superconducting closed loop 2 can no longer store one magnetic flux quantum inside it, so A logical value "0" is stored.

On the other hand, in order to write the logical value "1", the circuit current Iy=Y and the control current Ix=X is added. However, at this time as well, there is no particular timing for applying the voltage, and it may be applied either first.

If the state of the superconducting closed loop 2 before this writing operation is a storage state of logical "0", no persistent current i flows in the superconducting closed loop 2.

Therefore, the circuit current Iy having the value Y flows through the first Josephson switch section 3 as it is. Therefore, if Y>Io1min...6) is selected, the first Josephson switch section 3 will transition to the voltage state, and the circuit current Iy will be commutated to the second Josephson switch section 4, As a result, the first Josephson switch section 3 returns to the zero voltage state again.

After such a state occurs, if the control current Ix is returned to zero and the circuit current Iy is also returned to zero (this timing is always the same), a persistent current i corresponding to one magnetic flux quantum Φ ₀ remains in the superconducting closed loop 2. , the logical value "1" is stored as expected.

On the other hand, when the currents Iy = Y and Ix = The magnitude of the current flowing through the first Josephson switch section 3 is effectively (Yi)
becomes. Therefore, if (Y-i)<Io1min...7), the first Josephson switch section 3 will not change to the voltage state, and the contents of the memory cell 10 will remain in the storage state of the logical value "1". keep. This is equivalently the same result as after writing a logical value "1".

Therefore, regarding writing, 6) above,
From equation 7), it can be seen that the value Y of the circuit current Iy should be kept within the following range.

Io1min<Y<Io1min+i...8) Also, as is clear from the above mechanism, the maximum critical current value Io2max of the second Josephson switch section 4 during writing may be set to a value sufficiently larger than the above value Y.

Next, the read operation will be explained. In this mode, the value of the current Iy' flowing through the second control line 15 is set as Y', and the critical current value of the second Josephson switch section 4 is sufficiently reduced to the minimum critical current value Io2min.

Based on this, the circuit current Iy=Y and the first control line 5
Control current Ix=X is applied to. Whichever comes first is fine.

Then, as mentioned above, if the value Y of the circuit current Iy is selected within the range of the above formula 8), the first Josephson switch section 3 will change the memory content of the memory cell 10 to the logical value "1". If it is, it does not switch to the voltage state, but only if it is "0",
Transition to voltage state.

When the first Josephson switch unit 3 transitions to the voltage state with respect to the memory content logical value "0", the circuit current Iy flows into the right branch circuit 2R, and the critical current value is reduced to the minimum critical current value Io2min. The second Josephson switch section 4 is brought into a voltage state. Therefore, the memory cell 10 also transitions to a voltage state.

In this way, with regard to reading, the memory content is read based on whether or not the memory cell 10 itself changes to a voltage state according to the memory content, without particularly considering the relationship between the application timing of the circuit current Iy and the control current Ix. be able to.

Note that the peak value of the current flowing into the second Josephson switch section 4 due to the transition of the first Josephson switch section 3 to the voltage state is generally determined by adjusting the damping resistors 9 and 9' to the circuit current Iy. It can be larger than the value.

Therefore, the circuit current Iy is smaller than the minimum critical current value Io2min of the second Josephson switch section 4.
Even if the voltage is low, the transition to the desired voltage state can occur.

Furthermore, if further practical considerations are given to the above-mentioned readout, non-destructive readout is preferable. However, the circuit system itself for this purpose is not directly defined by the present invention, and for example, the circuit structure disclosed in Japanese Patent Application Laid-open No. 1984-199492 mentioned above regarding the conventional example may be used. be able to.

That is, after reading the logical value "1",
First, the value of the control current Ix is set to zero, then the value of the circuit current Iy is set to zero, and conversely, after reading the logic value "0", the value of the circuit current Iy is first set to zero, and then the value of the control current is set to zero.
All you have to do is build a circuit system that automatically sets the value of Ix to zero.

In the first embodiment of the present invention, the three-junction skid shown in FIG. 2 was used for the first and second Josephson switch parts 3 and 4. Next, an embodiment will be described in which a two-junction skid shown in FIG. 3 is used for the second Josephson switch section 4.

The skid whose configuration is shown in Figure 3A is an existing one called an asymmetric two-junction skid, in which the inductance L2 in one branch circuit is much larger than the inductance L1 in the other branch circuit. It's made to grow.

Then, the critical current value Io (J2) of Josephson element J2 in the branch circuit with larger inductance is:
It is larger than the critical current value Io (J1) of Josephson element J1 in the branch circuit with smaller inductance.

In such a skid, if (L1 + L2) × {Io (J1) + Io (J2)}/2 = 0.3~0.4Φ ₀ ...9) is chosen, the control current will change as shown in Figure 3B.
When Ic = 0 or in the vicinity thereof, the critical current value becomes the lowest or minimum value Iomin, and conversely, when it takes a significant value in the positive and negative directions, it reaches the maximum value Iomax, resulting in a dichotic-like threshold characteristic.

Therefore, if the asymmetric two-junction skid shown in FIG. 3 is used for the second Josephson switch section 4 in FIG. The read/write mode specifying current Iy' to be applied specifies a read operation when Iy'=0, and specifies a write operation when Iy'=Y'.

Therefore, as will be described later, when a two-dimensional memory space is constructed using a plurality of memory cells of the present invention and a match selection method is adopted for each address, the skid shown in FIG. In the case of the memory cell used in the second Josephson switch section 4, even if all other memory cells in the half-selected state other than those selected coincidentally are set to the read mode, power is consumed regarding the second control line 15. This is desirable because it will never happen.

However, other related operations can be considered in almost the same way as in the first embodiment, and the first control current Ix, circuit current Iy, damping resistor, etc. Therefore, an appropriate value can be set.

Further, Josephson switch circuits other than those shown in FIGS. 2 and 3, such as skids containing more single-junction Josephson elements, are also applicable to the Josephson switch circuit of the memory cell of the present invention. It is possible to use it as the switch parts 3 and 4. The reason why the skids in FIGS. 2 and 3 are specifically mentioned is because, as mentioned above, the current value relationship between them happens to be reversed with respect to the control current Iy' or the mode specified current Iy'. This is to prove that the present invention can be effectively implemented in either case.

When a two-dimensional memory space is configured using a plurality of memory cells of the present invention, if a certain control line 5 is selected and a control current or X selection current Ix is passed through it, the control line is The word selection configuration is such that all memory cells connected to a certain X row operate.

Of course, there is no problem if this is acceptable, but there may be cases where matching selection in which only specific X-Y intersections or bits are selected is desirable.

In such a case, one auxiliary control line may be added in a direction perpendicular to the control line 5, and the corresponding first Josephson switch section may be driven by the AND operation of the currents flowing through both of them. If this is done, the effect of increasing the operating margin provided by the present invention will be somewhat reduced, the manufacturing will be complicated, and there will be disadvantages in terms of size.

Therefore, as a match selection method that does not have these drawbacks, the method described below is effective.

The feature of this method is that when the memory cell according to the present invention is used in the circuit configuration disclosed in the above-mentioned publication, it automatically becomes non-destructive read. The problem is that a read operation is performed on the selected bit.

The fourth example of a memory space configuration that realizes this method is
The operation timing is shown in Figure A.
Shown in Figure B. In FIG. 4A, each of the cells C11 to C44 indicated by squares can be considered to have the same configuration as the memory cell 10 as the embodiment of the present invention shown in FIG.

In this case, the four X selection lines 5-1, 5-2, 5-3, and 5-4 extending from the X selection circuit 30 are as follows:
Similarly, four mode specifying current lines 15-1, 15-2, 15- extend from the Y selection circuit 40, each corresponding to the control current line 5 in FIG.
3 and 15-4 correspond to the second control line or mode designation line 15 in FIG. 1, respectively.

Memory cells C11 and C2 included in the same Y column
1, C31, C41; ~; C14, C24, C3
4 and C44 are connected in series with current lines corresponding to circuit current lines 1 and 6 in FIG. 1, respectively, and one circuit current line 11- for each column.
1, 16-1,; ~; 11-4, 16-4 are configured.

Below, the subscript of each code is “-j; j=1, 2,
3,4", each circuit current line 11-
j, 16-j, a Josephson gate 20-j for reset is inserted in series with each series cell, and a Josephson gate 21-j for setting is inserted in parallel thereto.

Each gate may be a single-junction Josephson device or a skid configuration, but the reset Josephson gate 20-j is provided with a control line 23-j for selectively switching it. A control line 24-j for selectively switching the gate 21-j is also arranged.

Under such a memory space configuration, when a DC supply current is passed through the circuit current lines 11-j and 16-j, the four cell columns and the reset gate 20
Since the line including -j has a large inductance, most of its supply current first flows into the setting gate 21-j. This state is the initial state.

However, when a set pulse is applied to the set gate 21-j to change it to a voltage state, the supply current flows into the cell column and becomes a Y selection current corresponding to the circuit current Iy in FIG.

In this case, the current flowing into the setting gate 21-j becomes almost zero, so the current flowing into the setting gate 21-j becomes almost zero.
1-j automatically returns to the zero voltage state.

As an example, a write operation to the memory cell C32 will be explained.

In this circuit system, all memory cells belonging to columns other than the second column in the Y direction including the memory cell C32 are placed under read mode designation. It is assumed here that each memory cell has a three-junction skid shown in FIG. 2 in its Josephson switch portion.

First, the mode specifying current lines 15-1, 15-3, and 15-4 other than the control line or mode specifying current line 15-2 related to the second column in the Y direction have a current Iy'= Y′ is given.
In other words, all the memory cells other than the memory cells belonging to the second column in the Y direction are placed in the read mode as described above.

Under this condition, the target memory cell C32
When writing a logical value “1” to
While flowing, select the X selection line 5- in the third row in the X direction.
3 is supplied with selection current Ix=X.

Then, the X selection line 5-3 in the third row in the X direction
Other memory cells C31, C33, C3 connected to
4, since the read mode command is given, the read operation is performed, and the intended write operation is performed only in the target memory cell C32. If the currents Ix and Iy' are then returned to zero, one write operation is completed. Either of the currents Ix and Iy′ can be returned first.

It should be noted here that in this circuit system, it is not necessarily necessary to operate the reset gate 20-j every time the above write operation is performed.

Indeed, the control line 23- attached to the reset gate
Applying a reset pulse to gate 20-j
If the voltage state is changed to the voltage state, the circuit current is returned to the setting gate 21-j, and the initial state is completely restored, but there is no particular need to do so.

Further, in the case of the memory cell of the present invention, since the read operation is non-destructive as described above, the storage contents of the half-selected bits of the memory cell will not be changed before or after the end of the operation.

When writing "0", the reset gate 20-2 belonging to the second column in the Y direction is connected to its control line 20-2.
By applying a reset pulse to 3-2, the voltage state is changed, and the supply current is applied to the set gate 2.
By bypassing the current to the 1-2 side, a state equivalent to effectively reducing the circuit current Iy to zero is realized.

On the other hand, a set pulse is applied to the set gates in each of the other columns in the Y direction, causing them to transition to a voltage state, and causing a circuit current Iy=Y to flow into each cell column.

Under such conditions, when selection current Ix=X is supplied to the X selection line in the third row in the C
Only at 32 is a logical "0" written as expected. After that, the currents Ix and Iy′ are returned to zero regardless of the order, and each time
Finish the write operation.

In this way, the desired logic value "1" or "0" is written in a two-line matching manner, and the contents of other unselected memory cells do not need to be changed.

Next, the read operation will be explained. Again, the target memory cell is C32.

In this read operation, first, a set pulse is applied to all the Josephson gates 21-j for setting, and by making them all transition to a voltage state, the circuit current Iy=Y is applied to all the columns in the Y direction. be swept away.

Further, a read mode specifying current Iy'=Y' is applied to all mode specifying lines 15-j, and all Y-direction columns are placed in the read mode.

However, on the other hand, Josephson gate 2 for each set
In the group of sensing Josephson gates 22-j each inductively coupled to the current line on the 1-j side, Y including the target memory cell C32
Josefson gate 22 for sense of direction column
The gate current specified by the Y selection circuit 40 is applied only to -2.

However, this alone does not switch the sense Josephson gate 22-2. This is because, at this time, the supply current Iy=Y has already flowed into each cell column and its corresponding reset gate by the switch of the set gate.

However, when the selection current Ix =
If the logic value "0" is stored, it is switched, and therefore the circuit current Iy is set at the gate 21-2.
being chased back to the side.

Therefore, the sensing gate 22-2 detects this return current and indicates that the stored content of the target memory cell C32 is a logic value "0" by making a transition to the voltage state.

Of course, other memory cells C31, 3C33, C3 connected to the selected X selection line 5-3
4 also performs a read operation simultaneously with the read operation of the memory cell C32, but sense gates 22-1, 22-3, and
Since no gate current is applied to 22-4, no significant output signal is generated.

Therefore, it can be configured to take the logical sum of all the sensing gates, and the contents can be read out only from the memory cells that are matched and selected at that time.

Note that, as is clear from the above operations, when such a memory space configuration and its operating method are adopted, the number of read operations increases considerably under actual operation.

Therefore, although the three-junction skid shown in FIG. It is advantageous to adopt the two-junction asymmetric skid configuration shown in FIG. 3, which allows the specified current Iy' to be 0 when specifying the read mode, for the Josephson switch section 4.

〔Effect of the invention〕

As described above in detail, the magnetic flux quantum memory memory cell of the present invention can easily provide operation with fewer constraints on the timing relationship during writing and reading. As far as current components directly involved in writing and reading are concerned, it can be said that such a limited timing relationship does not exist in principle.

Moreover, since there is no need to generate contradictory operating elements, the operating margin can essentially be increased.

Furthermore, even when this memory cell is assembled in a two-dimensional memory space, the coincidence selection method can be easily adopted by effectively utilizing the principle of non-destructive read operation.

Of course, since the structure itself is simple and can be accessed with just three wires, high-density design is not compromised, and it is expected that it will greatly contribute to the realization of high-speed, large-capacity memory in the future.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram of a preferred embodiment of a magnetic flux quantum memory memory cell according to the present invention, and FIG. 2 is a diagram showing the structure of a Josephson switch used in the memory cell according to the embodiment of the present invention shown in FIG. FIG. 3 is an explanatory diagram of a two-junction asymmetric skid as another example that can be used in the Josephson switch section in the memory cell of the embodiment of the present invention. FIG. 4 is an explanatory diagram of a three-junction skid that can be used. FIG. 5 is an explanatory diagram of the configuration and operation when the memory cell of the present invention is assembled in a two-dimensional memory space, and FIG. 5 is a schematic diagram of the configuration of a conventional magnetic flux quantum memory type memory cell to be improved by the present invention. In the figure, 1 and 6 are circuit current lines, 2 is a superconducting closed loop, 2L is a left branch circuit, 3 and 4 are Josephson switch parts, 5 is a first control line, 8 is an inductor,
9 and 9' are damping resistors, 10 is the magnetic flux quantum storage memory cell of the present invention as a whole, 15 is a second control line or write/read mode designating current line, 5-j is an X selection line, 11-j, 16-j is a circuit current line or Y selection line, 15-j is a write/read mode specifying current line, 20-j is a Josephson gate for reset, 21-j is a Josephson gate for setting, and 22-j is a Josephson gate for setting. Josephson gate for sense, 23-j is a control line for applying a reset pulse, 24-j is a control line for applying a set pulse,
30 is an X selection circuit, and 40 is a Y selection circuit.

Claims (1)

[Claims] 1. Two Josephson switch sections are provided in the superconducting closed loop; a circuit current line is connected to the superconducting closed loop so that the two Josephson switch sections are distributed to left and right branch circuits. In addition to making the inductance of the above two branch circuits different, the critical current value is set for the Josephson switch section in the branch circuit whose inductance is relatively small among the two Josephson switch sections. The control line for controlling the control line is inductively coupled; and the control line for controlling the critical current value is also inductively coupled to the Josephson switch part in the branch circuit, which has a relatively large inductance. Magnetic flux quantum memory memory cell.