JPH033415B2 - - Google Patents
Info
- Publication number
- JPH033415B2 JPH033415B2 JP19898784A JP19898784A JPH033415B2 JP H033415 B2 JPH033415 B2 JP H033415B2 JP 19898784 A JP19898784 A JP 19898784A JP 19898784 A JP19898784 A JP 19898784A JP H033415 B2 JPH033415 B2 JP H033415B2
- Authority
- JP
- Japan
- Prior art keywords
- wave device
- resistance band
- acoustic wave
- constant voltage
- surface acoustic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000010408 film Substances 0.000 claims description 27
- 239000000758 substrate Substances 0.000 claims description 16
- 238000000605 extraction Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 13
- 239000010409 thin film Substances 0.000 claims description 8
- 238000010897 surface acoustic wave method Methods 0.000 claims description 7
- 239000012535 impurity Substances 0.000 claims description 6
- 239000003990 capacitor Substances 0.000 claims description 5
- 230000000903 blocking effect Effects 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 4
- 229910052787 antimony Inorganic materials 0.000 claims description 3
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052797 bismuth Inorganic materials 0.000 claims description 3
- JCXGWMGPZLAOME-UHFFFAOYSA-N bismuth atom Chemical compound [Bi] JCXGWMGPZLAOME-UHFFFAOYSA-N 0.000 claims description 3
- 239000011195 cermet Substances 0.000 claims description 3
- 238000010894 electron beam technology Methods 0.000 claims description 3
- 229910001120 nichrome Inorganic materials 0.000 claims description 3
- 229910052715 tantalum Inorganic materials 0.000 claims description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- 238000009966 trimming Methods 0.000 claims description 3
- 230000003993 interaction Effects 0.000 description 11
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 8
- 239000013078 crystal Substances 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 239000011787 zinc oxide Substances 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910004479 Ta2N Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Landscapes
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体基板上に設けられた圧電膜を有
する、モノリシツク型表面弾性波（以下本明細書
においてはSAWと略記する。）装置、特にSAW
コンボルバまたはコリレータに関する。Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a monolithic surface acoustic wave (hereinafter abbreviated as SAW) device having a piezoelectric film provided on a semiconductor substrate, and particularly to a SAW device.
Regarding convolvers or correlators.
〔発明の背景〕
SAWを利用する小型軽量の信号処理機能素子
としてSAWコンボルバやSAWコリレータがあ
る。これらは構造上分離媒質型とモノリシツク型
とに大きく分けられるが、特に生産性や効率の面
からモノリシツク型が有力である。半導体基板と
圧電膜とを組合せたモノリシツク型SAWコンボ
ルバあるいはコリレータにおいて、その信号処理
機能はSAWと半導体表面の空間電荷層との非線
形相互作用によつて生じる。この作用を利用する
ために、従来、第５図および第６図に示す半導体
基板１、絶縁膜３を介してその上に設けられた圧
電膜２、その圧電膜２の表面上の両端近傍に設け
られた信号入力用トランスデユーサ４ａおよび４
ｂおよび処理信号の出力用ゲート電極５を有する
構造が用いられている。第５図中６は裏面電極で
あり、第６図中、７は可変の直流バイアス伝源、
８は直流阻止用コンデンサ、９ａ，９ｂおよび９
ｃは整合回路、１０ａおよび１０ｂは信号源、１
１は信号出力用外部負荷抵抗を表わす。[Background of the Invention] There are SAW convolvers and SAW correlators as small and lightweight signal processing functional elements that utilize SAW. These can be roughly divided into separation medium type and monolithic type based on their structure, but the monolithic type is particularly popular from the viewpoint of productivity and efficiency. In a monolithic SAW convolver or correlator that combines a semiconductor substrate and a piezoelectric film, its signal processing function is generated by nonlinear interaction between the SAW and a space charge layer on the semiconductor surface. In order to utilize this effect, conventionally, as shown in FIG. 5 and FIG. Provided signal input transducers 4a and 4
A structure having a gate electrode 5 for outputting a processed signal and a gate electrode 5 for outputting a processed signal is used. 6 in FIG. 5 is a back electrode, 7 in FIG. 6 is a variable DC bias source,
8 is a DC blocking capacitor, 9a, 9b and 9
c is a matching circuit, 10a and 10b are signal sources, 1
1 represents an external load resistance for signal output.
この構造において、非線形相互作用はゲート電
極５直下の領域で行なわれ（以下本明細書におい
ては、この領域を相互作用領域と呼ぶ。）出力は
ゲート電極５と裏面電極６の間から取り出され
る。相互作用の強さは、半導体基板１表面の相互
作用領域における容量−電圧特性（Ｃ−Ｖ特性）
に依存するから、ゲート電極５と接地されている
裏面電極６間に印加される直流バイアス電圧によ
り大きく変化する。したがつて、従来の方式では
ゲート電極内で加え合わされた総合的な出力が最
大値を示すバイアス電圧を最適バイアスとして、
全相互作用領域に均一に印加し、動作を行なわせ
ることが一般的であつた。 In this structure, nonlinear interaction takes place in a region directly below the gate electrode 5 (hereinafter, this region will be referred to as an interaction region), and the output is extracted from between the gate electrode 5 and the back electrode 6. The strength of the interaction is determined by the capacitance-voltage characteristics (C-V characteristics) in the interaction region on the surface of the semiconductor substrate 1.
Therefore, it varies greatly depending on the DC bias voltage applied between the gate electrode 5 and the grounded back electrode 6. Therefore, in the conventional method, the bias voltage at which the total output added within the gate electrode shows the maximum value is set as the optimal bias.
It was common practice to uniformly apply the voltage to the entire interaction area to cause the operation to take place.
しかし、相互作用領域内のＣ−Ｖ特性は通常均
一ではなく、面内分布を持つから、特に素子の信
号処理能力の向上を図る目的で相互作用領域を長
くする場合など、従来の方式の様に領域全体に対
して均一なバイアス電圧を印加する方法では、前
記Ｃ−Ｖ特性の分布のために印加バイアスが領域
のあらゆる部分に対して最適とは限らなくなり、
素子に最適動作を行なわせる上で無視できない問
題となる。 However, the C-V characteristics within the interaction region are usually not uniform but have an in-plane distribution, so when the interaction region is lengthened to improve the signal processing ability of the device, it is difficult to In the method of applying a uniform bias voltage to the entire region, the applied bias is not necessarily optimal for all parts of the region due to the distribution of the C-V characteristics.
This becomes a problem that cannot be ignored in order for the device to perform optimal operation.
本発明の目的は、全体的な素子の効率を向上さ
せるように、簡単な装置を用いて素子の非線形相
互作用領域におけるＣ−Ｖ特性の分布に合わせて
直流バイアス電圧を分布されることができる。冒
頭に述べた種類のSAW装置を提供することであ
る。
An object of the present invention is that the DC bias voltage can be distributed according to the distribution of C-V characteristics in the nonlinear interaction region of the device using a simple device so as to improve the overall device efficiency. . The object of the present invention is to provide a SAW device of the type mentioned at the beginning.
上記目的を達成するために、本発明による
SAW装置は、半導体基板と、該基板の一表面上
に積層された絶縁膜と、該絶縁膜上に積層された
圧電膜と、該圧電膜上の離れた位置に設けられた
２つの信号入力用トランスジユーサと、上記基板
の他表面に設けられ接地に連ねられる裏面電極
と、上記圧電膜上の上記２つの信号入力用トラン
スジユーサに挟まれた位置に前記２つの信号入力
用トランスジユーサを結ぶ方向に複数個に分割し
て設けられた信号出力用ゲート電極と、前記各信
号出力用ゲート電極に接続され直流阻止用コンデ
ンサを含む出力信号取出手段と定電圧端子とアー
ス端子とを備え、この定電圧端子とアース端子と
の間には所定のシート抵抗を有する抵抗帯が設け
られ、この抵抗帯の長手方向複数個所には上記各
信号出力用ゲート電極に適切なバイアス電圧を与
えるように上記ゲート電極に適宜接続されるバイ
アス電圧取出用タツプが設けられていることを特
徴とする。
In order to achieve the above object, the present invention
A SAW device includes a semiconductor substrate, an insulating film laminated on one surface of the substrate, a piezoelectric film laminated on the insulating film, and two signal inputs provided at separate positions on the piezoelectric film. a rear electrode provided on the other surface of the substrate and connected to ground, and the two signal input transducers on the piezoelectric film at positions sandwiched between the two signal input transducers. A signal output gate electrode divided into a plurality of parts in a direction connecting the users, an output signal extraction means connected to each signal output gate electrode and including a DC blocking capacitor, a constant voltage terminal, and a ground terminal. A resistance band having a predetermined sheet resistance is provided between the constant voltage terminal and the ground terminal, and an appropriate bias voltage is applied to each of the signal output gate electrodes at multiple locations in the longitudinal direction of this resistance band. The present invention is characterized in that a bias voltage extraction tap is provided which is appropriately connected to the gate electrode.
本発明の有利な実施の態様においては、上記半
導体基板はシリコン単結晶またはサフアイア単結
晶の一主面上に形成されたシリコン単結晶であ
り、上記圧電膜は上記シリコン単結晶表面に形成
された二酸化シリコン絶縁層の上に形成された酸
化亜鉛膜または上記シリコン単結晶表面に形成さ
れた窒化アルミニウム膜である。上記出力ゲート
電極の各々と上記バイアス電圧取出し用タツプの
接続は、上記定電圧端子に所定の定電圧を印加
し、所望の電圧が得られる電圧取出し用タツプを
適宜選択して行なわれるか、またはバイアス電圧
の調整が上記抵抗帯をレーザあるいは電子ビーム
を用いてトリミングすることによつて行なわれ
る。抵抗帯はニクロムまたはサーメツト（Cr−
SiO）の真空蒸着膜または窒化タンタル（Ta2N）
のスパツタ膜であるか、またはアンチモン、ビス
マス、またはタンタルから成る金属薄膜である。
さらに、抵抗帯は、半導体基板表面領域に設けら
れた高不純物濃度層で形成されることもできる。 In an advantageous embodiment of the present invention, the semiconductor substrate is a silicon single crystal formed on one principal surface of a silicon single crystal or a sapphire single crystal, and the piezoelectric film is formed on a surface of the silicon single crystal. This is a zinc oxide film formed on a silicon dioxide insulating layer or an aluminum nitride film formed on the silicon single crystal surface. The connection between each of the output gate electrodes and the bias voltage extraction tap is carried out by applying a predetermined constant voltage to the constant voltage terminal and appropriately selecting a voltage extraction tap from which a desired voltage can be obtained; The bias voltage is adjusted by trimming the resistance band using a laser or an electron beam. The resistance band is made of nichrome or cermet (Cr-
Vacuum deposited film of SiO) or tantalum nitride ( Ta2N )
or a thin metal film of antimony, bismuth, or tantalum.
Furthermore, the resistance band can also be formed by a highly doped layer provided in the surface region of the semiconductor substrate.
以下に、図面を参照しながら、実施例を用いて
本発明を一層詳細に説明するが、それらは例示に
過ぎず、本発明の枠を越えることなしにいろいろ
な変形や改良があり得ることは勿論である。 Hereinafter, the present invention will be explained in more detail using examples with reference to the drawings, but these are merely illustrative and it is understood that various modifications and improvements may be made without going beyond the scope of the present invention. Of course.
第１図は本発明によるSAW装置の上面図で図
中第６図と共通する引用番号は第６図におけるも
のと同じ部分を示し、′は本発明によつて複数個
に分割されていることを表わす。第１図に見られ
るように、本発明によるSAW装置においては、
出力用ゲート電極５′は利端近傍に設けられてい
る信号入力用トランスデユーサ４ａと４ｂを結ぶ
方向に複数個に分割されている。素子表面には、
さらに定電圧端子１２およびアース端子１３が設
けられており、それらの端子１２，１３は適当な
シート抵抗を有する薄膜抵抗帯１４で結ばれてい
る。薄膜抵抗帯用材料としては、製造方法が簡便
でかつ適当なシート抵抗を有するものとして、ニ
クロムまたはサーメツト（Cr−SiO）の真空蒸着
膜または窒化タンタル（Ta2N）のスパツタ膜等
が有利である。薄膜抵抗帯１４には適当な間隔で
バイアス電圧取出し用タツプ１５が設けられてい
る。出力ゲート電極５′の各々とバイアス電圧取
出し用タツプ１５の接続は定電圧端子１２に所定
の定電圧を印加し、所望の電圧が得られる電圧取
出し用タツプ１５を適宜選択して行なわれるか、
薄膜抵抗帯１４をレーザあるいは電子ビームを用
いてトリミングすることによつてバイアス電圧の
調整が行なわれる。このようにして、直流バイア
ス電源７から各電極５′直下のＣ−Ｖ特性に対し
て最適なバイアス電圧が印加される。相互作用領
域で処理された信号は分割されたゲート電極５′
直下の領域における信号毎にそのゲート電極で加
え合され、直流電圧を阻止するコンデンサ８′を
介して出力される。
FIG. 1 is a top view of a SAW device according to the present invention. Reference numbers common to FIG. 6 in the figure indicate the same parts as in FIG. represents. As seen in FIG. 1, in the SAW device according to the present invention,
The output gate electrode 5' is divided into a plurality of parts in the direction connecting the signal input transducers 4a and 4b provided near the dominant end. On the element surface,
Furthermore, a constant voltage terminal 12 and a ground terminal 13 are provided, and these terminals 12 and 13 are connected by a thin film resistance band 14 having an appropriate sheet resistance. As materials for thin film resistance bands, vacuum-deposited films of nichrome or cermet (Cr-SiO), sputtered films of tantalum nitride (Ta 2 N), etc. are advantageous because they are easy to manufacture and have appropriate sheet resistance. be. Bias voltage extraction taps 15 are provided on the thin film resistance band 14 at appropriate intervals. The connection between each of the output gate electrodes 5' and the bias voltage extraction tap 15 is carried out by applying a predetermined constant voltage to the constant voltage terminal 12 and appropriately selecting the voltage extraction tap 15 from which the desired voltage can be obtained.
The bias voltage is adjusted by trimming the thin film resistance band 14 using a laser or an electron beam. In this way, the optimum bias voltage is applied from the DC bias power supply 7 to the CV characteristics directly under each electrode 5'. The signal processed in the interaction region is transferred to the divided gate electrode 5'
The signals in the region immediately below are summed at their gate electrodes and output via a capacitor 8' that blocks DC voltage.
抵抗帯はまた、第２図に示すように、アンチモ
ン、ビスマス、タンタル等の金属薄膜であつても
よい。 The resistive band may also be a thin film of metal such as antimony, bismuth, tantalum, etc., as shown in FIG.
さらに、第３図に示すように、抵抗帯を半導体
基板１の中に形成することもできる。第４図は第
３図に示す装置の−′線に沿つて切つた断面
図を示す。半導体基板１の表面に絶縁膜３を形成
する前に、第３図中破線で囲まれた領域に所定の
不純物濃度が得られるように不純物を拡散し、高
不純物濃度領域１７を形成する。絶縁膜３の形成
後、選択エツチングによつて所定の領域に高不純
物濃度領域１７に達する複数の孔を設け、公知の
方法によつて電極を形成する。一方の端の電極は
定電圧端子１２の役をし、他方の端の電極はアー
ス端子１３の役を果す。それらの電極の間にある
電極がバイアス電圧取出し用タツプ１５である。 Furthermore, as shown in FIG. 3, a resistance band can also be formed in the semiconductor substrate 1. FIG. 4 shows a cross-sectional view of the device shown in FIG. 3 taken along line -'. Before forming the insulating film 3 on the surface of the semiconductor substrate 1, impurities are diffused to obtain a predetermined impurity concentration in the region surrounded by the broken line in FIG. 3 to form a high impurity concentration region 17. After forming the insulating film 3, a plurality of holes reaching the high impurity concentration region 17 are formed in predetermined regions by selective etching, and electrodes are formed by a known method. The electrode at one end serves as a constant voltage terminal 12, and the electrode at the other end serves as a ground terminal 13. The electrode located between these electrodes is a bias voltage extraction tap 15.
本発明はモノリシツク型のSAWコンボルバあ
るいはコリレータに関するものであり、半導体基
板１と圧電膜３との層状構造素子を前提としてい
る。ここで素子の動作効率あるいは温度特性、ま
たICとの一体化等を考慮する場合、構造として
はZnO／SiO2／SiまたはZnO／SiO2／Si／Al2O3
あるいはAlN／SiまたはAlN／Si／Al2O3が有利
である。ここで、Al2O3はサフアイアの単結晶、
Siはシリコン単結晶を表わし、ZnOおよびAlNが
圧電膜である。 The present invention relates to a monolithic SAW convolver or correlator, and is based on a layered structure element consisting of a semiconductor substrate 1 and a piezoelectric film 3. When considering the operating efficiency or temperature characteristics of the element, or its integration with an IC, the structure should be ZnO/SiO 2 /Si or ZnO/SiO 2 /Si/Al 2 O 3
Alternatively, AlN/Si or AlN/Si/Al 2 O 3 are preferred. Here, Al 2 O 3 is a single crystal of sapphire,
Si represents silicon single crystal, and ZnO and AlN are piezoelectric films.
以上説明した通り、本発明によれば、モノリシ
ツク型SAWコンボルバまたはコリレータにおい
て、出力用ゲート電極が複数個に分割されている
から、分割されたゲート電極の各々を最小の単位
領域として容易に印加バイアスを調整することが
でき、したがつて素子の非線系相互作用領域にお
けるＣ−Ｖ特性の分布に対し、前記単位領域ごと
にその領域での最適バイアスを選択し、印加する
ことができるので、全体的な素子の効率を向上さ
せることができる。
As explained above, according to the present invention, in a monolithic SAW convolver or correlator, the output gate electrode is divided into a plurality of parts, so that it is possible to easily apply bias to each divided gate electrode as the smallest unit area. Therefore, for the distribution of CV characteristics in the nonlinear interaction region of the element, the optimum bias for each unit region can be selected and applied. Overall device efficiency can be improved.
第１図は本発明によるSAW装置の上面図および
その周辺回路の図式図、第２図および第３図は本
発明の他の二つの実施の態様によるSAW装置の
一部の上面図、第４図は第３図に示す装置の−
′線に沿つて切つた断面図、第５図は従来の
SAW装置の断面図、第６図は従来のSAW装置の
上面図およびその周辺回路の図式図である。
１…半導体基板、２…圧電膜、３…絶縁膜、４
ａ，４ｂ…信号入力用トランスデユーサ、５，
５′…出力用ゲート電極、６…裏面電極、７…直
流バイアス電源、８，８′…直流阻止用コンデン
サ、９ａ，９ｂ，９ｃ…整合回路、１０ａ，１０
ｂ…信号源、１１…信号出力用外部負荷抵抗、１
２…定電圧端子、１３…アース端子、１４…薄膜
抵抗体、１５…バイアス電圧取出し用タツプ、１
６…金属薄膜、１７…高不純物濃度領域。
FIG. 1 is a top view of a SAW device according to the present invention and a schematic diagram of its peripheral circuit, FIGS. 2 and 3 are top views of a part of a SAW device according to two other embodiments of the present invention, and FIG. The diagram shows the equipment shown in Figure 3.
Figure 5 is a cross-sectional view taken along line '.
FIG. 6 is a cross-sectional view of a SAW device, and is a top view of a conventional SAW device and a schematic diagram of its peripheral circuit. 1... Semiconductor substrate, 2... Piezoelectric film, 3... Insulating film, 4
a, 4b...transducer for signal input, 5,
5'... Output gate electrode, 6... Back electrode, 7... DC bias power supply, 8, 8'... DC blocking capacitor, 9a, 9b, 9c... Matching circuit, 10a, 10
b...Signal source, 11...External load resistance for signal output, 1
2... Constant voltage terminal, 13... Earth terminal, 14... Thin film resistor, 15... Bias voltage extraction tap, 1
6...Metal thin film, 17...High impurity concentration region.
Claims (1)
た絶縁膜と、該絶縁膜上に積層された圧電膜と、
該圧電膜上の離れた位置に設けられた２つの信号
入力用トランスジユーサと、上記基板の他表面に
設けられ接地に連ねられる裏面電極と、上記圧電
膜上の上記２つの信号入力用トランスジユーサに
挟まれた位置に前記２つの信号入力用トランスジ
ユーサを結ぶ方向に複数個に分割して設けられた
信号出力用ゲート電極と、前記各信号出力用ゲー
ト電極に接続され直流阻止用コンデンサを含む出
力信号取出手段と定電圧端子とアース端子とを備
え、この定電圧端子とアース端子との間には所定
のシート抵抗を有する抵抗帯が設けられ、この抵
抗帯の長手方向複数個所には上記各信号出力用ゲ
ート電極に適切なバイアス電圧を与えるように上
記ゲート電極に適宜接続されるバイアス電圧取出
用タツプが設けられていることを特徴とする表面
弾性波装置。 ２ 上記信号出力用ゲート電極の各々と上記バイ
アス電圧取出し用タツプの接続が、上記定電圧端
子に所定の定電圧を印加し、所望の電圧が得られ
る電圧取出し用タツプを適宜選択して行われる
か、またはバイアス電圧の調整が上記抵抗帯をレ
ーザあるいは電子ビームを用いてトリミングする
ことによつて行われることを特徴とする特許請求
の範囲第１項記載の表面弾性波装置。 ３ 上記抵抗帯がニクロムまたはサーメツト
（Cr−SiO）の真空蒸着膜または窒化タンタル
（Ta2N）のスパツタ膜であることを特徴とする
特許請求の範囲第１項または第２項記載の表面弾
性波装置。 ４ 上記抵抗帯がアンチモン、ビスマス、または
タンタルから成る金属薄膜であることを特徴とす
る特許請求の範囲第１項または第２項記載の表面
弾性波装置。 ５ 上記抵抗帯が上記半導体基板表面領域に設け
られた高不純物濃度層であることを特徴とする特
許請求の範囲第１項記載の表面弾性波装置。 ６ 上記信号出力用ゲート電極の各々と上記バイ
アス電圧取出し用タツプの接続が、上記定電圧端
子に所定の定電圧を印加し、所望の電圧が得られ
る電圧取出し用タツプを適宜選択して行われるこ
とを特徴とする特許請求の範囲第５項記載の表面
弾性波装置。[Claims] 1. A semiconductor substrate, an insulating film laminated on one surface of the substrate, a piezoelectric film laminated on the insulating film,
two signal input transducers provided at separate positions on the piezoelectric film; a back electrode provided on the other surface of the substrate and connected to ground; and the two signal input transformers on the piezoelectric film. A gate electrode for signal output divided into a plurality of parts in the direction connecting the two signal input transducers at a position sandwiched between the transducers, and a gate electrode for DC blocking connected to each of the gate electrodes for signal output. It is equipped with an output signal extraction means including a capacitor, a constant voltage terminal, and a ground terminal, and a resistance band having a predetermined sheet resistance is provided between the constant voltage terminal and the ground terminal, and the resistance band is connected at multiple locations in the longitudinal direction of the resistance band. A surface acoustic wave device characterized in that the surface acoustic wave device is provided with a bias voltage extraction tap that is appropriately connected to the gate electrode so as to apply an appropriate bias voltage to each of the signal output gate electrodes. 2. Connection between each of the signal output gate electrodes and the bias voltage extraction tap is performed by applying a predetermined constant voltage to the constant voltage terminal and appropriately selecting a voltage extraction tap that provides the desired voltage. 2. The surface acoustic wave device according to claim 1, wherein the bias voltage is adjusted by trimming the resistance band using a laser or an electron beam. 3. The surface elasticity according to claim 1 or 2, wherein the resistance band is a vacuum-deposited film of nichrome or cermet (Cr-SiO) or a sputtered film of tantalum nitride (Ta 2 N). wave device. 4. The surface acoustic wave device according to claim 1 or 2, wherein the resistance band is a metal thin film made of antimony, bismuth, or tantalum. 5. The surface acoustic wave device according to claim 1, wherein the resistance band is a high impurity concentration layer provided in the surface region of the semiconductor substrate. 6. Connection between each of the signal output gate electrodes and the bias voltage extraction tap is performed by applying a predetermined constant voltage to the constant voltage terminal and appropriately selecting a voltage extraction tap from which a desired voltage can be obtained. A surface acoustic wave device according to claim 5, characterized in that:
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19898784A JPS6177415A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
| GB8523150A GB2166616B (en) | 1984-09-21 | 1985-09-19 | Surface acoustic wave device |
| SE8504350A SE462132B (en) | 1984-09-21 | 1985-09-20 | Acoustic Surface Device |
| FR858514000A FR2570902B1 (en) | 1984-09-21 | 1985-09-20 | SURFACE ACOUSTIC WAVE DEVICE |
| DE19853533611 DE3533611A1 (en) | 1984-09-21 | 1985-09-20 | ACOUSTIC SURFACE WAVE DEVICE |
| US07/099,688 US4745378A (en) | 1984-09-21 | 1987-09-18 | Surface acoustic wave device |
| GB8822450A GB2208769B (en) | 1984-09-21 | 1988-09-23 | Surface acoustic wave device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19898784A JPS6177415A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6177415A JPS6177415A (en) | 1986-04-21 |
| JPH033415B2 true JPH033415B2 (en) | 1991-01-18 |
Family
ID=16400221
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19898784A Granted JPS6177415A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6177415A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7158767B2 (en) * | 2003-10-24 | 2007-01-02 | Cts Corporation | Tuneable frequency translator |
-
1984
- 1984-09-21 JP JP19898784A patent/JPS6177415A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6177415A (en) | 1986-04-21 |
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