JPH0337766B2 - - Google Patents
Info
- Publication number
- JPH0337766B2 JPH0337766B2 JP59198985A JP19898584A JPH0337766B2 JP H0337766 B2 JPH0337766 B2 JP H0337766B2 JP 59198985 A JP59198985 A JP 59198985A JP 19898584 A JP19898584 A JP 19898584A JP H0337766 B2 JPH0337766 B2 JP H0337766B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- output gate
- piezoelectric film
- signal input
- divided
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
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- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は半導体基板上に設けられた圧電膜を有
する、モノリシツク型表面弾性波（以下本明細書
においてはSAWと略記する。）装置、特にSAW
コンボルバまたはコリレータに関する。Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a monolithic surface acoustic wave (hereinafter abbreviated as SAW) device having a piezoelectric film provided on a semiconductor substrate, and particularly to a SAW device.
Regarding convolvers or correlators.
SAWを利用する小型軽量の信号処理機能素子
としてSAWコンボルバやSAWコリレータがあ
る。これらは構造上分離媒質型とモノリシツク型
とに大きく分けられるが、特に生産性や効率の面
からモノリシツク型が有力である。半導体基板と
圧電膜とを組合せたモノリシツク型SAWコンボ
ルバあるいはコリレータにおいて、その信号処理
機能はSAWと半導体表面の空間電荷層との非線
形相互作用によつて生じる。この作用を利用する
ために、従来、第３図および第４図に示す半導体
基板１、絶縁膜３を介してその上に設けられた圧
電膜２、その圧電膜２の表面上の両端近傍に設け
られた信号入力用トランスデユーサ４ａおよび４
ｂ、および処理信号の出力用ゲート電極５を有す
る構造が用いられている。第３図中６は裏面電極
であり、第４図中、７は可変の直流バイアス電
源、８は直流阻止用コンデンサ、９ａ，９ｂおよ
び９ｃは整合回路、１０ａおよび１０ｂは信号
源、１１は信号出力用外部負荷抵抗を表わす。
SAW convolvers and SAW correlators are small and lightweight signal processing functional elements that utilize SAW. These can be roughly divided into separation medium type and monolithic type based on their structure, but the monolithic type is particularly popular from the viewpoint of productivity and efficiency. In a monolithic SAW convolver or correlator that combines a semiconductor substrate and a piezoelectric film, its signal processing function is generated by nonlinear interaction between the SAW and a space charge layer on the semiconductor surface. In order to utilize this effect, conventionally, as shown in FIG. 3 and FIG. Provided signal input transducers 4a and 4
b, and a gate electrode 5 for outputting a processed signal. In Figure 3, 6 is a back electrode, in Figure 4, 7 is a variable DC bias power supply, 8 is a DC blocking capacitor, 9a, 9b and 9c are matching circuits, 10a and 10b are signal sources, and 11 is a signal Represents the external load resistance for output.
この構造において、非線形相互作用はゲート電
極５直下の領域で行なわれ（以下本明細書におい
ては、この領域を相互作用領域と呼ぶ。）、出力は
ゲート電極５と裏面電極６の間から取り出され
る。相互作用の強さは、半導体基板１表面の相互
作用領域における容量−電圧特性（Ｃ−Ｖ特性）
に依存するから、ゲート電極５と接地されている
裏面電極６間に印加される直流バイアス電圧によ
り大きく変化する。したがつて、従来の方式で
は、ゲート電極内で加え合わされた総合的な出力
が最大値を示すバイアス電圧を最適バイアスとし
て、全相互作用領域に均一に印加し、動作を行な
わせることが一般的であつた。 In this structure, nonlinear interaction takes place in the region directly below the gate electrode 5 (hereinafter, in this specification, this region is referred to as an interaction region), and the output is extracted from between the gate electrode 5 and the back electrode 6. . The strength of the interaction is determined by the capacitance-voltage characteristics (C-V characteristics) in the interaction region on the surface of the semiconductor substrate 1.
Therefore, it varies greatly depending on the DC bias voltage applied between the gate electrode 5 and the grounded back electrode 6. Therefore, in conventional methods, it is common to use the bias voltage that gives the maximum total output added within the gate electrode as the optimal bias, and apply it uniformly to the entire interaction region to perform the operation. It was hot.
しかし、相互作用領域内のＣ−Ｖ特性は通常均
一ではなく、面内分布を持つから、特に素子の信
号処理能力の向上を図る目的で相互作用領域を長
くする場合など、従来の方式の様に領域全体に対
して均一なバイアス電圧を印加する方法では、前
記Ｃ−Ｖ特性の分布のために印加バイアスが領域
のあらゆる部分に対して最適とは限らなくなり、
素子に最適動作を行なわせる上で無視できない問
題となる。 However, the C-V characteristics within the interaction region are usually not uniform but have an in-plane distribution, so when the interaction region is lengthened to improve the signal processing ability of the device, it is difficult to In the method of applying a uniform bias voltage to the entire region, the applied bias is not necessarily optimal for all parts of the region due to the distribution of the C-V characteristics.
This becomes a problem that cannot be ignored in order for the device to perform optimal operation.
本発明の目的は、全体的な素子の効率を向上さ
せるように、素子の非線形相互作用領域における
Ｃ−Ｖ特性の分布に合わせて直流バイアス電圧を
分布させることができる、冒頭に述べた種類の
SAW装置を提供することである。
It is an object of the present invention to provide a method of the type mentioned at the outset, which allows the DC bias voltage to be distributed in accordance with the distribution of the C-V characteristics in the nonlinear interaction region of the device, so as to improve the overall device efficiency.
Our goal is to provide SAW equipment.
上記目的を達成するために、本発明による
SAW装置は、半導体基板と、該基板の一表面上
に積層された絶縁膜と、該絶縁膜上に積層された
圧電膜と、該圧電膜上の離れた位置に設けられた
２つの信号入力用トランスジユーサと、上記基板
の他表面に設けられた接地に連ねられる裏面電極
と、上記圧電膜上の上記２つの信号入力用トラン
スジユーサに挟まれた位置に前記２つの信号入力
用トランスジユーサを結ぶ方向に複数個に分割し
て設けられた信号出力用ゲート電極と、上記分割
された各出力ゲート電極に対して供給される各非
線形相互作用領域毎に容量−電圧特性に応じた最
適直流バイアスを独立して調整可能な複数の直流
バイアス電源と、上記出力ゲート電極に夫々一端
を接続する複数の直流阻止用コンデンサの各々の
他端に接続された複数の整合回路とより成ること
を特徴とする。
In order to achieve the above object, the present invention
A SAW device includes a semiconductor substrate, an insulating film laminated on one surface of the substrate, a piezoelectric film laminated on the insulating film, and two signal inputs provided at separate positions on the piezoelectric film. a rear electrode connected to the ground provided on the other surface of the substrate, and the two signal input transformers at a position sandwiched between the two signal input transducers on the piezoelectric film. A gate electrode for signal output is divided into a plurality of parts in the direction of connecting the output gate electrodes, and a gate electrode is provided for each nonlinear interaction area according to the capacitance-voltage characteristics to be supplied to each of the divided output gate electrodes. Consisting of a plurality of DC bias power supplies capable of independently adjusting the optimum DC bias, and a plurality of matching circuits each connected to the other end of a plurality of DC blocking capacitors each having one end connected to the output gate electrode. It is characterized by
以下に、図面を参照しながら、実施例を用いて
本発明を一層詳細に説明するが、それらは例示に
過ぎず、本発明の枠を越えることなしにいろいろ
な変形や改良があり得ることは勿論である。 Hereinafter, the present invention will be explained in more detail using examples with reference to the drawings, but these are merely illustrative and it is understood that various modifications and improvements may be made without going beyond the scope of the present invention. Of course.
第１図は本発明によるSAW装置の上面図で、
図中第４図と共通する引用番号は第４図における
ものと同じ部分を示し、′は本発明によつて複数
個に分割されていることを表わす。第１図に見ら
れるように、本発明によるSAW装置においては、
出力用ゲート電極５′は両端近傍に設けられてい
る信号入力用トランスジユーサ４ａと４ｂを結ぶ
方向に複数個に分割されており、その各々に独立
に調整可能な、ゲート電極５′と同じ数の直流バ
イアス電源７′から各電極５′直下のＣ−Ｖ特性に
対して最適なバイアス電圧が印加される。相互作
用領域で処理された信号は分割されたゲート電極
５′直下の領域における信号毎にそのゲート電極
で加え合され、直流電圧を阻止するコンデンサ
８′を介して出力される。
FIG. 1 is a top view of the SAW device according to the present invention.
In the figure, reference numbers common to those in FIG. 4 indicate the same parts as in FIG. 4, and '' indicates that the parts are divided into a plurality of parts according to the present invention. As seen in FIG. 1, in the SAW device according to the present invention,
The output gate electrode 5' is divided into a plurality of parts in the direction connecting the signal input transducers 4a and 4b provided near both ends, and can be adjusted independently for each part, the same as the gate electrode 5'. An optimum bias voltage is applied from several DC bias power supplies 7' to the CV characteristics directly under each electrode 5'. The signals processed in the interaction region are summed for each signal in the region immediately below the divided gate electrode 5' at the gate electrode, and outputted via a capacitor 8' that blocks DC voltage.
本発明はモノリシツク型のSAWコンボルバあ
るいはコリレータに関するものであり、半導体基
板１と圧電膜３との層状構造素子を前提としてい
る。ここで素子の動作効率あるいは温度特性、ま
たICとの一体化等を考慮する場合、構造として
はZnO／SiO2／SiまたはZnO／SiO2／Si／Al2O3
あるいはAlN／SiまたはAlN／Si／Al2O3が有利
である。ここで、Al2O3はサフアイアの単結晶、
Siはシリコン単結晶を表わし、ZnOおよびAlNが
圧電膜である。 The present invention relates to a monolithic SAW convolver or correlator, and is based on a layered structure element consisting of a semiconductor substrate 1 and a piezoelectric film 3. When considering the operating efficiency or temperature characteristics of the element, or its integration with an IC, the structure should be ZnO/SiO 2 /Si or ZnO/SiO 2 /Si/Al 2 O 3
Alternatively, AlN/Si or AlN/Si/Al 2 O 3 are preferred. Here, Al 2 O 3 is a single crystal of sapphire,
Si represents silicon single crystal, and ZnO and AlN are piezoelectric films.
第２図は本発明の他の一つの実施の態様による
SAW装置の上面図で、この実施の態様において
は、出力用ゲート電極５′、直流バイアス電源
７′、および直流阻止用コンデンサ８′だけでな
く、整合回路９c′および出力用外部負荷抵抗１
１′もまた出力用ゲート電極５′に対応して分割さ
れている。この実施の態様によれば、出力は、各
ゲート電極５′毎に独立に取り出されることがで
きる。 FIG. 2 is according to another embodiment of the present invention.
This is a top view of the SAW device. In this embodiment, not only an output gate electrode 5', a DC bias power supply 7', and a DC blocking capacitor 8', but also a matching circuit 9c' and an output external load resistor 1 are shown.
1' is also divided corresponding to the output gate electrode 5'. According to this embodiment, the output can be taken out independently for each gate electrode 5'.
以上説明した通り、本発明によれば、モノリシ
ツク型SAWコンボルバまたはコリレータにおい
て、出力用ゲート電極が複数個に分割されている
から、分割されたゲート電極の各々を最小の単位
領域として独立に印加バイアスを調整することが
でき、したがつて素子の非線形相互作用領域にお
けるＣ−Ｖ特性の分布に対し、前記単位領域ごと
にその領域での最適バイアスを選択し、印加する
ことができるので、全体的な素子の効率を向上さ
せることができる。
As explained above, according to the present invention, in a monolithic SAW convolver or correlator, the output gate electrode is divided into a plurality of parts, so that each divided gate electrode is treated as the smallest unit area and a bias is applied independently. Therefore, for the distribution of CV characteristics in the nonlinear interaction region of the device, the optimum bias for each unit region can be selected and applied, so that the overall The efficiency of the device can be improved.
第１図および第２図は本発明の二つの異なつた
実施の態様によるSAW装置の上面図およびその
周辺回路の図式図、第３図は従来のSAW装置の
断面図、第４図は従来のSAW装置の上面図およ
びその周辺回路の図式図である。
１……半導体基板、２……圧電膜、３……絶縁
膜、４ａ，４ｂ……信号入力用トランスジユー
サ、５，５′……出力用ゲート電極、６……裏面
電極、７，７′……直流バイアス電源、８，８′…
…直流阻止用コンデンサ、９ａ，９ｂ，９ｃ，９
c′……整合回路、１０ａ，１０ｂ……信号源、１
１，１１′……信号出力用外部負荷抵抗。
1 and 2 are top views of SAW devices according to two different embodiments of the present invention and schematic diagrams of their peripheral circuits, FIG. 3 is a sectional view of a conventional SAW device, and FIG. 4 is a diagram of a conventional SAW device. FIG. 2 is a top view of the SAW device and a schematic diagram of its peripheral circuits. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Piezoelectric film, 3... Insulating film, 4a, 4b... Transducer for signal input, 5, 5'... Gate electrode for output, 6... Back electrode, 7, 7 '...DC bias power supply, 8,8'...
...DC blocking capacitor, 9a, 9b, 9c, 9
c'... Matching circuit, 10a, 10b... Signal source, 1
1, 11'...External load resistance for signal output.
Claims (1)
た絶縁膜と、該絶縁膜上に積層された圧電膜と、
該圧電膜上の離れた位置に設けられた２つの信号
入力用トランスジユーサと、上記基板の他表面に
設けられ接地に連ねられる裏面電極と、上記圧電
膜上の上記２つの信号入力用トランスジユーサに
挟まれた位置に前記２つの信号入力用トランスジ
ユーサを結ぶ方向に複数個に分割して設けられた
信号出力用ゲート電極と、上記分割された各出力
ゲート電極に対して供給される各非線形相互作用
領域毎に容量−電圧特性に応じた最適直流バイア
スを独立して調整可能な複数の直流バイアス電源
と、 上記出力ゲート電極に夫々一端を接続する複数
の直流阻止用コンデンサと、 該直流阻止用コンデンサの各々の他端に接続さ
れた複数の整合回路と、より成ることを特徴とす
る表面弾性波装置。[Claims] 1. A semiconductor substrate, an insulating film laminated on one surface of the substrate, a piezoelectric film laminated on the insulating film,
two signal input transducers provided at separate positions on the piezoelectric film; a back electrode provided on the other surface of the substrate and connected to ground; and the two signal input transformers on the piezoelectric film. A signal output gate electrode is provided at a position between the transducers and divided into a plurality of parts in a direction connecting the two signal input transducers, and a signal output gate electrode is supplied to each of the divided output gate electrodes. a plurality of DC bias power supplies capable of independently adjusting the optimum DC bias according to the capacitance-voltage characteristics for each nonlinear interaction region; a plurality of DC blocking capacitors each having one end connected to the output gate electrode; A surface acoustic wave device comprising: a plurality of matching circuits connected to the other end of each of the DC blocking capacitors.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19898584A JPS6177413A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
| GB8523150A GB2166616B (en) | 1984-09-21 | 1985-09-19 | Surface acoustic wave device |
| SE8504350A SE462132B (en) | 1984-09-21 | 1985-09-20 | Acoustic Surface Device |
| FR858514000A FR2570902B1 (en) | 1984-09-21 | 1985-09-20 | SURFACE ACOUSTIC WAVE DEVICE |
| DE19853533611 DE3533611A1 (en) | 1984-09-21 | 1985-09-20 | ACOUSTIC SURFACE WAVE DEVICE |
| US07/099,688 US4745378A (en) | 1984-09-21 | 1987-09-18 | Surface acoustic wave device |
| GB8822450A GB2208769B (en) | 1984-09-21 | 1988-09-23 | Surface acoustic wave device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19898584A JPS6177413A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6177413A JPS6177413A (en) | 1986-04-21 |
| JPH0337766B2 true JPH0337766B2 (en) | 1991-06-06 |
Family
ID=16400193
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19898584A Granted JPS6177413A (en) | 1984-09-21 | 1984-09-21 | Surface acoustic wave device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6177413A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02199910A (en) * | 1989-01-27 | 1990-08-08 | Clarion Co Ltd | Surface acoustic wave device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5879779A (en) * | 1981-11-06 | 1983-05-13 | Clarion Co Ltd | Elastic surface-wave convolver |
-
1984
- 1984-09-21 JP JP19898584A patent/JPS6177413A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6177413A (en) | 1986-04-21 |
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