JPH033424A - Receiver - Google Patents

Abstract

PURPOSE:To perform a demodulation arithmetic operation at high speed by performing a correction arithmetic operation so as to approximate the sum of the absolute values of orthogonal transform output to a specific value, and performing the demodulation arithmetic operation by using a correction result. CONSTITUTION:Reception signals orthogonally transformed with first and second multipliers 37 and 38 are supplied to an arithmetic means 43 via low-pass filters 30 and 40. The arithmetic means 43 finds the sum k1 of the absolute values x1a and x2a of the output x1 and x2 of the low pass-filters. The computed result of the arithmetic means 43 is supplied to a demodulation means 43, and the demodulation means 43 performs the correction arithmetic operation so as to approximate the sum k1 to (x1<2>+x2<2>), and demodulation is performed by using a correction value ka that is the correction result in an arithmetic operation for the demodulation of the reception signal. Therefore, it is possible to perform the direct detection of a reference signal and the reception signal asynchronously even when the complicated arithmetic operation of a square root is omitted. In such a way, the demodulation arithmetic operation of the reception signal can be performed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a receiver suitably implemented as a radio broadcast receiver, and more specifically to a receiver that demodulates a received signal using a direct detection method. do.

BACKGROUND OF THE INVENTION FIG. 5 is a block diagram showing the electrical configuration of a basic radio receiver 1 that performs direct transverse stringing of amplitude modulation broadcasting. This receiver 1 roughly includes an antenna 2, a high frequency amplification circuit 3, an orthogonal exchange circuit 4, a low pass filter (hereinafter abbreviated as LPF) 9.10, and a multiplier 11.12.
, an adder 13 , an arithmetic circuit 14 , an amplifier 17 , a power amplifier 18 , a speaker 19 , and a tuning control circuit 20 .

The received signal received by the antenna 2 is sent to the high frequency amplification circuit 3.
It is applied to the orthogonal transformation circuit n4 via .

The quadrature R boundary circuit 4 includes a voltage controlled oscillation circuit 5 that oscillates at a frequency corresponding to the output voltage from the tuning control circuit 20;
A multiplier 7 that multiplies the reference signal from the voltage controlled oscillation circuit 5 by the received signal, a phase shifter 6 that shifts the phase of the reference signal from the voltage controlled oscillation circuit 5 by 90 degrees, and a phase shifter a multiplier 8 for multiplying the signal from 6 and the received signal;
It consists of:

The output from the multiplier 7 is given to the multiplier 11 via the LPF 9, multiplied by 2 and given to the adder 13. The output from the multiplier 8 is given to the multiplier 1 via the LPFlo.
The resultant signal is multiplied by 2 to the power of 2 and provided to the adder 13. The output of adder 13 is given to arithmetic circuit 14.

The operational circuit 14 includes an operational amplifier 15 and a multiplier 16, and the output from the adder 13 is applied to a non-inverting input terminal of the operational amplifier 15. After the output of the operational amplifier 15 is multiplied by a square by a multiplier 16, it is negatively fed back.

As a result, a signal representing the square root of the input signal is derived from the arithmetic circuit 14, and a signal representing the square root of the input signal is derived from the amplifier 17.
8 to the speaker 19.

The tuning control circuit 20 is configured in substantially the same manner as the phase lock loop 1 circuit of a conventionally used electronic tuning tuner, and includes a programmable counter 21 that divides the frequency of the oscillation signal of the voltage controlled oscillation circuit 5, and a programmable counter 21 that divides the oscillation signal of the voltage controlled oscillation circuit 5. A control circuit 22 that controls the frequency division ratio of the pull counter 21, a crystal oscillator 23 that vibrates at a reference frequency, a frequency dividing circuit 24 that divides the frequency of the oscillation signal of the crystal oscillator 23, and the programmable counter 21. 21 and the output from the frequency dividing circuit 24, and an LPF 26 that provides a DC voltage level corresponding to the comparison result of the phase comparator 25 to the voltage control Q system n5. configured.

In the receiver 1 configured as described above, the received signal S1 from the high frequency amplifier circuit 3 and the reference signal S2 from the voltage controlled oscillation circuit 5 are respectively 51=E, sin
(ω, tmoθ) ・(1) S2
= Eos i n (ωot) −(
2), where El is a modulated wave, ω1 is a carrier wave angular frequency, Eo is a constant, ω. is the angular frequency of the reference signal generated by the voltage controlled oscillator circuit 5. θ is the phase difference between the reference signal from the voltage w4 control oscillation circuit 5 and the received signal, and it changes from moment to moment when the two are not synchronized.

Based on the first equation and the second equation, the output S of the multiplier 7 is
3, S 3=E+0in(ω+t+θ)XEosin(ωo
t) = E+Eo(cos(ω, t+ωoL+
θ)-C! O3(ωlt-ωJ〇)...(3〉) The output S3 of the multiplier 7 is converted into an r-wave by the LPF 9 in the modulated wave band, for example, a band of about 10 kHz or less, and therefore, in the third equation, the The top portion is blocked, and the output S4 of the LPF 9 is expressed as .

On the other hand, the reference signal from the voltage controlled oscillation circuit 5 is applied to the multiplier 8 by the phase shifter 6 with a phase shift of 90 degrees, so the output S5 of the multiplier 8 is as follows: 55=E1sin(ω,L+θ )x Eocos(ωo
k) = −E+Eo(sin(ωat÷(IJ 6 t
"θ)+5in(ωIL-ωot+θ)...(5) The front top portion is blocked by the LPF 10, so the output s6 from the LPF 10 is as follows.

Therefore, the output S7 from the arithmetic circuit 14 is +n 2N
13 is the square root of the sum of the output S4 of the LPF 9 squared by the multiplier 11 and the output S6 of the LPFIO squared by the multiplier 12, that is, 57=J'1 Therefore, as is clear from the seventh equation, even if the phase shift θ between the received signal and the reference signal from the voltage-controlled m generation diagram n5 changes, the output $7 from the arithmetic circuit 14 is In this way, the direction is asynchronous to the received signal, without any change.
It can be understood that it is possible to detect

However, as shown in the seventh equation, square root calculation processing is required, and therefore, when the configuration from the multipliers 11 and 12 to the calculation circuit n14 is realized by a digital signal processing device, the typical In the conventional technique, the calculation process of the square root is performed by series expansion or the like.

Problems to be Solved by the Invention In the prior art as described above, a large number of processing steps are required for square root calculation processing. Therefore, it takes a long time to demodulate the received signal, and therefore it is necessary to provide a plurality of digital signal processing devices I'11 to perform parallel processing.

An object of the present invention is to provide a receiver that can perform demodulation calculations on received signals at high speed.

Means for Solving the Problems The present invention includes: a first multiplier that multiplies a first reference signal and a received signal; and a second multiplier that multiplies the received signal by a second reference signal having a different phase with respect to the first reference signal. a second multiplier, first and second low-pass filters respectively provided after the first and second multipliers, and an absolute value x1a of each output x1°x2 of the first island and second low-pass filter, arithmetic means for calculating 1 in the sum of x2a, and responding to a signal representing 1 in the sum, and 1 in this sum xl'+
This receiver is characterized by comprising demodulation means that performs correction to approximate x2'' and performs demodulation by using the correction value ka in a calculation for recovery.

Further, in the present invention, the demodulation means may be arranged so that the absolute value Xla
, x 2 = t, and the larger value is linearly approximated using the smaller value to find a correction coefficient of 2, and the correction coefficient is multiplied by 2 to the sum of 1 to obtain the above. This receiver is characterized by determining a correction value ka.

Furthermore, in the present invention, when the predetermined constant is ε, the correction coefficient is set as follows when x1a≧x2a, and when x1a<x2a, the constant ε is set to the correction value ka=kl*. 2 is the above
x12+x2''.

According to the present invention, the received signal is commonly given to the first multiplier and the second multiplier, and the received signal is multiplied by the first reference signal in the first multiplier and multiplied by the first reference signal in the first multiplier. In the multiplier, the first reference signal is multiplied by a second reference signal having a different phase, and thus the received signal is orthogonally transformed by the first and second multipliers. The multiplication result of the first multiplier is applied to the first low-pass filter, and the multiplication result of the second multiplier is applied to the second low-pass filter.

Each degree output xi of these first and second low-pass filters
, x2 are given to a calculation means, and this calculation means is
Absolute value of each output xi, x2 x1a T X 2 a
Find 1 in the sum of . The calculation results of the calculation means are given to the four demodulation means, and the demodulation means adds 1 to this sum.
A correction calculation is performed so as to approximate .

Therefore, even if the complicated square root calculation of Pi is removed from the demodulation calculation, the reference signal and the received signal can be directly detected asynchronously.

Further, according to the present invention, the correction calculation in the demodulation means first compares the magnitude relationship between the absolute values x1a and x2a,
A correction coefficient of 2 is obtained by linearly approximating the larger value using the smaller value. That is, for example, X 1 a≧x
2a, when the predetermined constant is ε, calculate, and when x1a·Cx2a, calculate.

Next, the correction value ka is obtained by multiplying the correction coefficient thus obtained by 2 and the sum of the absolute values x1a and x2a of the outputs xi and x2 by 1.

At this time, the constant ε is such that the correction value ka is the xl'+x
2”.

Therefore, when the constant ε is determined, the absolute value operation, addition operation, and multiplication operation are performed twice each, and the division operation is performed once.
x12+x2' by linear approximation
It is possible to obtain a correction value ka that approximates .

Embodiment FIG. 1 is a block diagram showing the electrical configuration of a receiver 31 according to an embodiment of the present invention. This receiving fi 31 can perform direct detection of the received signal received by the antenna 32 asynchronously to the captured and transmitted wave. This receiver 31 roughly includes an antenna 32, a high frequency amplification circuit 33, an orthogonal conversion circuit 3.1, and an LPF which is a tenth bus filter.
39, an LPF 40 which is a second low-pass filter, analog/digital converters 41, 42, a digital signal processing circuit 43 which is a calculation means and a demodulation means, a digital/1 analog converter 44, a speaker 49, The tuning control circuit 50 is configured to include a tuning control circuit 50.

The received signal received by the antenna 32 is given to the orthogonal conversion circuit 34 via the high frequency amplification circuit 33. The orthogonal conversion circuit 34 oscillates at a frequency corresponding to the output voltage from the tuning control circuit 50, and includes a voltage-controlled oscillation circuit 35 that derives the oscillation signal as a first reference signal, and a voltage-controlled oscillation circuit 35 that derives the oscillation signal as a first reference signal. The first reference signal is multiplied by the received signal, and the phase of the output signal from the multiplier 37, which is the first multiplier, and the voltage control Q-system path 35 are shifted by 90 degrees, and the second reference signal is derived. The output from the 0 multiplier 37, which is configured by multiplying the received signal by the second reference signal from the phase shifter 36 and the second multiplier 38, is output from the LPF 39. The output from the multiplier 38 is also provided to the LPF 40.

The outputs of the LPFs 39 and 40 are sent to the digital signal processing circuit 4 via analog/digital converters 41 and 42, respectively.
3 is input. The acoustic signal demodulated within this digital signal processing circuit 43 is converted into an analog acoustic signal by a digital/analog converter 344, and then is given to a speaker 49 from an amplifier 47 via a power amplifier 48, where it is converted into sound. .

The tuning control port n50 includes a programmable counter 51 that frequency divides the oscillation signal of the voltage controlled oscillation circuit 35, and a control circuit 52 that controls the frequency division ratio of this programmable counter 51.
and a crystal oscillator 53 that vibrates at a reference frequency.
A frequency dividing circuit 54 that divides the frequency of the oscillation signal of this crystal oscillator 53
and a phase comparator 5 that compares the phase of the output from the programmable counter 51 and the output from the frequency dividing port 2354.
and an LPF 56 that provides the voltage controlled oscillation circuit 35 with a DC voltage level corresponding to the soft ratio result of the phase comparator 55.

FIG. 2 is a flowchart for explaining the demodulation calculation operation within the digital signal processing circuit 43. First, in step n1, the absolute values x1a and x2a of the outputs xi and x2 from the LPF 3940 inputted via the analog/digital converters 41 and 42 are calculated using the equation 3E1. In step n2, 1 is calculated as the sum of the absolute values x1a and x2a. In step ri 3, the absolute value x1a and x
2a is larger, and when x1a≧x2a, the process moves to step rr4, and x 1 a <
When x 2 a, the process moves to step n5.

Step n4. In n5, a predetermined constant described later is ε
In this case, 2 is calculated as the correction coefficient based on the first equation or the second equation, respectively.

From steps n4 and n5, the process moves to step n6, where a correction value ka is calculated and determined based on the third equation.

ka=kl*2-(10)
On the other hand, as described in the prior art section, in order to perform direct detection asynchronously to the carrier wave, it is necessary to find the square root of the sum of the squares of the outputs xi and x2 from the LPF 39.40. These outputs x1. x2 corresponds to the output S4.86 in the fifth I2I, respectively.

Therefore, from the fourth and sixth equations, x1°=A
cos(/'-(11)x2
= As i nψ ,, (12
), and when xl'+x-Στ is expressed in polar coordinates, the locus is circular as shown by reference numeral 11 in 3I2I. On the other hand, the correction value εt obtained as described above is formed line-symmetrically with respect to the center line 13 in each quadrant, as indicated by the reference numeral e2.

Here, by changing the constant ε, the trajectory 11.
12 intersection point P, that is, the position where the error becomes zero, can be changed. For example, when ψ=35°, x1a=cos35'″=0.819 −(
13) x2a=siri35°=0.574
...(14) Therefore, kl=x1a+x2a=0.819+0.574=1.
393...(15) From the above equations 8 and 10, therefore ε=0
．． 561, and by setting a constant ε to this value, the intersection point P can be set at the position ψ=35° and 55° in the first quadrant, for example.

Therefore, the correction value k a obtained as described above is obtained by performing the absolute value operation, addition operation, multiplication operation twice, and division operation once, as described above, without performing complicated square root calculations. Through a total of seven calculation operations, it is possible to obtain a value close to the value x12 + x - Σ , which is necessary for direct detection. Thereby, the calculation operation within the digital signal processing circuit 43 can be reduced and the calculation time can be shortened.

On the other hand, when the sum of the absolute values x1a and x2a of the outputs xi and x2 from the LPF 39.40 is used without correction of 1, as shown by reference numeral 14 in FIG. However, a large error occurs, and the received signal cannot be detected.

Effects of the Invention As described above, according to the present invention, the sum of the absolute values x1a and x2a of the orthogonal transform outputs Xi and X2 of the received signal and two reference signals having mutually different phases is 1. ．． Two Σ
Since a correction calculation is performed to approximate τ and a demodulation calculation is performed using the correction value ka that is the correction result,
Even if complex square root calculations are removed from the demodulation calculation, the reference signal and the received signal can be directly detected asynchronously, and the demodulation calculation can be performed at high speed.

Further, according to the present invention, the correction calculation includes the absolute value x1
Compare the magnitude relationship of a and x2a, use the smaller value to linearly approximate the larger value, multiply the correction coefficient by 2, and multiply the sum of the absolute values x1ax2a of the outputs xi and x2 by 1 to obtain the above result. Since the correction value ka is calculated, the correction value ka can be calculated with a small number of calculations, and the demodulation calculation of the received signal can be performed at high speed.

[Brief explanation of the drawing]

1 (2I) is a block diagram showing the electrical configuration of the receiver 1131 according to an embodiment of the present invention, FIG. Graph showing the trajectory of the correction value output k a from LPF 39.43, Figure 4 is the output xl from LPF 39.40
, x2 is a graph showing a locus of 1 for the sum of absolute values. FIG. 5 is a block diagram showing the basic electrical configuration of a receiver 1 for directly detecting an amplitude modulated signal. 31... Receiver, 32... Antenna, 34... Orthogonal conversion circuit, 36... Phase shifter, 37.38... Multiplier, 39.40.56... LPF, 41.42 ...
Analog/digital converter, 43... Digital signal processing circuit, 44... Digital/analog converter, 49.
... Speaker, 50 ... Tuning control circuit

Claims (3)

[Claims] (1) a first multiplier that multiplies a first reference signal and a received signal; a second multiplier that multiplies the received signal by a second reference signal having a different phase with respect to the first reference signal; First and second low-pass filters provided after the first and second multipliers, respectively, and the sum k1 of the absolute values x1a and x2a of the outputs x1 and x2 of the first and second low-pass filters, respectively.
arithmetic means for calculating the sum k1;
Correction is made to approximate +x2^2, and the correction value k
A receiver comprising: demodulation means for performing demodulation by using a for demodulation calculations. (2) The demodulation means compares the magnitude relationship of the absolute values x1a and x2a, obtains a correction coefficient k2 by linearly approximating the larger value using the smaller value, and calculates the correction coefficient k2 by linearly approximating the larger value using the smaller value. 2. The receiver according to claim 1, wherein the correction value ka is obtained by multiplying k1. (3) When the predetermined constant is ε, the correction coefficient k2 is as follows: when x1a≧x2a, k2=x1a/(x1a+x2a*ε), and when x1a<x2a, k2=x2a/(x2a+x1a*ε) and the constant ε is the correction value ka=k1*k2 as the above ▲
3. The receiver according to claim 2, wherein there are mathematical formulas, chemical formulas, tables, etc., and the receiver is selected so as to be close to ▼.