JPH0334331U - - Google Patents

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Publication number
JPH0334331U
JPH0334331U JP9522489U JP9522489U JPH0334331U JP H0334331 U JPH0334331 U JP H0334331U JP 9522489 U JP9522489 U JP 9522489U JP 9522489 U JP9522489 U JP 9522489U JP H0334331 U JPH0334331 U JP H0334331U
Authority
JP
Japan
Prior art keywords
signal
power source
comparison circuits
generation period
digital signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9522489U
Other languages
Japanese (ja)
Other versions
JP2541444Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1989095224U priority Critical patent/JP2541444Y2/en
Publication of JPH0334331U publication Critical patent/JPH0334331U/ja
Application granted granted Critical
Publication of JP2541444Y2 publication Critical patent/JP2541444Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案のＡ／Ｄコンバータを示す回路
図、第２図は第１図の各部波形を示すタイミング
チヤートである。 １〜４……抵抗、５……トランスフアゲート、
６〜９……コンパレータ、１１……スイツチ制御
回路、１７〜２０……ラツチ回路。 FIG. 1 is a circuit diagram showing the A/D converter of the present invention, and FIG. 2 is a timing chart showing waveforms of various parts of FIG. 1 to 4...Resistance, 5...Transfer gate,
6-9...Comparators, 11...Switch control circuits, 17-20...Latch circuits.

Claims (1)

【実用新案登録請求の範囲】 (1) 第１電源と第２電源との間にｎ本の抵抗を
直列接続して成る直列抵抗回路網と、前記ｎ本の
抵抗の各接続点に生じる電圧が一方の入力端子に
印加され、且つデジタル信号に変換すべきアナロ
グ信号が他方の入力端子に共通印加され、一括レ
ベル比較を行なうｎ個の一括比較回路とを備え、
前記ｎ個の一括比較回路からｎビツトのデジタル
信号を得るＡ／Ｄコンバータにおいて、 前記第１電源及び前記第２電源の何れか一方と
前記直列抵抗回路網との間に接続されたスイツチ
回路と、 前記ｎ個の一括比較回路からｎビツトのデジタ
ル信号を得るための出力制御信号に基づいて、該
出力制御信号が発生する第１発生期間より長い第
２発生期間だけ、前記スイツチ回路をオンするオ
ン信号を発生するスイツチ制御回路と、 前記出力制御信号の第１発生期間と前記オン信
号の第２発生期間との差期間に、前記ｎ個の一括
比較回路から得られたｎビツトのデジタル信号を
保持する保持回路と、 を備えたことを特徴とするＡ／Ｄコンバータ。 (2) 請求項(1)記載のＡ／Ｄコンバータを備えた
マイクロコンピユータ。[Claims for Utility Model Registration] (1) A series resistance network consisting of n resistors connected in series between a first power source and a second power source, and a voltage generated at each connection point of the n resistors. is applied to one input terminal, and an analog signal to be converted into a digital signal is commonly applied to the other input terminal, and n batch comparison circuits perform batch level comparison,
In the A/D converter that obtains an n-bit digital signal from the n batch comparison circuits, a switch circuit connected between either one of the first power source and the second power source and the series resistor network; , turning on the switch circuit for a second generation period, which is longer than the first generation period during which the output control signal is generated, based on an output control signal for obtaining an n-bit digital signal from the n batch comparison circuits; a switch control circuit that generates an on signal; and an n-bit digital signal obtained from the n batch comparison circuits during a difference period between the first generation period of the output control signal and the second generation period of the on signal. An A/D converter characterized by comprising: a holding circuit that holds . (2) A microcomputer equipped with the A/D converter according to claim (1).
JP1989095224U 1989-08-10 1989-08-10 A / D converter Expired - Lifetime JP2541444Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1989095224U JP2541444Y2 (en) 1989-08-10 1989-08-10 A / D converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1989095224U JP2541444Y2 (en) 1989-08-10 1989-08-10 A / D converter

Publications (2)

Publication Number Publication Date
JPH0334331U true JPH0334331U (en) 1991-04-04
JP2541444Y2 JP2541444Y2 (en) 1997-07-16

Family

ID=31644501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1989095224U Expired - Lifetime JP2541444Y2 (en) 1989-08-10 1989-08-10 A / D converter

Country Status (1)

Country Link
JP (1) JP2541444Y2 (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103226A (en) * 1981-12-15 1983-06-20 Nec Corp Resistance string type load circuit
JPS60256229A (en) * 1984-05-31 1985-12-17 Fujitsu Ltd Da converter
JPS63144617A (en) * 1986-12-08 1988-06-16 Sony Corp Chopper type comparator

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58103226A (en) * 1981-12-15 1983-06-20 Nec Corp Resistance string type load circuit
JPS60256229A (en) * 1984-05-31 1985-12-17 Fujitsu Ltd Da converter
JPS63144617A (en) * 1986-12-08 1988-06-16 Sony Corp Chopper type comparator

Also Published As

Publication number Publication date
JP2541444Y2 (en) 1997-07-16

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