JPH0334366A - Cmos circuit - Google Patents

Abstract

PURPOSE:To obtain a CMOS circuit which can be made minimum in delay time by a method wherein a driver is made optimal in size for a load through the peak value of the load charge (discharge) current of the driver and a time required for the load charge current to reach the peak value at the input of step signals. CONSTITUTION:When a device parameter, an inverter size, and an input waveform are given, an optimal driver size Wopt which makes tpd minimum for a load CL satisfies a formula I. In the formula I, IDSAT, CL, VDD, COV, CJ, and gm represent the following respectively: saturation current par unit transistor; load capacitance; power source voltage; gate capacitance per unit transistor; overlap capacitance; junction capacitance per unit transistor size; and conductance per unit transistor size. The optimized driver is driven by an inverter, whereby a CMOS circuit composed of an inverter and a driver optimized for a load, and a load can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS circuit, and more particularly to a CMOS circuit having an inverter and driver configuration.

[Conventional technology]

Digital loads (CLl, OL,..., CL
. ), it is common to drive each load with an inverter array and a driver circuit.

For each load that is a problem in circuits such as memory LSIs and gate array LSIs, a single stage of inverter is sufficient, and as shown in Figure 9, it is possible to configure the inverter, driver, and basic load circuits by connecting them. I can do it.

Therefore, the delay time tld (hereinafter referred to as
(simply written as t) can be minimized by minimizing t and d of each basic circuit (inverter, driver, and load).

Conventionally, as a method for optimizing t of an inverter array of transistor sizes Xe, X++, . . . , x7, a method using the following calculation formula is known.

[Problem to be solved by the invention]

The conventional CMOS circuit described above uses the t□ optimization method (
Since the configuration uses equations 1) and (2), this method is inappropriate when there is only one stage of inverter, and it is difficult to find an optimal solution for the inverter size in consideration of the load (CL). The disadvantage is that it cannot be obtained.

A first object of the present invention is to present a method for optimizing tl in a CMOS circuit with an inverter and driver configuration, taking load into consideration, and to provide a CMOS circuit with an inverter and driver configuration optimized by this method. .

A second object of the present invention is to achieve t9. An object of the present invention is to provide an inverter and a driver circuit having optimally divided drivers in order to avoid an increase in the number of drivers.

[Means to solve the problem]

The CMOS circuit of the present invention is a CMOS circuit configured with an inverter, a driver, and a load, and is designed to calculate the peak value of the load charging (or discharging) current when a step signal is input to the driver. IA? If the time taken to reach this peak value is τ, here, ■. ,.・・・・・・V
o = Saturation current value per unit transistor size at VDD C2...Load capacitance vDD...-Power supply voltage Co...Gate capacitance per unit transistor size COV...・Overlap capacitance per unit transistor size C5... Junction capacitance per unit transistor size g, l+... Conductance per unit transistor size. It has a configuration that optimizes the

Also, the gate resistance of the driver transistor is set to R6 and 0.
It has drivers that are optimally divided so that 1τ (2) the number of divisions of driver transistors.

[Effect]

For a CMOS circuit with an inverter, driver, and load configuration, given the device parameters, inverter size, and input waveform, there is an optimal driver size (W, p,) that minimizes t□ for the load OL, and the following It can be found using the following method.

FIG. 8(a) shows a transient waveform of the charging current flowing from the driver to the load when a step signal is input.

In FIG. 8(a), w, , Wl, Wl, and W4 indicate driver sizes (P-type transistor side).

I p+ + I pg # I ps p I p□
indicates the peak value of E at each size,
LIll* t142p ted2zt, 44 indicates t, 6 (50% interval between input and output) at each size.

The waveform of the load current is generally the saturation current of the transistor (
Figure 8(c) shows that the current rises at the pentode current characteristic) and decreases at the non-saturation current (triode current characteristic). t□+C, . This is the time to complete charging of VDD.

In Fig. 8(a), driver sizes Wl and W2 are insufficient in transistor capacity, that is, transistor size, for the load, so the current reaches its limit at the saturation current value IPI+Ip□ of I Vas l "VDD, and charging As time increases, tea+ and t□2 are delayed.

The driver size W4 is the transistor capacity, that is, the transistor size is excessive for the load, and I□ is I
The peak value is shown when V a l < V nn, t.

”This is jpd4.

The driver size W3 is the optimum size (W, . . . ) of the driver for the load C□. That is, the peak value IP3 is exactly equal to the saturation current value of the transistor at l Vos l =VDD, and if the saturation current value per unit transistor size is I□1, the following equation holds true.

Here, OL is load capacitance, VDD is power supply voltage, Co is gate capacitance per unit transistor size, and COV is overlap capacitance % per unit transistor size.CJ is S per unit transistor size.

The D junction capacitance, g, is the conductance per unit transistor size.

The optimum size of the driver can be determined for the device parameters and load given by equation (4).

By driving this optimal driver with an inverter, it is possible to obtain a CMOS circuit with an inverter, driver, and load configuration optimized for the load.

Inverter section delay t, □, driver section delay t□
, then t□=1. □+t pdd.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(b) are a circuit diagram showing a first embodiment of the present invention and a simulation characteristic diagram thereof, respectively.

This example is based on process A, and this process A
is an n-type MOS) range switch Q. β of 2 is β, P-type MOS) transistor Q, β of 2 is β,
), β, /β, = 3
00(μtT/V)/150(IJ/V), channel length, /L,, = 1.2 p m71.2 μm, gate oxide film thickness T. X=20OA.

In this embodiment, each transistor size of the driver 2 (hereinafter simply referred to as driver size) w-a/w, a
is the value determined by the above-mentioned equation (4).

Region 1 shown in FIG. 1(b) (0≦CL≦1.0p
In F), one stage of 40 μm/20 μm inverter is sufficient, but in region II (1, OpF≦Ct, ≦1.35 p
In F), an inverter and a driver configuration are required, and the optimal driver size is w,,7w,,d=10
0 μm and 150 μm.

In the region In (1.35 pF≦CL≦1.8 pF), the optimum driver size is 140 μm 1TO μm, and in the region ■ (1.8 pF≦CL≦2.5 pF′) the optimum driver size is 180 μm 790 μm.

In region ■, 100 μm to 150 μm is insufficient in transistor size, and wi, wz in FIG. 8(a) in the above explanation
t: Corresponding. On the other hand, 180 μm/90 μm is an excessive transistor size and corresponds to W4 in FIG. 8(a).

The optimal size corresponding to w3 in Figure 8(a) is 140 μm.
/70μm.

Figure 2 is based on process B, and this process B is
β, , /β, = 400 (,uU/V) /200(μ
o/v), Lp/Ln=o, 8pm 10.8pm.

Tox=15 OA.

Region 1 (0≦OL≦1.0 pF)
One stage of 40 μm/20 pm inverter is sufficient.

In region 11 (1.0 pF≦OL≦1.3 pF), an inverter and a driver configuration are required, and the optimum driver size is w, 7w, a=100 μrm150 μm. In addition, region l11 (1,3pF≦Ct,≦2.5pF
), the optimum size is 140 μm/70 μm.

As mentioned above, given the driver size, process, and input waveform, the CMOS of the inverter and driver configuration
In the circuit, the optimum driver size that minimizes 1 for the load C1 can be actually determined by simulation based on equation (4).

In the above explanation, it is assumed that the gate resistance (layer resistance) is 0Ω.1. In reality, the gate resistance has a value of several Ω/portion to several tens of ohms/portion, so in the case of a transistor with a size exceeding 100 μm, the influence of the gate resistance appears on tl4. To avoid this, it is necessary to divide the transistors.

FIG. 3 is an equivalent circuit diagram showing a second embodiment of the present invention.

In this embodiment, the MOS transistor Q111Qllll of the driver 2 of the first embodiment is divided into n parts.
OS) If the gate resistance of transistor Q p 2 e Q a 2 is Ro, then each divided transistor DQ, l to D
Qp.

The gate resistance of DQ, r~DQ,,a is 'R,/n
(C0 is the gate capacitance).

Figure 4 shows the gate resistance Ro "40Ω in process A.
4 shows the dependence of t and 4 on the number of divisions (n) when the transistor size is 1 to 0 μm.

Up to n=6, t and d decrease with division, but n=
1 for 6 or more. hardly changes. Ct.

At -3 pF, the reduction is 3% when n==4, 10% when n=6, and 10% when n=8 compared to the non-divided case.

That is, n=6 is the optimal number of divisions, and τG/τ=0.07 for the optimal load.

Figure 5 shows t when the gate resistance R6 = 6Ω/gate in process B and the transistor size is 140μm to 770μm.
, d versus the number of divisions (n).

When 0L=3pF, t and d are 3 when n=4 compared to the undivided case.
%, the decrease is 4% when n=6 and 5% when n=8. In this case, n=4 is the optimal division, and for the optimal load τ0/τ
=0.05.

From the above results, approximately τ. It can be seen that it is sufficient to divide the transistors so that <0.1τ. Next, a simulation example of t,4 of an inverter and a driver circuit having an optimally divided driver 2A will be shown.

The size of the inverter is 40 μm/20 μm in the following two examples.

Figure 6 shows the gate resistance 802400 in process A.
This is the simulation result when there are 7 mouths.

The optimal driver size for regions I, n, and I is 100 each.
μm150μm, 140um/70,um.

180 μm/90 μm, and in the case of 6 divisions, the tpa due to division at O L = 3 p F is lower than that of no division shown by the dotted line
The degree of improvement is 11%.

FIG. 7 shows the simulation results when the gate resistance Ro'' is 6Ω/gate in process B.

The optimal driver size in the area I, I, I [[ is 100,
un15 (Jum, 140pm/70, um.180,
un/90, um, and in the case of 6 divisions, C t. =
The degree of improvement due to division at 3 pF is 5%.

As shown above, assuming that the gate resistance of the transistor of driver 2 is Ro and the input capacitance is 00, then t□ of the CMOS circuit with the inverter, driver, and load configuration
can be minimized.

〔Effect of the invention〕

As explained above, the present invention has a driver size (W.
, ), and by performing delay division using gate resistance, it is possible to minimize tl.

Therefore, it is possible to optimally design a CMOS circuit consisting of a basic circuit of a digital inverter and driver configuration.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a circuit diagram and a simulation characteristic diagram for Process B of the first embodiment of the present invention, respectively, and FIG. 2 is a simulation characteristic diagram for Process B of the first embodiment of the present invention. , FIG. 3 is an equivalent circuit diagram of the second embodiment of the present invention, FIGS. 4 and 5 are division dependence characteristic diagrams in process A and process B, respectively, of the second embodiment of the present invention, and FIG. and FIG. 7 are simulation characteristic diagrams for process A and process B of the second embodiment of the present invention, respectively, and FIGS. 8(a) to (c) are delay time pairs for explaining the operating principle of the present invention, respectively. A current characteristic diagram, an equivalent circuit diagram, an operation characteristic diagram of a driver, and FIG. 9 are circuit diagrams showing an example of a conventional CMOS circuit. 1... Inverter, 2, 2A, 21...
Driver %2D1-2D11...Divided driver %CL#CLt-CLll ``'...Load, DQ,...
~DQ,, DQ,, ~DQ,, ...... Division transistor, Qpltqp*eQ alt Q 112.
...MOS) transistor, R,1~Rell 1 Rfil~Ran...gate resistance.

Claims (2)

[Claims] (1) A CMOS circuit configured with an inverter, a driver, and a load, and the peak value of the load charging (or discharging) current at the time of inputting the step signal of the driver is I_D_S_
When A_T is the time taken to reach this peak value and τ is, W_o_p_t=V_D_D・C_L/I_D_S_A
_T・τ, τ=C_G+C_O_V+C_J/g_m Here, I_D_S_A_T... |V_G|=V
Saturation current value per unit transistor size at _D_D C_L...Load capacitance V_D_D...Power supply voltage C_G...Gate capacitance per unit transistor size C_O_V...Unit Overlap capacitance per transistor size C_J... Junction capacitance per unit transistor size g_m... Conductance per unit transistor size Optimize the driver size of the driver with respect to the load A CMOS circuit characterized by: (2) When the gate resistance of the driver transistor is R_G and the input capacitance is C_G, R_G/n・C_G/
Claim (1) having a driver optimally divided so that n<0.1τ (n is the number of divisions of driver transistors)
CMOS circuit as described.