JPH0334376A - Manufacture of vertical type field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Field of Application) The present invention relates to a method for manufacturing a vertical type field effect transistor.

[Prior Art] Vertical can field effect transistors are attracting attention as power-generating devices that have excellent characteristics such as high speed, wide safe operation range, and ability to operate in parallel.

FIG. 3 is a cutaway diagram of a semiconductor chip showing an example of a vertical magnetic field effect transistor.

As shown in FIG. 3, an n-
g A gate electrode 2 is grown, and a gate oxide film 3 is formed on the surface of the epitaxial layer 2. Next, a p-type impurity is ion-implanted using the gate electrode 1fi7 as a mask to form a p-type base region 18 on the surface of the gate electrode 20. Next, an n-type source region 13 is selectively formed on the surface of the base region 7 with a portion aligned with the gate electrode 7 .

Next, PSG (phos) is applied to the surface including the gate electrode 7.
ph.

-5ilinate glass) film 14 is deposited and selectively etched;
The surface of base region 18 is exposed, leaving membrane 14 behind. Next, an aluminum layer is deposited on the entire surface to form a source 'aIc1 billion'.
form 5. Next, a drain pole 16 is provided on the back surface of the p+ type 7 silicon group @1.

[Problems to be Solved by the Invention] In the above-described conventional vertical field effect transistor, a channel is created in the surface region of the base region by applying a positive voltage to the gate electrode. When this channel is formed, the structure consisting of an n-type source region, an n-channel, an n-type epitaxial layer, and a p-type silicon substrate becomes substantially the same as a pin diode. The n-type external layer is formed by a few thousand yen implanted from the p+ silicon base layer and a few thousand yen implanted from the source region. l! Due to the accumulation of carriers, the on-voltage between the source and drain is adjusted to the normal MOS FET.
The fishing rate is about 1/10.

However, the behavior of the minority carries f injected into this base region poses a problem. This small number of dried lobsters are eventually gathered in the base area and pass through to the source area's dokinosu*M. When the current density in this part becomes 1% as the current ID increases, a 1 voltage drop occurs when passing through this part due to the resistance of the base region under the source region. 15° This voltage forward biases the source-base region junction, so if this voltage drop is large, electrons or holes will be directly injected from the source region to the base region, causing the parasitic Nyristor's latch gamma gate. The drawback is that it is difficult to keep up. In order to solve this drawback, the concentration in the base region can be increased, but the gate force is too high!
[Pressure V. The upper limit of the dose of ion implantation for forming base base is determined by limitations from the viewpoint of characteristics such as 5 (off), and it is difficult to control chia lag. In addition, by using lithography technology, the sigate cutoff viewing pressure vGs (off
), etc., it is a good idea to increase the impurity concentration in the base region only in parts that do not affect the impurity concentration, but it always contains unstable conditions such as misalignment, and is not suitable for miniaturization of devices.

[Means for Solving the Problems J] A method for manufacturing a vertical field effect transistor according to the present invention includes forming a gate insulating film on an inverted 41 type Evitar P7 layer provided on a 24 type semiconductor substrate. and a step of selectively forming a gate '11 electrode on the gate insulating film, f8) a step of ion-implanting a 124-voltage type high-iron impurity into the surface of the Ebitaki layer using the gate electrode as a mask. , A step of ion-implanting a low (S degree impurity@) of Izuka-mvt type using 'it&' as a mask, p) Etching only the side surface of the impurity by heat treatment and etching it onto the surface of the shrimp layer. forming a first base region having impurity concentration and a second base region having low-strength impurity adjoining the first base region (2) aligning a part of the gate electrode 7 and forming a second base region having a low concentration impurity; The method includes the step of selectively forming an inverted-type source region on the surfaces of the first and second base regions.

[Example j Next, the present invention will be explained with reference to the drawings.

Figures 1 (a) to 1 (g) are cross-sectional views of a cow monument shown in the order of steps for explaining the first embodiment of the present invention.

As shown in Figure 1 (12), an n- type Evita layer 2 is grown on the p+ type silicon substrate 1, and the surface of the Evita layer 2 is thermally oxidized to a thickness of 50 to 200 nm.
A gate oxide film 3 is formed to a thickness of .

Next, a polycrystalline silicon layer 4 with a thickness of 0.5 to 1 μm is deposited on the silicate oxide film 3 by the CVD method, and a photoresist [5-thickness layer] is applied on the polycrystalline/licon/14 layer. Buttering is performed to form openings 6.

Next, as shown in FIG. 1 tb+, the polycrystalline silicon layer 4 is anisotropically etched using the photoresist film 5 as a mask to form the gate electrode 7. Next, using the photoresist film 5 and gate '4 pole 7 as a mask, boron ions are applied to 71
0 speed energy 40-150keV.

Ion implantation is performed at a dose @l Q15cR-2 to form a high concentration p-type impurity implantation region 8.

Next, as shown in No. 117 (cl), the opening 6 is etched by glazma etching using a freon thread gas such as CF, which has a high etching rate for the gate oxide film 3 and a high etching rate for the gate electrode 7. The side surface of the gate electrode 7 is etched to form a 17-darker and a bottom portion 9.

Next, as shown in FIG. 1 d), after removing the photoresist film 5, boron ions are
Ion implantation is performed at 0 keV and at a dose of IQ''(I'1l-2) to form a low yield p-type impurity implantation region 10.

Next, as shown in FIG. A p-type base region 12 is formed.

Next, as shown in FIG. 1(f), phosphorus ions are selectively accelerated directly onto the surface of the p+ type base region 11 and the p− type base region 12 by aligning a portion with the gate '4 pole 7 and increasing the energy Ion implantation is performed at ~l 50 ke'V and a dose lid IQ"ff-2 to form an n-type source immersion castle 13.

Next, as shown in FIG. 1(g), four layers of one PSG film are selectively etched on the surface including the gate electrode 7.

The P8U film 14 is left on the sidewalls of the gate electrode 7, and the surfaces of the p+ type base region 11 and the p− type base region 12 are exposed. Next, a north electrode 15 is formed by depositing an Iluminescent layer over the entire image. Next, p + type silicon substrate 1
A drain pole 16 is provided on the 0 surface to constitute an M-type field effect transistor.

Here, the gate force, 7, is the pressure V. ! 1 (off)
If the thickness of the gate oxide film 3 is constant and the ion implantation element and process are the same, the peak of the base region adjacent to the north region 13 is approximately determined by degrees.

In order to secure a base region 13 that does not affect the gate cutoff voltage vG8 (.ff) due to diffusion in the lateral force direction of the p+ type diffusion region 11, [Controlling the etching width of pole 7 in the lateral force direction. In this way, the source area 11
Because the base resistance directly below can be sufficiently lowered,
It is possible to prevent a voltage drop in this part during device operation.

It is possible to increase the strength of the gate and the gate, and also to control the gate force and the voltage vGs (.ff).

! FIG. 2 is a diagram of a semiconductor chip for explaining the second embodiment of the present invention.

As shown in FIG. 2, except that an n-type gate electrode 17 and an n-type evitor P7 layer 2 having a thickness of about 1 to 20 μm were sequentially grown and provided on a p+ type 7 silicon substrate l.
It has the same configuration as the embodiment.

Here, by providing an n+ type gate electrode on the p-type 7 recon itgml, the sil"type"/recon group+bLl
The injection efficiency of a few thousand Yari γ from γ decreases. Therefore, it is possible to roughly prevent a voltage drop in the base region below the source 13, so that the withstand voltage of the chip can be increased.

[Effect of the invention] By forming a region, the switching force and to-off voltage v08
This has the effect of controlling (.ff) and increasing the power of the pupil, cheerleader, and pupil.

[Brief explanation of drawings]

FIGS. 1(a) to (ml) are cross-sectional views of a semiconductor oak 1 shown in the order of steps for explaining a first embodiment of the present invention, and FIG. 2 is a cross-sectional view for explaining a second embodiment of the present invention. This is.l...p+ type 7 recon basis, 2...n
- type epitaxial layer, 3... gate modified film,
4... Polycrystalline silicon layer, 5... Photoresist film, 6... Opening, 7... Gate pole, 8... High concentration p-type impurity implantation region,
9...r/darka, toto, lO...low concentration p-type impurity implantation region, 11...p+ type base region, 12...p- Type base area, 13...
... Source Renjo, 14゛ ... PSG film, 1
5...North electrode, 16...Drain pole, 17...Meter type Eviter? 7ya #Im, 1
8...Be-X area.

Claims (1)

[Claims] (A) A gate insulating film is formed on an epitaxial layer of an opposite conductivity type provided on a semiconductor substrate of one conductivity type, and a gate electrode is selectively formed on the gate insulating film. (B) using the gate electrode as a mask to ion-implant high concentration impurities of one conductivity type into the surface of the epitaxial layer; (C) etching only the side surfaces of the gate electrode to narrow the width of the gate electrode; (D) ion-implanting a low concentration impurity of one conductivity type using the gate electrode as a mask; (E) forming a second base region having a low concentration of impurities adjacent to the first base region; (E) selecting a second base region on the surfaces of the first and second base regions with a portion aligned with the gate electrode; 1. A method for manufacturing a vertical field effect transistor, comprising the step of forming a source region of opposite conductivity type.