JPH0334579A - Nonvolatile semiconductor storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To facilitate micronization by making the first gate insulating film under a floating gate into a tunnel insulating film wherein one part above the channel region caught by source and drain diffusion layers becomes a rewriting region. CONSTITUTION:The first gate insulating film 3 is formed on a substrate region where elements are separated, and on the film 3 a floating gate 5 is formed of the first polycrystalline silicon film. The second gate insulating film 6 is formed at the surface of the floating gate 5, and on this a control gate 7 is laminated and made by the second layer polycrystalline silicon film. The rewriting region for transferring charge between the floating gate 5 and a substrate 1 is formed partially above a channel region. That is, at the center in the channel length direction of the channel region caught by source and drain diffusion layers 8 and 9, one part of the first gate insulating film 3 is used as a tunnel insulating film 4, and this place is made a rewriting region. The region of this tunnel insulating film 4 makes slender stripe shape crossing the channel region in the channel width direction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a nonvolatile semiconductor memory device using a rewritable memory cell having a floating gate and a control gate, and a method for manufacturing the same.

(Prior Art) As a nonvolatile semiconductor memory device, one using a memory cell having a MOS (MOS) transistor structure having a floating gate and a control gate is known. Among them, the one that can be electrically rewritten is known as EEFROM.

Typical EEFROM memory cell structures are:
They are FLOTOX type, FET M, and OS type.

FIG. 6 is a plan view showing the structure of a FLOTOX type memory cell and a cross-sectional view taken along line AA' thereof. This memory cell has p
n+ type source and drain diffusion layers 22 and 23 spaced apart from each other are formed on a type silicon substrate 21, a floating gate 26 is formed on the channel region with a first gate insulating film 24 interposed therebetween, and a second gate insulating film is further formed on the floating gate 26. A control gate 28 is formed through the film 27. The drain diffusion layer 23 is
It has a portion 231 that is formed to extend a predetermined distance below the end of the floating gate 26. 1st below floating gate 26
This drain diffusion layer 23 in the gate insulating film 24.
A thin tunnel insulating film 25 is partially formed in the upper portion, and this serves as a rewriting region where charges are exchanged between the extended plate and the floating gate.

The manufacturing process for obtaining this memory cell structure will be briefly described. First, a drain diffusion layer 231 is formed on a device-isolated substrate in a portion that will become a rewriting region of a gate region. After that, a first gate insulating film 24 is formed. Then, a part of this gate insulating film 24 is selectively etched to expose the substrate surface, and a tunnel insulating film 25 is formed by thermal oxidation.

Thereafter, a first layer polycrystalline silicon film is deposited, and this is selectively etched to form a layer for floating gate isolation on the element isolation region, after which an 11-layer insulating film 26 and a second layer polycrystalline silicon film are sequentially deposited. do. Then, these are patterned to form separate control gates 28 and floating gates 26.

This FLOTOX type memory cell has a drawback in that the manufacturing process is complicated. That is, it is necessary to form a part of the drain diffusion layer in advance before forming the gate electrode.
Further, a portion of the first gate insulating film must be etched to form a tunnel insulating film. Therefore, three PEP steps are required to form the device, including the patterning steps for the control gate and floating gate. Moreover, the tunnel insulating film must be formed on the drain diffusion layer.
It is also necessary to have a margin for this purpose. Also, since the source and drain diffusion layers are not formed in a self-aligned manner with the gate,
The variation in channel length will also be large.

On the other hand, FIGS. 7(a) and 7(b) show a plan view and a sectional view taken along the line AA' of the FETMO8 type memory cell structure. In this structure, a thin first gate insulating film 34 through which a tunnel current can flow is formed over the entire channel region of a p-type silicon substrate 31 with element isolation, a floating gate 35 is formed on this, and a second gate insulating film 34 is formed on this. Gate insulating film 3
A control gate 37 is formed through the gate 6. The control gate 37 and floating gate 35 are formed to have the same gate length by successively etching two layers of polycrystalline silicon films in the same manner as described in the manufacturing process of the FLOTOX type memory cell. Using these stacked gates as a mask, impurity ions are implanted to form source and drain diffusion layers 32 and 33 that are self-aligned to the gates.

This FETM OS type memory cell is FLOTO
Compared to the X-type, the manufacturing process is simpler, the source and drain are self-aligned with the gate, so there is no need for alignment margins, miniaturization is possible, and there is less variation in channel length. has. However, this FETMOS type memory cell has a problem in that a high voltage must be applied to the control gate during rewriting. In other words, in the FETMOS type, since the entire surface above the channel region is a thin tunnel insulating film, the FLO
Compared to the TOX type, the capacitance between the floating gate and the substrate is large, and the coupling capacitance between the floating gate and the control gate is relatively small. Therefore, in order to apply a high voltage to the floating gate during rewriting, a sufficiently high voltage of 20 V, for example, must be applied to the control gate. This means that it is necessary to have sufficient punch-through resistance between adjacent cells under the element isolation region, and that sufficient consideration must also be given to the reliability of peripheral circuits.

(Problems to be Solved by the Invention) As described above, the conventional EEPROM memory cell has FL
The OTOX type has the disadvantage that it requires a large number of manufacturing steps and has a complicated structure, making it difficult to miniaturize, while the FETMOS type can be miniaturized, but has the disadvantage of requiring high voltage during rewriting.

The present invention has been made in view of the above points, and is
An object of the present invention is to provide a nonvolatile semiconductor memory device having a memory cell structure that combines the advantages of the FETMOS type and the FETMOS type, and a method for manufacturing the same.

[Structure of the Invention] (Means for Solving the Problems) A memory cell of a nonvolatile semiconductor memory device according to the present invention includes:
The source and drain diffusion layers are formed in self-alignment with the control gate and the floating gate, and the first gate insulating film under the floating gate is formed with the source and drain diffusion layers.

A feature is that a part of the channel region sandwiched between the drain diffusion layers is a tunnel insulating film that becomes a rewriting region.

The method of the present invention deposits a first layer conductor film to be used as a floating gate via a tunnel insulating film over the entire surface of a semiconductor substrate with device isolation, and selectively etches this to separate the floating gate on the device isolation region. After forming a trench for use as a control gate, a second conductor film to be used as a control gate is deposited thereon via an interlayer insulating film. Thereafter, using a mask with a predetermined pattern, the second layer conductor film is selectively etched to form the control gate, and the same mask is used to selectively etch the interlayer insulating film and the first layer conductor film thereunder to form the floating gate. Separate and form. Then, by isotropic etching, the tunnel insulating film under the floating gate is etched horizontally to a predetermined depth, and an oxide film thicker than the tunnel insulating film is formed in the gap formed under the floating gate by thermal oxidation. do. Thereafter, impurities are doped using the control gate as a mask to form source and drain diffusion layers.

(Function) The memory cell according to the present invention is common to the FETMOS type in that the source and drain diffusion layers are self-aligned with the gate. As a result, there is no variation in channel length,
Further, it is possible to miniaturize the cell, and even when it is miniaturized, excellent cell characteristics can be obtained. Moreover, the entire surface of the channel region is not a tunnel insulating film, but only a portion thereof is a tunnel insulating film. Therefore, the capacitance between the control gate and the floating gate can be made relatively larger than the capacitance between the floating gate and the substrate compared to the FETMOS type. That is, FLO
It has the advantages of TOX type and FE-7MO3 type.

Furthermore, according to the method of the present invention, there is no need for a PEP process for selectively forming a tunnel insulating film, which is required in the manufacture of conventional FLOTOX memory cells. There is no need for a step of forming a part of the drain diffusion layer in the element region before forming the gate. Furthermore, no alignment allowance is required for overlapping the tunnel insulating film region on the drain diffusion layer. Therefore, it is possible to miniaturize the memory cell with a simple process that is almost the same as the manufacturing process of the conventional FETMO8 type memory cell, and a memory cell with less variation in channel length can be obtained.

(Example) The present invention will be explained in detail below.

FIG. 1 shows the structure of one memory cell portion of an EEFROM according to an embodiment. (a) is a plan view, (b) (c)
are AA' and BB' cross-sectional views of (a), respectively. A thick element isolation insulating film 2 is formed in the element isolation region of the p-type silicon substrate 1 . A first gate insulating film 3 is formed in the element-isolated substrate region, and a floating gate 5 is formed thereon by a first layer polycrystalline silicon film.

A second gate insulating film 6 is formed on the surface of the floating gate 5,
A control gate 7 is laminated thereon using a second layer polycrystalline silicon film. The floating gate 5 and the control gate 7 are
They are patterned simultaneously in the channel length direction and are formed to have the same gate length. and control gate 7
N+ type source and drain diffusion layers 8 and 9 are formed in the substrate in self-alignment with the floating gate 5. In the channel width direction, the floating gates 5 are separated on the element isolation region and are independent for each cell, and the control gates 7 are continuously arranged in a plurality of cells to form word lines.

A rewriting region for transferring charge between the floating gate 5 and the substrate 1 is partially formed on the channel region.

That is, in the central part of the channel region sandwiched by the source and drain diffusion layers 8.9, the first
A part of the gate insulating film 3 is used as a thin tunnel insulating film 4,
This is the rewriting area. As shown in FIG. 1(a), the region of this tunnel insulating film 4 has an elongated stripe shape that traverses the channel region in the channel width direction.

The manufacturing process of this memory cell structure will be explained with reference to FIGS. 2(a) to 2(d). After forming an element isolation insulating film 2 on a substrate 1 according to a normal process, a 50%
Tunnel insulating film 4 made of ~200 silicon oxide film
is formed on the entire surface, and then a first layer polycrystalline silicon film 5° for forming a floating gate is deposited on the entire surface. 1st
The layered polycrystalline silicon film 5.degree. is formed to a thickness of 500 to 4000 mm by, for example, the LPCVD method. Further, this first layer polycrystalline silicon film 5° is doped with an impurity such as phosphorus or arsenic in order to impart conductivity. Next, the first polycrystalline silicon film 5° is selectively etched by reactive ion etching to form floating gate isolation grooves on the element isolation regions. Then, the second gate insulating film (
An interlayer insulating film) 6 is formed. The second gate insulating film 6 is, for example, a triple layer of a silicon oxide film, a silicon nitride film, and a silicon oxide film. That is, a first silicon oxide film with a thickness of 80 to 200 Å is formed by thermal oxidation of 5 degrees of the first layer polycrystalline silicon film, and then a silicon oxide film of 80 to 200 Å is formed on this film by CVD.
A silicon nitride film with a size of 0 is deposited. Thereafter, a second silicon oxide film of 80 to 200 layers is further formed on the surface of the nitride film by thermal oxidation. After that, the first layer of polycrystalline silicon l! is used to form a control gate on the entire surface. 17 o to 50
The film is deposited to a thickness of 0 to 4000 Å, and doped with impurities in the same manner as the first layer polycrystalline silicon film (FIG. 2(a)).

After this, a second layer polycrystalline silicon film 7° is formed by reactive ion etching after a normal PEP process.

The second gate insulating film 6 and the first polycrystalline silicon film 5° are sequentially etched to separate the control gate 7 and floating gate 5 (FIG. 2(b)).

Thereafter, the tunnel insulating film 4 under the floating gate 5 is laterally etched by an isotropic etching method in which the etching rate for the silicon oxide film is higher than that for silicon, such as a solution etching method using ammonium fluoride. For example, set the horizontal etching depth to 0.3μ.
m or more, a state in which a gap 10 is formed under the floating gate 5 is obtained (FIG. 2(C)).

After that, thermal oxidation is performed to oxidize the surface of the substrate 1 exposed directly under the end of the floating gate 5 and the lower surface of the floating gate 5, so that a first oxide film made of an oxide film thicker than the tunnel insulating film 4 is formed in the gap 10. The gate insulating film 3 is in a buried state. Next, using the control gate 7 as a mask, impurity ions are implanted to form source and drain diffusion layers 8.9 (FIG. 2(d)).

After this, although not shown, the entire surface is covered with a CVD oxide film according to the usual process, contact holes are made, and bit lines and the like are arranged using an Al film, thereby completing the process.

The operation of the memory cell according to this embodiment will be explained.

Electron injection into the floating gate 5 is performed by keeping the source, drain, and substrate at a low potential, for example, ground potential, and applying a positive high voltage to the control gate 7. As a result, electrons are injected from the n-type inversion layer formed in the channel region into the floating gate 5 through the tunnel insulating film 4, and the threshold value of the memory cell moves in the positive direction. When electrons from the floating gate 5 are to be emitted to the substrate side, the source, drain, and substrate are kept at a low potential, for example, the ground potential, and a negative high voltage is applied to the control gate 7. As a result, the electrons in the floating gate 5 are emitted to the substrate through the tunnel insulating film 4, and the memory cell enters a state in which the threshold value moves in the negative direction. Electrical rewriting is performed by making one of these electron injection and electron emission correspond to data writing and the other to data erasing. Data reading is performed by applying a read voltage intermediate between the threshold value of the "0" state and the threshold value of the "1" state to the control gate 7, and detecting the presence or absence of current.

Note that in the memory cell rewriting operation of this embodiment,
The reason why voltages with both positive and negative polarities are used for writing and erasing is
This is due to the following reasons. In conventional FLOTOX type memory cells or FETMOS type memory cells, the rewriting region in which the tunnel insulating film is formed is located on the drain diffusion layer, or is formed in a position extremely close to the drain diffusion layer, even if it does not completely overlap. Therefore, by applying a high positive voltage to the drain diffusion layer and setting the control gate to the ground potential, electrons in the floating gate can be emitted to the substrate side.

In other words, selective writing and selective erasing can be performed using only positive voltage. However, in the memory cell structure of this embodiment, the rewriting region in which the tunnel insulating film is formed is formed in the center of the channel region, away from the drain diffusion layer. For this reason, the electrons in the floating gate cannot be effectively released to the substrate under the same potential relationship as in the prior art. It is possible to emit electrons from the floating gate by applying a high positive voltage to the substrate at the same time as the drain diffusion layer, but this does not allow for selectivity in memory cells along the word line direction where the control gates are commonly connected. There isn't. However, if electron emission from the floating gate is used, for example, as a bulk erase operation,
It is possible to use only positive voltages.

According to this embodiment, like the FETMOS type memory cell, the source and drain are self-aligned with the gate, so that variations in channel length are eliminated, and a memory cell with a fine structure can be obtained. Since the tunnel insulating film is partially formed on the channel region, the coupling capacitance between the floating gate and the control gate is relatively large compared to the FETMO8 type, and therefore the voltage applied to the control gate during rewriting is reduced by F E T
It can be lower than the MOS type. In addition, its manufacturing process does not require complicated processes unlike the FLOTOX type memory cell.

As a method for obtaining the memory cell of the present invention, a process similar to the FLOTOX type memory cell assembly can be used for forming the tunnel insulating film.

FIGS. 3(a) to 3(e) are cross-sectional views showing the manufacturing process of such an embodiment. Parts corresponding to those in the previous embodiment are given the same reference numerals as in the previous embodiment. A first gate insulating film 3 having a thickness of 300 to 400 Å is formed on a device-isolated p-type silicon substrate 1 by thermal oxidation, and the first gate insulating film 3 in the rewriting area is selectively etched using a hydrofluoric acid solution or reactive ion etching. do. Then, a tunnel insulating film 4 with a thickness of 50 to 200 Å is formed on the exposed substrate surface by thermal oxidation (
Figure 3(a)). Thereafter, as in the previous embodiment, the LPCV
First layer polycrystalline silicon film 5 which becomes a floating gate by D method
An interlayer insulating film 6 is formed on this film, and a second layer polycrystalline silicon film 7°, which will become a control gate, is deposited and impurities are doped into it (Fig. 3). (b)). The interlayer insulating film 6 has a three-layer structure similar to the previous embodiment, and after two layers are formed, an isolation trench is formed on the element isolation region of the floating gate. and P
By EP process and reactive ion etching, the second layer polycrystalline silicon film 7° to the first layer polycrystalline silicon film 5° are continuously processed to form the control gate 7 and floating gate 5.
Then, source and drain diffusion layers 8.9 are formed by ion implantation of impurities (FIG. 3(C)).

In the method of this example, compared to the method of the previous example,
Although there is a drawback that the rewriting region is shifted from the center of the channel region due to mask misalignment, the same effects as in the previous embodiment can be obtained except for this point.

The present invention is not limited to the above embodiments. For example, in the manufacturing process described in FIG. 2, the substrate surface exposed in the step in FIG. 2(e) is partially etched by reactive ion etching to form shallow recesses 11, as shown in FIG. You can. As shown in FIG. 5, the substrate 1 is an n-type silicon substrate 1 in which a p-type well 1□ is formed in the memory cell array region, and a p-type well 12 is formed in the same manner as in the above embodiment. Memory cells can also be formed. For example, the p-type well 12 may be common to the entire memory cell array region, or may be formed separately for each appropriate memory array block.

In addition, in the embodiment, only one memory cell section was explained, but
The cell array system may be a NOR type in which one memory cell is connected to the bit line and a common control gate for multiple memory cells in the word line direction, or a NOR type in which multiple memory cells are connected to the source and drain. It is also possible to form a NAND type by connecting them in series so that adjacent ones can be shared.

The pond water invention can be implemented with various modifications without departing from the spirit thereof.

[Effects of the Invention] As described above, the present invention provides a nonvolatile semiconductor memory device that has a memory cell structure that combines the advantages of the FETMO3 type and the FLOTOX type, is easily miniaturized, and has high reliability. Obtainable.

[Brief explanation of drawings]

FIGS. 1(a), (b), and (c) are a plan view and a cross-sectional view showing the memory cell structure of an EEFROM according to an embodiment of the present invention, and FIGS. 2(a) to (d) are specific manufacturing steps thereof. 3(a) to (C) are sectional views corresponding to FIG. 1(b) showing other manufacturing steps.
), FIG. 4 is a process cross-sectional view corresponding to FIG. 2(C) of a memory cell of another example, and FIG. 5 is a cross-sectional view showing a memory cell structure of still another example. Figures 6(a) and 6(b) are diagrams and cross-sectional views of conventional FLOTOX type memory cells, and Figures 7(a) and (b) are plan views and cross-sectional views of conventional FETMOS type memory cells. . 1...p-type silicon substrate, 2...element isolation insulating film,
3: First gate insulating film, 4: Tunnel insulating film,
5... Floating gate, 5°... First layer polycrystalline silicon film, 6... Second gate insulating film (interlayer insulating film) 7...
・W control gate, 0...Second layer polycrystalline silicon film, 8°9...n+ type diffusion layer, 0...Gap.

Claims (4)

[Claims] (1) Sources formed spaced apart from each other on a semiconductor substrate;
A drain diffusion layer, these sources, a floating gate formed on a channel region sandwiched between the drain diffusion layers via a first gate insulating film, and a control layer formed on the floating gate via a second gate insulating film. In a nonvolatile semiconductor memory device in which memory cells having gates are integrated,
The source and drain diffusion layers are formed in a self-aligned manner with the control gate, and a tunnel insulation layer is formed on a portion of the first gate insulating film on the channel region sandwiched between the source and drain diffusion layers to serve as a rewriting region. A nonvolatile semiconductor memory device characterized in that a film is formed. (2) The nonvolatile semiconductor memory device according to claim 1, wherein the tunnel insulating film of the rewriting region is formed in a stripe shape elongated in the channel width direction at the center of the channel region. (3) A step of forming a thin tunnel insulating film over the entire element region of the device-isolated semiconductor substrate, and then depositing a first layer conductor film on the entire surface of the substrate, and selectively etching the first layer conductor film to form the device. forming a floating gate isolation groove on the isolation region; forming an interlayer insulating film on the surface of the first layer conductor film; and depositing a second layer conductor film on the entire surface; A mask is formed on the film, the second layer conductor film is selectively etched using the mask to form a control gate, and the same mask is subsequently used to sequentially select the interlayer insulating film and the first layer conductor film thereunder. A process of separating and forming a floating gate by etching, a process of etching the tunnel insulating film under the floating gate to a predetermined depth in the lateral direction by isotropic etching using the obtained control gate and floating gate as a mask, and thermal oxidation. and forming an oxide film thicker than the tunnel insulating film in the gap directly under the edge of the floating gate from which the tunnel insulating film has been removed; and doping the substrate with impurities using the control gate as a mask to diffuse source and drain. 1. A method of manufacturing a nonvolatile semiconductor memory device, comprising: a step of forming a layer; and a step of forming a layer. (4) The interlayer insulating film between the first layer conductor film and the second layer conductor film includes a first silicon oxide film, a silicon nitride film, and a second silicon oxide film.
4. The method of manufacturing a nonvolatile semiconductor memory device according to claim 3, wherein the nonvolatile semiconductor memory device is formed of a triple layer of silicon oxide films, and is formed after forming the floating gate isolation trench.