JPH0334610A - Arbitrary waveform generator - Google Patents

Abstract

PURPOSE:To heighten the resolution of an output waveform by the resolving capability of a pulse width modulation by adding pulse width modulation data corresponding to the variation polarity of waveform data to the least significant bit(LSB) of waveform data outputted from a pattern generator. CONSTITUTION:In the case that output data of a pattern generator 1 is added to a D/A converter 2 and converted to an analog, it is varied greatly by the resolution of one level such as '0' 1 2 .... Therefore, output data of an adder 8 is added and converted to an analog signal. Accordingly, it is varied a small amount of the resolution of a 1/4 level such as '0' 1/4 2/4 ...3/4 2 .... In such a way, an output signal whose level is varied by the resolution being higher than the resolution of the D/A converter 2 can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an arbitrary waveform generator, and more particularly, to high resolution of an output waveform.

<Prior Art> FIG. 4 is a block diagram showing an example of a conventional arbitrary waveform generator. The waveform data of multiple bits (e.g. 8 bits) output from the pattern generator 1 is transferred to the D/A converter 2.
In addition to this, the analog signal is converted into an analog signal, and this analog signal is output via the low-pass filter 3.

<Problems to be Solved by the Invention> However, the resolution of the output waveform in such a configuration is limited by the resolution of the D/A converter 2, and the
It was not possible to obtain an output waveform with a resolution higher than that of the /A converter 2.

The present invention has focused on these points, and its purpose is to provide an arbitrary waveform generator that has a relatively simple configuration and can obtain an output waveform with a resolution higher than that of a D/A converter. There is a particular thing.

Means for Solving the Problems> The arbitrary waveform generator of the present invention converts waveform data output from a pattern generator into an analog signal using a D/A converter, and outputs this analog signal via a low-pass filter. In the arbitrary waveform generator configured to
Modulation data for outputting modulation data for applying monotonically increasing or monotonically decreasing pulse width modulation to the lowest pitch data of the waveform data output from the pattern generator according to the determination result of the change polarity determining means. generating means; and adding means for adding the modulated data output from the modulated data generating means and the waveform data output from the pattern generator and outputting the output data to the D/A converter. It is characterized by

Effect> In the high-resolution output mode, pulse width modulation data corresponding to the change polarity of the waveform data is added to the least significant bit (LSB) of the waveform data output from the pattern generator.

As a result, the resolution of the output waveform is increased by the amount of resolution of the pulse width modulation.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention, and the same parts as in FIG. 4 are given the same reference numerals. In the figure, the output data of the pattern generator 1 is applied to one input terminal of the selector 4 and is also applied to the high resolution block 5. This high resolution block 5 applies pulse width modulation to the LSB of the output data of the pattern generator 1. This high-resolution block 5 includes a change polarity discrimination circuit 6 that discriminates the change polarity of the waveform data output from the pattern generator 1, and a change polarity discrimination circuit 6 that determines the change polarity of the waveform data output from the pattern generator 1 in accordance with the discrimination result of the change polarity discrimination circuit 6. A modulation data generation circuit 7 outputs modulation data for monotonically increasing or decreasing pulse width modulation on the LSB of waveform data, and the modulation data output from the modulation data generation circuit 7 and the pattern generator 1 are The adder 8 adds the waveform data and adds the output data to the other input terminal of the selector 4. In addition, selector 4
selects the data to be input to the D/A converter 2 according to the operation mode, and in the case of low resolution output mode similar to the conventional one, the waveform data output from the pattern generator 1 is sent out and the main In the high-resolution output mode according to the invention, the output data of the adder 8 of the high-resolution block 5 is sent out.

When configuring as a device exclusively for high-resolution output mode,
Such a selector 4 can be omitted.

The operation of the device configured in this way will be explained.

Figure 2 shows that the resolution of the monotonically increasing output waveform is essentially 2
It is an explanatory diagram of the operation when increasing the bit.

In this case, the modulation data generator 7 generates (LSB) (MSB) 0000000 as shown in (a) and below.
0 <1 clock> oooooooo.

ooooooooo.

ooo, ooooo.

10000000 ooooooooo.

ooooooooo.

ooooooooo.

10000000 ooooooooo.

10000000 ooooooooo.

10000000 10000000 ooooooooo.

Modulation data that changes periodically in units of 16 clocks is output to the adder 8 using 10000000<16 clocks> as a unit block. Here, when these series of modulation data are divided every 4 clocks, L
The weight of SB is set to increase by 1 bit. That is, L in the first section of 1 to 4 clocks
S B are all set to 0, the LSB in the second interval from 5 to 8 clocks is set to 1 for 5 clocks and 0 for other clocks, and the LSB in the third interval from 9 to 12 clocks is 9, The 11th clock is set to 1 and the other clocks are set to O, and the LSB in the fourth section of the 13th to 16th clocks is set to 0 only for the 14th clock and 1 for the other clocks. By converting such data into an analog signal using the D/A converter 2 and applying it to the low-pass filter 3, the average value of the analog signal in the first section becomes 0.
, the average value of the analog signal in the second section is 1/4, the average value of the analog signal in the third section is 2/4, the average value of the analog signal in the fourth section is 3/4, and so on. 174 every
It will increase monotonically.

On the other hand, as shown in (b) and below, the pattern generator 1 generates the following: <1.6 clocks> Waveform data updated every 16 clocks is added to the adder 8.
Output to. Such waveform data is, for example, calculated in advance and stored in the pattern generator 1, and is read out sequentially in accordance with a clock when the high-resolution output mode is selected.

The adder 8 adds the output data of the modulation data generator 7 and the output data of the pattern generator 1 and outputs waveform data as shown in (c) and below.

(LSB) (MSB) 00000000<1 clock>10000000<16clock>10000000<1clock> (d) shows the analog signal converted and output from the D/A converter 2, and (e) shows the output of the low-pass filter 3. Showing a signal. Further, (f> indicates output data of the pattern generator 1 in analog form.

As is clear from these, when the output data of the pattern generator 1 is added to the D/A converter 2 and converted into an analog signal, the resolution becomes large as O→1→2→... However, when the output data of the adder 8 is added to the D/A converter 2 and converted into an analog signal, it changes from 0 to 1.
D
An output signal whose level changes with a resolution higher than that of the /A converter 2 can be obtained.

Specifically, for example, if the operation in the conventional low-resolution output mode is to output a 100MHz frequency waveform for two periods with an 8-bit resolution at an IGHz tarok frequency, the high-resolution output mode of the above embodiment According to the above, assuming that the memory areas are equal, a 100 MHz frequency waveform can be output for 1/4 period with a resolution of 10 bits.

FIG. 3 is a block diagram showing another embodiment of the present invention,
In FIG. 0, which shows an example of a circuit that operates in the same manner as the operation explanatory diagram in FIG. Detects an increase or decrease in the number of bits, and outputs 10-bit data to which the lower two bits are added as LSB pulse width modulation data to the memory 10 according to the result. Between each waveform data, four types of 2-bit data (00, 01, 10, 11) are added to change each waveform data by 1/4 level in four steps as shown in Fig. 2(e). Outputs 4 pieces of data. 10 written in memory 10
The upper eight bits of the bit waveform data are read out to the selector 4 and adder 14 via the latch 11 as data shown in FIG. 2(b). On the other hand, the added lower two bits of data are read out to the decoder 12. The decoder 12 converts the 2-bit lower order data into the data shown in FIG.
) is decoded into the LSB data string of the modulation data and output to the shift register 13. i.e. "'oo"
is converted to “0000” in the first interval, and “01” is converted into the second interval.
'10' is converted to '1000' in the third interval, '11' is converted to '1010' in the third interval, and '11' is converted to '1010' in the fourth interval.
The output data of the shift register 13 is applied to the adder 14 and added to the LSB of the 8-bit output data added via the latch 11.

As a result, the adder 14 outputs the data shown in FIG. 2(c).

+ IGHz clock 1 is added as a shift clock for the D/A converter 2 and shift register 13,
Tarock 2 of 250 MHz is added as a load clock for the memory 10 and shift register 13.

Even in such a configuration, high-speed, low-resolution output and low-speed, high-resolution output can be selectively obtained, as in FIG. 1.

In the above embodiment, an example in which the level is changed in steps of 174 levels has been described, but the level resolution may be set as appropriate depending on the purpose.

Furthermore, when the waveform data decreases, the modulation data may be decreased by a predetermined level resolution.

Further, the pattern generator may be one that outputs desired pattern data according to a predetermined program, or may be one that stores measurement waveforms as digital data, such as a digital oscilloscope.

<Effects of the Invention> As described above, according to the present invention, it is possible to realize an arbitrary waveform generator that can obtain an output waveform with a resolution higher than that of a D/A converter with a relatively simple configuration.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is an explanatory diagram of the operation of Fig. 1, Fig. 3 is a block diagram showing another embodiment of the invention, and Fig. 4 is a conventional device. It is a block diagram showing an example. l... pattern generator, 2... D/A converter, 3.
...Low pass filter, 5...High resolution block, 6
... Change polarity discrimination circuit, 7... Modulation data generator,
8...Adder.

Claims (1)

[Claims] An arbitrary waveform generator configured to convert waveform data output from a pattern generator into an analog signal using a D/A converter and output the analog signal via a low-pass filter, a change polarity determining means for determining the change polarity of the waveform data output from the pattern generator; and a change polarity determining means for determining the change polarity of the waveform data output from the pattern generator; modulation data generation means for outputting modulation data for applying increasing or monotonically decreasing pulse width modulation; An arbitrary waveform generation device comprising: an adding means for outputting output data to the D/A converter.