JPH0334624A - Mos transistor circuit - Google Patents

Abstract

PURPOSE:To improve the degree of integration by constituting the subject circuit so that exclusive OR can be obtained by four pieces of PMOS transistors and three pieces of NMOS transistors. CONSTITUTION:A source of a first PMOS transistor 31 is connected to a powder source terminal VDD, and as for a first NMOS transistor 41, its drain is connected to a drain of the MOS transistor 31, and as for a second PMOS transistor 32, its drain is grounded(GND), and as for a second NMOS transistor 42, its source is connected to a source of the transistor 32, and its drain is connected to the drain of the transistor 41. Also, as for a third PMOS transistor 33, its source is connected to the VDD, its gate is connected to the drain of the transistor 31, and as for a third NMOS transistor 43, its source is connected to the GND, its gate is connected to a source of the transistor 32, and as for a fourth PMOS transistor 34, its source is connected to a source of the transistor 41, and its gate is connected to an input terminal 1. In such a way, the degree of integration is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a MOS transistor circuit, and relates to a patented exclusive OR circuit.

[Conventional technology]

Conventionally, there has been a circuit shown in FIG. 2(a) as a circuit for realizing this type of exclusive OR.

Click the button in Fig. 2(a) and select 1. Between the second input terminal 1゜2 and the output terminal 3, two NOR gates 4゜5 and AN
The D gate 6 is υ, and these υ constitute an exclusive OR.

FIG. 2(b) shows that the MOS transistor
This is a circuit that realizes the circuit a).

The NOR gate 4 in FIG. 2(a) is composed of a PMO8 transistor 11.12 and an NMO8) range metal 23.24, and the NOR gate 5 in FIG.
The AND gate 6 in FIG. 2(a) is composed of an O8 transistor 16.17, an NMOS transistor 26.27, and a PMO8 transistor 13, 14.15.
It is composed of NMOS transistors 21, 22, and 25.

Next, the circuit operation will be explained using FIG. 2(a). First, number 1. logic level at the second input terminal 1.2.
If Low (hereinafter referred to as below) is input, N
The output of the OR gate 4 is a logic level High (high level) (
(hereinafter referred to as H), the output of AND gate 6, NOR,
The output of the gate 5 becomes L, and the output terminal 3 becomes L.

Next, when L is input to input terminal IKH and input terminal 2, and when L is input to input terminal 1 and H is input to input terminal 2, the output of NOR gate 4 and AND gate 6 are both
The output is L%N0)1. The output of the gate 5 becomes H, and the output terminal 3 becomes H.

Next, when H is input to both input terminals 1 and 2, NO
The output of R gate 4 is L%, and the output of gate 6 is H, N.
The output of the OR gate 5 becomes L, and the output terminal 3 becomes L.

As explained above, the circuit of FIG. 2(a) forms an exclusive OR circuit.

[Problem to be solved by the invention]

Since the conventional exclusive OR MOS transistor circuit described above is configured as shown in FIG. 2(b), seven PMO8 transistors and seven NMOS transistors are required. When configuring a semiconductor integrated circuit with a large number of MOS transistors, there is a drawback that the area becomes large and wiring becomes difficult.

It is an object of the present invention that the above-mentioned drawbacks are solved and that an MO
An object of the present invention is to provide a MOS transistor circuit which has a small number of S transistors and can be easily wired.

[Means to solve the problem]

The configuration of the MOS transistor circuit of the present invention includes a first MOS transistor whose one pole is connected to a power supply terminal and whose gate is connected to a first input terminal, and whose other pole is connected to the first MOS transistor.
a second MOS transistor connected to the other pole of the OS transistor and whose gate is connected to the first input terminal; and a second MOS transistor whose other pole is connected to one pole of the second MOS transistor and whose gate is connected to the first input terminal. a third MOS transistor connected to the first input terminal, one pole connected to one pole of the third MOS transistor, a gate connected to the first input terminal, and the other pole grounded. a fourth MOS transistor; a fifth MOS transistor having one pole connected to the power supply terminal, a gate connected to the other pole of the first MOS transistor, and another pole connected to the output terminal; a sixth MOS transistor whose one pole is grounded, whose gate is connected to one pole of the fourth MOS transistor, and whose other pole is connected to the output terminal; a seventh MOS transistor whose gate is connected to the first input terminal, and whose other pole is connected to the output terminal and one pole of the second MOS transistor; It is characterized by having a terminal.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing a MOS transistor circuit according to an embodiment of the present invention.

In FIG. 1, in the MOS transistor circuit of this embodiment, the source of the first PMO8 transistor 1 is connected to the power supply terminal VDD, and the gate is connected to the first input terminal 1. Furthermore, the drain of the first NMO8 transistor 41 is connected to the drain of the MOS transistor 31, and the gate is connected to the first input terminal l. The drain of the second PMO8 transistor 2 is grounded (GN
D), and the gate is connected to input terminal l. Second
The ONMO8 transistor 42 has a source connected to the source of the transistor 32, a gate connected to the input terminal 1, and a drain connected to the drain of the transistor 41. The third PMO8 transistor 33 has a source connected to VDD, a gate connected to the drain of the transistor 31, and a drain connected to the output terminal 3. The source of the third NMOS transistor 43 is G.
ND, its gate is connected to the source of the transistor 32, and its drain is connected to the output terminal 3. The fourth PMO8 transistor 34 has a source connected to the source of the transistor 41, a gate connected to the input terminal 1, and a drain connected to the output terminal 3. The second input terminal 2 is connected to the source of the transistor 41.

The operation of the exclusive OR CMOS transistor circuit configured in this manner will be described.

When the input terminal l is initially H, the transistor 31°32
．． 34 is off, and transistors 41 and 42 are on. Therefore, the logic level of input terminal 2 is the same as that of transistor 4.
1 and is transmitted to the gate of transistor 33, and also passes through transistor 42 and is transmitted to the gate of transistor 43. At this time, when H is input to input terminal 2,
The transistor 33 is turned off, the transistor 43 is turned on, and the output terminal 3 becomes L. When L is input to the input terminal 2, the transistor 33 is turned on, the transistor 43 is turned off, and the output terminal 3 becomes H.

Next, when input terminal 1 is L, transistors 31°32.
34 is on and transistors 41 and 42 are off, so
The gate of transistor 33 becomes HP, transistor 33 is turned off, and the gate of transistor 43 becomes L, transistor 43 is turned off. Therefore, the logic level of the input terminal 2 is transmitted to the output terminal 3 through the transistor 34. At this time, when H is input to input terminal 2, output terminal 3 becomes H1.When L is input to input terminal 2, output terminal 3
becomes L.

As explained above, the transistor circuit shown in FIG. 1 constitutes an exclusive OR circuit.

〔Effect of the invention〕

As explained above, the present invention provides at least four PM
Exclusive OR can be obtained using an OS transistor and three NMOS transistors, compared to a conventional similar circuit that requires seven PMOS transistors and seven NMOS transistors. This has the effect that the area of the integrated circuit can be reduced and the degree of integration can be improved.

[Brief Description of the Drawings] Fig. 1 is a circuit diagram showing a MOS transistor circuit according to an embodiment of the present invention, Fig. 2(a) is a conventional logic circuit diagram, and Fig. 2(b) is a circuit diagram showing a MOS transistor circuit according to an embodiment of the present invention. FIG. 3 is a circuit diagram in which the conventional logic circuit diagram in a) is realized using MOS transistors. 1.2...Input terminal, 3...Output terminal, 4.5...NOR gate, 6...A
ND gate, 11° to 17, 31. ~34...
・・PMOS transistor, 21 to 27, 41.42
．． 43...NMOS transistor.

Claims (1)

[Claims] a first MOS transistor having one pole connected to a power supply terminal and a gate connected to a first input terminal; the other pole being connected to the other pole of the first MOS transistor and having a gate connected to the first input terminal; a second MOS transistor connected to the input terminal of the second MOS transistor, a third MOS transistor whose other pole is connected to one pole of the second MOS transistor and whose gate is connected to the first input terminal; MOS with third pole
connected to one pole of the transistor, and whose gate is connected to the first
A fourth M connected to the input terminal of
an OS transistor, one pole connected to the power supply terminal;
and a fifth MOS whose gate is connected to the other pole of the first MOS transistor and whose other pole is connected to the output terminal.
a sixth MOS transistor whose one pole is grounded, whose gate is connected to one pole of the fourth MOS transistor, and whose other pole is connected to the output terminal, and whose one pole is connected to the second MOS transistor. connected to one pole of the transistor,
and a seventh MOS transistor whose gate is connected to the first input terminal and whose other pole is connected to the output terminal, and a second MOS transistor whose gate is connected to one pole of the second MOS transistor.
A MOS transistor circuit comprising an input terminal.