JPH033475B2 - - Google Patents

Info

Publication number
JPH033475B2
JPH033475B2 JP57229461A JP22946182A JPH033475B2 JP H033475 B2 JPH033475 B2 JP H033475B2 JP 57229461 A JP57229461 A JP 57229461A JP 22946182 A JP22946182 A JP 22946182A JP H033475 B2 JPH033475 B2 JP H033475B2
Authority
JP
Japan
Prior art keywords
output
circuit
motor
down counter
counted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57229461A
Other languages
Japanese (ja)
Other versions
JPS59123484A (en
Inventor
Tetsuo Maeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57229461A priority Critical patent/JPS59123484A/en
Publication of JPS59123484A publication Critical patent/JPS59123484A/en
Publication of JPH033475B2 publication Critical patent/JPH033475B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02PCONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P23/00Arrangements or methods for the control of AC motors characterised by a control method other than vector control
    • H02P23/22Controlling the speed digitally using a reference oscillator, a speed proportional pulse rate feedback and a digital comparator

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Control Of Direct Current Motors (AREA)
  • Rotational Drive Of Disk (AREA)
  • Control Of Electric Motors In General (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、レコードプレーヤ等に用いられるモ
ータの制御回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a control circuit for a motor used in a record player or the like.

従来例の構成とその問題点 一般にレコードプレーヤ等に用いられるモータ
は、一定速度で回転する事が必要であり、速度制
御を行なう。第1図はその制御回路の一従来例で
ある。モータ10の回転信号は周波数発電器1
1、増幅回路12、微分回路13によつてFGパ
ルスとして検出され、制御回路1の端子1bへ加
えられる。端子2は回転数を設定するためにあ
り、FGパルスの周期T1が基準時間T0より大、す
なわち回転数が遅い場合には、T1−T0の間制御
回路1の端子1dがハイレベルとなり、トランジ
スタ4がオンし、抵抗5を通して電流を吸込み、
反転増幅器8を通してモータ10に正転トルクを
与える。逆にT1<T0の場合は、T0−T1の間トラ
ンジスタ3がオンして電流を流し出し、モータ1
0に逆転トルクを与える。例えば、電源電圧を
Vcc、抵抗5,7の値をそれぞれR5,R7、電源
9からの基準電圧をVcc/2とすると、モータ1
0両端の電圧VMは下記式で与えられる。なお、
コンデンサ6はモータ電圧を平滑する為にある。
Conventional configuration and its problems Motors used in record players and the like generally need to rotate at a constant speed, and the speed is controlled. FIG. 1 shows a conventional example of the control circuit. The rotation signal of the motor 10 is generated by the frequency generator 1
1. It is detected as an FG pulse by the amplifier circuit 12 and the differentiation circuit 13, and is applied to the terminal 1b of the control circuit 1. Terminal 2 is provided to set the rotation speed, and if the period T 1 of the FG pulse is greater than the reference time T 0 , that is, the rotation speed is slow, the terminal 1d of the control circuit 1 goes high between T 1 and T 0 . level, transistor 4 turns on and sinks current through resistor 5,
Normal rotation torque is applied to the motor 10 through the inverting amplifier 8. Conversely, if T 1 < T 0 , transistor 3 is turned on during T 0 - T 1 and current flows out, causing motor 1
Apply reverse torque to 0. For example, the power supply voltage
Vcc, the values of resistors 5 and 7 are R 5 and R 7 respectively, and the reference voltage from power supply 9 is Vcc/2, motor 1
The voltage V M across 0 is given by the following formula. In addition,
Capacitor 6 is provided to smooth the motor voltage.

VM=R7/R5・Vcc/2・T1−T0/T1 …… すなわち、負荷トルクとつり合うモータ電圧
VMを生ずる周期T1でモータ10は回転する事に
なる。しかしながらこのような従来回路では、負
荷による回転数のずれが大きいという問題があつ
た。
V M = R 7 /R 5・Vcc/2・T 1 −T 0 /T 1 …… In other words, the motor voltage that balances the load torque
The motor 10 will rotate with a period T1 that produces V M. However, such a conventional circuit has a problem in that the rotational speed varies greatly depending on the load.

発明の目的 本発明は上記従来の欠点を解消するもので、負
荷による回転数のずれを小さくできるモータ制御
回路を提供することを目的とする。
OBJECTS OF THE INVENTION The present invention solves the above-mentioned conventional drawbacks, and an object thereof is to provide a motor control circuit that can reduce deviations in rotational speed due to load.

発明の構成 上記目的を達するため、本発明のモータ制御回
路は、モータの周波数発電器からのFG信号をパ
ルスに整形する波形整形回路と、この波形整形回
路から出力されたFGパルスの周期T1と基準時間
T0とを比較してその差に比例した電圧もしくは
それと等価なデユーテイ比を持つパルスを出力す
る出力手段と、アツプダウンカウンタと、このア
ツプダウンカウンタの各ステージの出力をラツチ
するラツチ回路と、このラツチ回路の出力をアナ
ログに変換するD/Aコンバータとを備え、T1
>T0の場合にはT1−T0の間、前記アツプダウン
カウンタを第1の基準クロツクでカウントアツプ
し、T0>T1の場合にはT0−T1の間、前記アツプ
ダウンカウンタをカウントダウンし、このカウン
ト値を前記ラツチ回路により第2の基準クロツク
でラツチし、これを前記D/Aコンバータによつ
てアナログ量に変換しこのアナログ量と前記出力
手段の出力とを合成した量によつてモータを制御
する構成としたものである。
Structure of the Invention In order to achieve the above object, a motor control circuit of the present invention includes a waveform shaping circuit that shapes an FG signal from a frequency generator of a motor into pulses, and a period T 1 of the FG pulse output from this waveform shaping circuit. and reference time
an output means that compares T0 and outputs a voltage proportional to the difference or a pulse having an equivalent duty ratio; an up-down counter; and a latch circuit that latches the output of each stage of the up-down counter. Equipped with a D/A converter that converts the output of this latch circuit into analog,
>T 0 , the up-down counter is counted up by the first reference clock during T 1 - T 0 , and when T 0 > T 1 , the up-down counter is counted up during T 0 - T 1 . The counter is counted down, this count value is latched with the second reference clock by the latch circuit, this is converted into an analog quantity by the D/A converter, and this analog quantity and the output of the output means are combined. The configuration is such that the motor is controlled depending on the amount.

実施例の説明 以下、本発明の一実施例について、図面に基づ
いて説明する。
DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

第2図は本発明の一実施例を示す回路図で、第
1図に示す構成要素と同一の構成要素には同一の
符号を付してその説明を省略する。制御回路1の
加速出力及び減速出力はアンドゲート回路15,
16の一方の入力端に供給され、他の入力端には
端子20からクロツク信号が加えられる。ゲート
回路15,16の出力はアツプダウンカウンタ1
7のダウン入力端、アツプ入力端にそれぞれ供給
され、アツプダウンカウンタ17の各ステージの
出力はラツチ回路18によつてFGパルスの周期
毎にラツチされる。ラツチ回路18の出力はD/
Aコンバータ19によつて電流に変換され、反転
増幅器8の入力に加算される。すなわち第3図の
様に基準時間T0よりFGパルスの周期T1が長い場
合は、T1>T0の期間ゲート回路16が開き、ク
ロツクによつてアツプダウンカウンタ17はカウ
ントアツプされる。T1−T0である限りこの動作
はくり返され、D/Aコンバータ19の吸込み電
流Icは増加し続け、トランジスタ4による加速パ
ルスと加算される。すなわち、モータ10の両端
の電圧VMは VM=R7/R5・Vcc/2・T1−T0/T1+K 〓n (Tn−To) … ここに、KはD/Aコンバータ19等の変換係
数である。T1>T0である限り、上記式右辺の
第2項は増加し続け、その値が負荷に対応する
VMと等しくなつた状態でT1=T0となつて定速回
転する事になる。T1<T0の場合はT0−T1の期間
アツプダウンカウンタ17はカウントダウンさ
れ、Icが小さくなる(場合によつては付号が変わ
る)が、基本的な動作は同様である。
FIG. 2 is a circuit diagram showing an embodiment of the present invention, in which the same components as those shown in FIG. 1 are given the same reference numerals and their explanations will be omitted. The acceleration output and deceleration output of the control circuit 1 are provided by an AND gate circuit 15,
16, and a clock signal from terminal 20 is applied to the other input. The outputs of gate circuits 15 and 16 are up-down counter 1
The output of each stage of the up-down counter 17 is latched by a latch circuit 18 at every cycle of the FG pulse. The output of the latch circuit 18 is D/
It is converted into a current by the A converter 19 and added to the input of the inverting amplifier 8. That is, when the period T 1 of the FG pulse is longer than the reference time T 0 as shown in FIG. 3, the gate circuit 16 is opened for a period of T 1 >T 0 and the up/down counter 17 is counted up by the clock. This operation is repeated as long as T 1 -T 0 , and the sink current Ic of the D/A converter 19 continues to increase and is added to the acceleration pulse from the transistor 4. That is, the voltage V M across the motor 10 is V M = R 7 /R 5・Vcc/2・T 1 −T 0 /T 1 +K 〓 n (Tn−To)... Here, K is the D/A converter. It is a conversion coefficient of 19 mag. As long as T 1 > T 0 , the second term on the right side of the above equation continues to increase, and its value corresponds to the load.
When V M is equal to T 1 = T 0 , it rotates at a constant speed. If T 1 <T 0 , the up-down counter 17 counts down during the period of T 0 -T 1 and Ic becomes smaller (the number may change depending on the case), but the basic operation is the same.

なお14はインバータである。また第3図は第
2図に示す回路の各部波形図で、aは基準信号、
bはFGパルス、cは制御回路1の端子Icから出
力される減速信号、dは制御回路1の端子1dか
ら出力される加速信号、eはD/Aコンバータ出
力電流Icである。
Note that 14 is an inverter. In addition, FIG. 3 is a waveform diagram of each part of the circuit shown in FIG. 2, where a is a reference signal,
b is the FG pulse, c is the deceleration signal output from the terminal Ic of the control circuit 1, d is the acceleration signal output from the terminal 1d of the control circuit 1, and e is the D/A converter output current Ic.

発明の効果 以上説明したように本発明によれば、T1>T0
の場合にはT1−T0の間、アツプダウンカウンタ
を第1の基準クロツクでカウントアツプし、T0
>T1の場合にはT0−T1の間、アツプダウンカウ
ンタをカウントダウンし、第2の基準クロツクで
カウント値をラツチし、D/Aコンバータによつ
てアナログ量に変換し、これと出力手段の出力と
を合成した量によつてモータを制御するようにし
たので負荷による直流的な回転数変動のないモー
タ制御を実現し得る。
Effects of the Invention As explained above, according to the present invention, T 1 > T 0
In the case of T 1 - T 0 , the up-down counter is counted up with the first reference clock, and T 0
> T 1 , the up-down counter counts down during T 0 - T 1 , the count value is latched by the second reference clock, converted to an analog quantity by the D/A converter, and output from this. Since the motor is controlled by the amount obtained by combining the outputs of the means, it is possible to realize motor control without direct current fluctuations in the rotational speed due to the load.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来回路の回路図、第2図は本発明の
一実施例におけるモータ制御回路の回路図、第3
図はT1>T0の場合のモータ制御回路の各部信号
波形図である。 1…制御回路、2…回転数設定端子、3,4…
トランジスタ、5,7…抵抗、6…コンデンサ、
8…駆動増幅器、9…電源、10…モータ、11
…周波数発電器、12…FG増幅器、13…微分
回路、14…インバータ、15,16…アンドゲ
ート、17…アツプダウンカウンタ、18…ラツ
チ回路、19…D/Aコンバータ、20…基準ク
ロツク入力端子。
Fig. 1 is a circuit diagram of a conventional circuit, Fig. 2 is a circuit diagram of a motor control circuit in an embodiment of the present invention, and Fig. 3 is a circuit diagram of a motor control circuit according to an embodiment of the present invention.
The figure is a signal waveform diagram of each part of the motor control circuit when T 1 >T 0 . 1...Control circuit, 2...Rotation speed setting terminal, 3, 4...
Transistor, 5, 7...Resistor, 6...Capacitor,
8... Drive amplifier, 9... Power supply, 10... Motor, 11
...Frequency generator, 12...FG amplifier, 13...Differential circuit, 14...Inverter, 15, 16...AND gate, 17...Up-down counter, 18...Latch circuit, 19...D/A converter, 20...Reference clock input terminal .

Claims (1)

【特許請求の範囲】[Claims] 1 モータの周波数発電器からのFG信号をパル
スに整形する波形整形回路と、この波形整形回路
から出力されたFGパルスの周期T1と基準時間T0
とを比較してその差に比例した電圧もしくはそれ
と等価なデユーテイ比を持つパルスを出力する出
力手段と、アツプダウンカウンタと、このアツプ
ダウンカウンタの各ステージの出力をラツチする
ラツチ回路と、このラツチ回路の出力をアナログ
量に変換するD/Aコンバータとを備え、T1
T0の場合にはT1−T0の間、前記アツプダウンカ
ウンタを第1の基準クロツクでカウントアツプ
し、T0>T1の場合にはT0−T1の間、前記アツプ
ダウンカウンタをカウンドダウンし、このカウン
ト値を前記ラツチ回路により第2の基準クロツク
でラツチし、これを前記D/Aコンバータによつ
てアナログ量に変換し、このアナログ量と前記出
力手段の出力とを合成した量によつてモータを制
御する構成としたモータ制御回路。
1. A waveform shaping circuit that shapes the FG signal from the motor frequency generator into pulses, and the period T 1 and reference time T 0 of the FG pulse output from this waveform shaping circuit.
an up-down counter, a latch circuit that latches the output of each stage of the up-down counter, and a latch circuit that latches the output of each stage of the up-down counter. Equipped with a D/A converter that converts the output of the circuit into an analog quantity, T 1 >
In the case of T 0 , the up-down counter is counted up with the first reference clock during T 1 - T 0 , and in the case of T 0 > T 1 , the up-down counter is counted up between T 0 - T 1 . is counted down, this count value is latched with the second reference clock by the latch circuit, this is converted into an analog quantity by the D/A converter, and this analog quantity and the output of the output means are combined. A motor control circuit configured to control the motor based on the amount of the motor.
JP57229461A 1982-12-28 1982-12-28 Control circuit for motor Granted JPS59123484A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57229461A JPS59123484A (en) 1982-12-28 1982-12-28 Control circuit for motor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57229461A JPS59123484A (en) 1982-12-28 1982-12-28 Control circuit for motor

Publications (2)

Publication Number Publication Date
JPS59123484A JPS59123484A (en) 1984-07-17
JPH033475B2 true JPH033475B2 (en) 1991-01-18

Family

ID=16892560

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57229461A Granted JPS59123484A (en) 1982-12-28 1982-12-28 Control circuit for motor

Country Status (1)

Country Link
JP (1) JPS59123484A (en)

Also Published As

Publication number Publication date
JPS59123484A (en) 1984-07-17

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