JPH033487A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To increase the effective light receiving area by using a 1st transistor(TR) storing a photoelectric charge to a control electrode section and amplifying and outputting the optical charge and a 2nd TR for resetting the stored photoelectric charge so as to control the signal readout. CONSTITUTION:A 1st TR MS1 storing a photoelectric charge to a control electrode and amplifying and outputting a photoelectric charge and a 2nd TR MS2 to reset the stored photoelectric charge are used to control the signal readout operation. Thus, number of TRs and wiring are decreased to increase the effective photodetection area, and a high aperture rate is kept even in a high integrated circuit sensor and high sensitivity is attained. Moreover, simultaneous readout of signal and dark output and its subtraction processing are implemented with a circuit of simple constitution to realize high S/N.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device that accumulates photocharges in a control electrode portion, amplifies and outputs the photocharges from a main electrode portion. [Prior Art] Conventionally, a photoelectric conversion device that outputs an amplified signal by accumulating optical signal charges in the gate of a MOS transistor has been described, for example, in the Technical Report of the Television Society of Japan, D1005 (November 1986). , JP-A-63-2
Some of them are disclosed in Japanese Patent No. 76377 and the like. FIGS. 7 and 8 are circuit configuration diagrams showing one pixel of a sensor of the conventional photoelectric conversion device. In FIGS. 7 and 8, Ma and M4 are MOS transistors that input the photocharges accumulated in the photodiodes D, D, to their gates, amplify them, and output them, respectively.
, M is the MO for selecting a two-dimensional row of pixels.
S transistor, M. M6 is a MOS transistor for resetting the photocharge of the photodiode, and Ls and Ls are signal output lines. These pixels have the advantage that the accumulated optical signal is amplified and output, so that the S/N ratio is not dominated by noise in the readout circuit system. [Problems to be Solved by the Invention] However, in the above conventional example, as shown in FIGS. 7 and 8, one pixel is composed of three transistors, so the number of wires connected to one pixel is also small. In most highly integrated sensors with small pixel areas, the effective light-receiving area of the pixel is significantly reduced, resulting in poor sensitivity.Also, since each pixel operates as one amplification element, There is also a problem in that variations in the offset of each pixel appear as fixed pattern noise, which limits the S/N ratio. [Means for Solving the Problems] The photoelectric conversion device of the present invention has It has a first transistor that accumulates photocharges in a control electrode portion, amplifies and outputs the photocharges, and a second transistor that resets the accumulated photocharges, and the second transistor One main electrode section is electrically connected to the output side main electrode section of the first transistor, and the other main electrode section of the second transistor is electrically connected to the control electrode section of the first transistor. In this application, "electrically connected" refers to not only a case where a plurality of electrode parts are formed in the same area, but also a case where a plurality of electrode parts are formed in different areas, and each area is connected. This includes the case where they are connected by wiring etc.

[Effect]

In the present invention, a signal readout operation is performed using a first transistor that accumulates photocharges in a control electrode portion, amplifies and outputs the photocharges, and a second transistor that resets the accumulated photocharges. The purpose is to increase the effective light receiving area by reducing the number of transistors and wiring. Furthermore, simultaneous reading of the signal and dark output and subtraction processing are facilitated, and a high S/N ratio is achieved. [Example] Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 is a circuit configuration diagram of a signal readout circuit system of a first embodiment of a photoelectric conversion device of the present invention. The following embodiments are examples in which the present invention is applied to a solid-state imaging device, but the present invention is not necessarily limited to such embodiments.
For example, it can also be used as a line sensor. In order to simplify the explanation, this embodiment shows a signal readout circuit for two rows and two portions of sensor pixels. As shown in FIG. 1, one sensor pixel S (indicated by a broken line in the figure) includes an amplification MOS transistor M□, a reset MOS transistor M0, and a photodiode D□.
It consists of Note that the source of the reset MO3 transistor M3□ is electrically connected to the gate of the amplification MO3 transistor Msl, and the drain of the reset MOS transistor M0 is electrically connected to the drain of the amplification MOS transistor M31. Note that when forming such a sensor pixel on a semiconductor substrate, the source of the reset MO3 transistor M□ and the gate of the amplification MO3h transistor Ms+ are formed in the same semiconductor region, and the drain of the reset MOS transistor Msa and the amplification MO3h transistor Ms+ are formed in the same semiconductor region. The drain of transistor M□ (MOS) can be formed in the same semiconductor region. Of course, it is also possible to form the source region, gate region, and drain region separately and connect them with wiring. Other sensors have similar configurations. In addition, M for amplification
O3 transistor M1, reset MO3 transistor Mst, and load transistor Ma. M7. is an n-type MOS transistor, and bipolar transistors Tr and Tx are explained as NPN-type bipolar transistors, but each is an n-type MOS transistor)
A transistor or a PNP bipolar transistor may be used. In FIG. 1, My+, 71/ItIl are load transistors, CI, caIC, , C, for forming an inverting amplifier together with the amplification transistor M□ in the pixel.
4 is the capacitance for accumulating the output from each pixel, M
Rl, M * * + M Fl s + M
+114 is a MOS transistor for transferring the pixel output to the capacitors 01 to C4, and Jl and J* are drive lines connected to the gates of the upper and lower transfer MOS transistors M91 to M□, respectively.0M□, MHII MH8N MH
4 are MOS transistors for transferring the signals accumulated in the capacitors 01 to C4 to the horizontal signal line H according to the output of the horizontal shift register 2, and T+ and Ts are MOS transistors whose emitters are for amplification of the sensor pixels in the readout row. It is a bipolar transistor that is connected to the source of and applies a constant voltage to the source. Mv1. Mvs is connected to the gate of the reset MOS transistor in the sensor pixel, and is a MOS transistor for selecting the reset row according to the output of the vertical shift register. This is a MOS transistor for selecting a row to be read based on the output from the vertical shift register 1. R
Reference numeral 1 denotes a drive line that transmits a pulse that provides timing for reading, and R represents a drive line that transmits a pulse that provides timing for setting the beam. A+ and As are amplifiers for taking out the sensor output. FIG. 2 is a partial circuit configuration diagram of the signal readout circuit system. The partial circuit configuration diagram shown in FIG. 2 is for explaining the characteristic part of the present invention, and as mentioned above, the emitter of the bipolar transistor T1 is an amplifying MOS transistor M.
It is connected to the source of □ and supplies source potential VOO. The amplification MOS transistor M□ and the MOS transistor M〒1 serving as a load constitute an inverting amplifier. FIG. 3 is a characteristic diagram showing the input/output characteristics of the inverting amplifier shown in FIG. 2. In the figure, ■ is a value where V IN=V ouy. The gain (-g) of the inverting amplifier is determined by the amplification MO3 transistor M□ and the MOS transistor MT.
It depends on the structural parameters of 1. Also, the input voltage range that maintains the gain -g is from MOS transistor to vo. −
■This is the current range. Hereinafter, a reading method from one sensor pixel will be explained using FIGS. 1 to 3. The signal read operation consists of three basic operations: read operation, reset operation, and storage operation. When the row of sensor pixels to be read is the first row, the base potential of the bipolar transistor TI rises to a high level, and the source potential vms of the inverting amplifier is supplied. At this time, the vertical output line is connected to an amplification MOS transistor M that changes according to the photocharge accumulated in the photodiode.
If the output potential corresponding to the gate potential of □ is set, a read operation can be performed. Next, the gate potential of the reset MOS transistor M3□ is set to a low level, and the reset MOS transistor M□ is turned on. At this time, the gate potential of the amplifier MO3) transistor M□ becomes V as shown in FIG. 3, and a reset operation can be performed. Next, reset -OS) transistor M. The gate potential of the bipolar transistor T is returned to a high level to turn off the reset MOS transistor M□, and the base potential of the bipolar transistor T is set to a low level.
The source of transistor Mll is set to ground potential (GND). In this state, the accumulation operation is started, and the electrode potential of the photodiode D□ connected to the gates of the amplification MOS transistors M and I rises from V in accordance with the amount of photocharge accumulated. In this accumulation operation, the gate potential of the amplification MOS l-transistor M□ is 71 or more, and the gate voltage of the reset MOS transistor M0 is at a high level, but even when pixels in other rows are being read out, Since the potential of the vertical output line does not exceed V, the amplification MOS transistor M□ and the reset MOS transistor M are connected. Both are always in the OFF state and do not affect the readout of other pixels. Next, the operation shown in FIG. 1 will be explained using FIG. 4. FIG. 4 is a timing chart of drive pulses of the photoelectric conversion device shown in FIG. 1. First, when a high level signal is applied to the drive line R1 and a high level signal is applied to the drive line J1, the output signal of the pixel in the row selected by the vertical shift register 1 is accumulated in the capacitor C,,C, be done. Next, when a low level signal is applied to the drive line R2, the pixels are reset. When a high-level signal is applied to the drive line R, and a high-level signal is applied to the drive line J, the output of the reset pixel, that is, the dark output, is accumulated in the capacitors C,,C,. After completing the read operation by setting the drive line R2 as a low level signal, the signal voltage and dark voltage on the capacitors are transferred to the amplifiers A and A3 according to the outputs of the upper and lower horizontal shift registers 2.
Output sequentially from If a subtraction process is performed outside the signal readout circuit system to subtract the dark output of the amplifier A2 from the signal output of the amplifier A1, a sensor signal without fixed pattern noise in the dark caused by variations in the dark output from pixel to pixel can be obtained. . FIG. 5 is a circuit configuration diagram of a photoelectric conversion section of a second embodiment of the photoelectric conversion device of the present invention. Note that the phototransistor is omitted for convenience of explanation. The constituent members of one sensor pixel are the same as the constituent members of one sensor pixel S shown in FIG.
One main electrode of the OS transistor Msm is connected to the drain of the amplification MOS transistor M□ of the adjacent sensor pixel. FIG. 6 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. In the figure, an image sensor 201 in which optical sensors are arranged in an area is subjected to television scanning by a vertical scanning section 202 and a horizontal scanning section 203. The signal output from the horizontal scanning section 203 is sent to the processing circuit 20.
4 as a standard television signal. Drive pulse φ for vertical and horizontal scanning units 202 and 203
(1) φM+, φHII φvs, φsil, φv2, etc. are supplied by the driver 205. Also driver 20
5 is limited by controller 206. [Effects of the Invention] As explained in detail above, the photoelectric conversion device of the present invention has the following features:
The signal readout operation can be controlled by a first transistor that accumulates photocharges in the control electrode portion, amplifies and outputs the photocharges, and a second transistor that resets the accumulated photocharges. By reducing the number of transistors and wiring, it is possible to increase the effective light-receiving area, maintain a high aperture ratio even with highly integrated sensors, and achieve high sensitivity. The simultaneous readout and subtraction processing can be performed by an integrated circuit with a simple configuration, and a high S/N can be achieved. 3
An amplifier having a negative gain can be constructed by connecting one main electrode of the transistor and making the amplification gain of the first transistor negative. By connecting the emitter of a bipolar transistor whose collector is connected to a constant voltage source to the main electrode on the side, the source potential can be changed arbitrarily, so that when one pixel outputs, it is not affected by other pixels. It is possible to provide an area sensor without false signals.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram of a signal readout circuit of a first embodiment of a photoelectric conversion device of the present invention. FIG. 2 is a partial circuit configuration diagram of the signal readout circuit system. FIG. 3 is a characteristic diagram showing the input/output characteristics of the inverting amplifier shown in FIG. 2. FIG. 4 is a timing chart of drive pulses of the photoelectric conversion device shown in FIG. 1. FIG. 5 is a circuit configuration diagram of a photoelectric conversion section of a second embodiment of the photoelectric conversion device of the present invention. FIG. 6 is a schematic configuration diagram of a solid-state imaging device to which the present invention is applied. FIGS. 7 and 8 are circuit configuration diagrams showing one pixel of a sensor of the conventional photoelectric conversion device. Mal. MTI. M y 3. Cs. A2: M□, Ml8. Ml: MOS transistor,
M, ,: MOS transistor, M Vl+ Mvi. Mv4: MOS transistor, CI I Cz +C4
:Capacitance, R,,Ri :Drive line, A,. Amplifier.

Claims (5)

[Claims] (1) It has a first transistor that accumulates photocharges in the control electrode section, amplifies and outputs the photocharges, and a second transistor that resets the accumulated photocharges, and the second transistor one main electrode part of the transistor is electrically connected to the output side main electrode part of the first transistor, and the other main electrode part of the second transistor is connected to the control electrode part of the first transistor. Electrically connected photoelectric conversion device. (2) The photoelectric conversion device according to claim 1, wherein the control electrode portion of the first transistor and the main electrode portion of the second transistor electrically connected to the control electrode portion are formed in the same semiconductor region. (3) At the main electrode portion on the output side of the first transistor,
2. The photoelectric conversion device according to claim 1, wherein one main electrode portion of the third transistor is connected, and the amplification gain of the first transistor is negative. (4) The photoelectric conversion device according to claim 1, wherein the emitter of a bipolar transistor whose collector is connected to a constant voltage source is connected to the main electrode portion of the first transistor on the side other than the output side. (5) The photoelectric conversion device according to claim 1, wherein the first transistor and the second transistor are insulated gate transistors.