JPH0334921Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to semiconductor integrated circuits, and particularly to digital integrated circuits.

(Prior art) Generally used digital integrated circuits such as demultiplexers are described in the literature, "Integrated Circuit Application Handbook" edited by Takuo Kanno (1986-6-30), Asakura Shoten.
It is described on pages 290-293.

FIG. 3 is a circuit diagram of a 1:4 demultiplexer. 1 is a data input terminal, 2 is a clock input terminal, 3 to 10 are data output terminals, 11 is a quarter clock output terminal, 13 to 22 are D-type flip-flops, 23 to 31 are super buffer circuits;
The area within the broken line 2 constitutes a logic circuit, and the area within the broken line 33 constitutes an output buffer circuit. In order to input a clock signal with a repetition frequency of 2 GHz to the clock input terminal 2 of this demultiplexer and operate it,
A logic circuit is formed using GaAs shot gate field effect transistors (hereinafter abbreviated as MESFET). Also, data output terminals 3 to 10 and 1/
Since the 4-clock output terminal 11 is normally connected to a transmission line whose characteristic impedance is 50Ω, its output impedance must be set to 50Ω. However, since the output impedance of the D-type flip-flops 13, 19-22 is as high as several hundred ohms or more, an output buffer circuit 33 is formed to amplify the current of these output signals.

Although the explanation here uses a demultiplexer as an example of a digital integrated circuit, GaAs
A digital integrated circuit that operates at high speed using MESFET is composed of a logic circuit and an output buffer circuit.

(Problems to be Solved by the Invention) However, in the digital integrated circuit having the above configuration, the output buffer circuit is a super buffer circuit as shown in FIG. 4, but the logic amplitude at the signal output terminal 42 is 0.8. ~1V and an output impedance of 50Ω, the gate width of normally-off GaAs MESFETs Q3 and Q4 should be set to 400 μm each, and the normally-off GaAs MESFETs Q3 and Q4 should be
MESFETQ2 and normally-on GaAs
The gate width of MESFETQ1 is 150μm and 75μm respectively.
Must be m. On the other hand, D inside the logic circuit
The gate width of the GaAs MESFETs constituting the type flip-flops 13 to 22 (see FIG. 3) can be 20 μm or less. Therefore, while the logic circuit 32 shown in Fig. 2 can be formed in an area of 0.4 mm ² on the wafer, only the output buffer circuit 33 can be formed.
Occupies an area of 0.4mm ² .

As described above, when attempting to lower the output impedance of a GaAs digital integrated circuit, the pattern area of the output buffer section becomes large. Therefore, the object of this invention is to reduce the size of the output buffer circuit and provide a digital integrated circuit with excellent ability to drive external loads.

(Means for solving the problem) This idea is based on a semiconductor integrated circuit that includes a Si semiconductor substrate, an output buffer circuit using bipolar transistors formed on the Si substrate, and a region in which the output buffer circuit is formed. A GaAs single crystal layer stacked on this Si substrate, a logic circuit using a field effect transistor formed on this GaAs single crystal layer, and a low resistance body connecting these logic circuits and an output buffer circuit. It is equipped with the following.

(Function) As described above, this idea uses GaAs, which can operate at high speed, for logic circuits in semiconductor integrated circuits.
Since FETs are used and Si bipolar transistors with a small area and low impedance are used in the output buffer circuit, it is possible to obtain a digital integrated circuit that is small and has excellent ability to drive external loads.

(Embodiment) FIG. 1 is a cross-sectional structural diagram of a digital integrated circuit for explaining one embodiment of the present invention, which will be explained below with reference to the drawings. The emitter, collector, base, and resistor regions 51 of the Si bipolar transistor are formed in the Si substrate 50 by ion implantation and diffusion. Next, a GaAs epitaxial layer 53 is MOCVDed to a thickness of 1 μm on the Si substrate 50.
or MBE method, and is formed in a region within the epitaxial layer 53 and separated from the region 51.
The active layer of the GaAs MESFET is formed by ion implantation. Next, the GaAs epitaxial layer on the region 51 of the Si bipolar transistor and resistor is removed, and the electrode 52 of the Si bipolar transistor and resistor is formed on the region 51 of the Si substrate 50, and the electrode of the GaAs MESFET and the first Layer wiring 54 is formed. After forming the interlayer insulating film 55, openings are selectively formed in this insulating film 55 and the second layer wiring 56 is formed.
A digital integrated circuit with a mixture of MESFET and Si bipolar transistors is formed.

FIG. 2 is an equivalent circuit diagram of an emitter follower circuit forming an output buffer circuit formed using the Si bipolar transistor of the above embodiment, 43 and 44 are power supply terminals, Q5 is a Si bipolar transistor, 45 is resistance. In FIG. 2, the resistor 45 is set to 50Ω, and the emitter length of the Si bipolar transistor Q5 required to output a voltage amplitude of 0.8 to 1V between the output terminal 42 and the constant potential power supply terminal 44 is 150 μm, and the output buffer circuit 33 (See Figure 3) can be formed with an area of 0.15 mm ² .

Note that the GaAs MESFET and Si bipolar transistor can be formed using a conventional method.

(Effects of the invention) As explained in detail above, according to the invention, a GaAs MESFET capable of high-speed operation is used in a logic circuit.
By using a Si bipolar transistor, which is a smaller area and lower impedance element than a GaAs MESFET, in the output buffer circuit, it is possible to obtain a semiconductor integrated circuit with a smaller area and excellent ability to drive external loads.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional structural diagram of a digital integrated circuit for explaining one embodiment of the present invention, Fig. 2 is an equivalent circuit diagram of an emitter follower circuit constituting an output buffer circuit, and Fig. 3 is a circuit of a general demultiplexer. 4 are equivalent circuit diagrams of the super buffer circuit. 1...Data input terminal, 2...Clock input terminal, 3-10...Data output terminal, 11...1/4
Clock output terminal, 13-22...D flip-flop, 23-31...super buffer circuit, 32...logic circuit, 33...output buffer circuit, 40, 43, 44...constant potential power supply terminal, 41
... Input terminal, 42 ... Output terminal, 45 ... Resistor, 50 ... Si substrate, 51 ... Constituent region of Si bipolar transistor and resistor, 52 ... Electrode on Si substrate, 54 ... Electrode on GaAs layer, 55... Insulating film, 56... Wiring.

Claims (1)

[Claims for Utility Model Registration] An Si semiconductor substrate, an output buffer circuit using bipolar transistors formed on the Si semiconductor substrate, and an output buffer circuit laminated on the Si substrate excluding the area where the output buffer circuit is formed. It is characterized by comprising a GaAs single crystal layer, a logic circuit using a field effect transistor formed in the GaAs single crystal layer, and a low resistance element connecting the logic circuit and the output buffer circuit. Semiconductor integrated circuit.