JPH0335328A - Computer system - Google Patents

Abstract

PURPOSE:To carry on the data processing operation as it is even when a switch is separated by connecting an IO device which controls the input/output of data to an external part of a computer system such as a process, etc., and each computer with no intervention of a switch. CONSTITUTION:A switch 10 is not connected between the computers 1a and 1b and a controller 15 for input/output of data to an external part of a computer system. Then the transfer of data is possible between those computers and the controller 15 even though the switch 10 is separated. Thus the state of a working system or a spare system set right before separation of the switch 10 is held despite the separation of the switch 10. Therefore the input/output data can be transferred between a computer of the working system and the external part of the system. In addition, the computer of the spare system copies the latest data contents and waits so as to back up the computer of the working system. Then the working system carries on the data processing operation as it is even wen the switch 10 is separated. As a result, the switches can be exchanged with no interruption of the data processing operation and the data processing efficiency is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system that processes data of, for example, an industrial process. The standby system copies the latest data contents of the active system computer that mainly processes the data, banks up the active system, and continues processing the data before switching even when the switch switches between the active system and the standby system. Concerning computer systems that perform.

[Conventional technology]

Fig. 3 is a block diagram showing the configuration of a conventional computer system, in which the system consists of two systems A and B, in which 1a and lb are the central processing units of each system A and B (
CPU), 2a, and 2b are their respective main memories. The CPU 1a and main memory 2a of the A system are connected to an internal bus 3a, and the CPU 1b and main memory 2b of the B system are connected to an internal bus 3b. It is connected to a detachable switch 10 for switching between the two. Via the switch 10, the internal buses 3a, 3b are connected to a 10 device 15 for inputting and outputting data to and from industrial processes and the like.

Next, we will explain the operation of the bank amplifier.Normally, while either the A system or the B system operates as the operating system and the mask system which is the main body of new record data processing, the other system operates as the mask system at appropriate times. Waiting to copy the latest data and back up the mask system. If the mask system fails for some reason, the switch IO switches between the standby system and the mask system, and after switching, the system that was on standby becomes the mask system and starts operating. Meanwhile, the original mask system is repaired or replaced with a normal crystal, and the new mask system stands by to back up.

[Problem to be solved by the invention]

By the way, in the conventional computer system, the switch lO
If a failure occurs, the internal bus of each of the two systems and the 10 device 15 that controls data input/output are connected via the switch 10, so when disconnecting the switch from the computer and replacing it with a normal one, However, there was a problem in that data processing had to be interrupted, resulting in low data processing efficiency.

The present invention has been made to solve such problems, and is capable of switching by connecting ten devices that control data input/output with the outside of the system such as processes and each computer without using a switch. An object of the present invention is to provide a computer system capable of processing data from before the device is separated even when the device is separated.

[Means to solve the problem]

The computer system of the present invention includes each computer,
A switch is not connected between the data input/output control device to the outside of the system, and even when the switch is disconnected, each computer and the data input/output control device to the outside of the system can be connected.
A connection is made between the two to enable transfer of input/output data to and from the outside of the system, and even when the switch is disconnected, data can be copied from the active system to the standby system. The feature is that each computer is connected to each other.

[Effect]

In the computer system of the present invention, even when the switching device is disconnected from the computer, each computer maintains the active or standby state immediately before disconnection, and there is no input between the active computer and the outside of the system. The output data is transferred, and the standby computer copies the latest data contents and stands by in order to back up the active computer, and the active system continues to process data from before the switch was disconnected.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof. FIG. 1 is a block diagram showing the configuration of a computer system consisting of two systems A and B according to the present invention.
The configuration of the B system is the same.

In the figure, 1a and Ib are CPUs of the A system and B system, respectively, and the A system CP01a is connected to the A system main memory 2a and the A system 10 main 4a via an internal bus 3a, and is connected to the A system 10 main memory 4a via a signal line 5a. It is connected to the switching device 10.

The switch 10 is connected to a flip-flop (F/F) 11, and the F/Fil is a flip-flop (F/F) 10 that controls data input/output between the A-system CPU Ula, each computer, and the outside of the system.
System A 10 relays data input/output of System A between devices 15
It is connected to the main 4a. A system CPU1a, A system 10
The main 4a and the switch lO are connected via a signal line 14,
A mode switch 13 is connected, which includes two alternate switches for setting the processing mode of each computer, such as attachment/detachment mode, stand-alone mode, etc., and a momencriis inch (transfer switch) for commanding program and data transfer. .

For the B system, switch 10. The F/Fil and mode switch 13 are shared with the A-system, and the configuration is the same as the A-system, so a description thereof will be omitted.

Further, the A-system constant voltage power supply 6a is connected to the A-system constant voltage power supply 6a via the power supply line 7a.
system CPU 1a, A system main memory 2a + A system 10 main 4
The B-system constant voltage power supply 6b supplies the B-system CPU 1b and the B-system main memory 2b via the power supply line 7b.

A voltage of 5■ is supplied to the B-system IO main 4b. Power line 7
a is connected to the diode 8a, the power line 7b is connected to the diode 8b, and the voltages from the A system and B system are output to the signal line 9. The OR output voltage of the output 5■ is transmitted to the switch 10 through the power supply line 7c. It is supplied to F/Fil and mode switch 13. Note that power may be supplied to the IO device 15 through the power line 7c or from another power source (not shown).

FIG. 2 is a circuit diagram showing in detail a partial configuration of the computer system shown in FIG. 1. The same reference numerals as in FIG. 1 indicate the same parts, and the explanation thereof will be omitted. Bus 3al +
3a2+3a3 is a divided internal bus 3a, and bus 3aI transfers an address signal (AD), a data output signal (Do), and an output command strobe (WR). Bus 3a2 is a data input signal (DI) and A-system CP.
The response signal to U1a is transferred to the A system CPU1a, and the response signal to U1a is transferred to bus 3.
a3 is input command strobe (RD), A-system main memory 2a
Alternatively, the error signal detected by the main 4a of the A system 10 is transferred.

In the figure, 1a is the core part of the A-system CPU 1a, and the A-system C
The AD, Do, and WR signals output from the PU core 1al are output to the bus 3al via the game) 1a2. The bidirectional game Ha3 connects the bus 3a1 and the signal line 5, and is connected to the B-system bidirectional game 1b3 via the signal line 5.

Logic circuit 1a4 is switched! 510. The signals provided from the F/F 11 and the mode switch 13 are logically operated and provided to the gate 1a2 and the bidirectional gate 1a3 to control them. The signal line 5al informs the switch 10 that the normality of the A system computer is low level (L), and that the abnormality is high level ()I), and the signal line 5a2 indicates that the voltage abnormality of the power line 7b is "L", and that it is normal. Notifies the logic circuit 1a at "H".

F/Fil consists of a combination of NAND circuits, one of which
The output of the AND circuit is the A-system CPU core 1a1. logic episode 18
．． and to the switch lO.

The configuration of the B-system CPU 1b is the same as that of the A-system CPU 1a, with a bidirectional gate la3 of the A system and a bidirectional gate lb of the B system.
3 is connected via the signal line 5, and the output of the other NAND circuit of the F/F 11 is given to the B-system CPU core tb and the logic circuit 1b4.

The operating modes of the Basokua 7B system configured as above include back amplifier mode and detachable mode.

There are three independent modes, and the operation of each mode will be explained below.

Note that the mask system and bus 3a in each mode.

3h1. Transfer signal output system of signal line 5 and ■0 device 15
The relationship of the signal input/output system to is shown in Table 1.

+11 Bank up mode For example, the A system is a mask, the B system is a standby system, and the memory contents of the A system and B system are currently - matched.
It is assumed that the A-system CPU 1a executes a program by exchanging data with the A-system main memory 2a and the A-system To main 4a.

Logic circuit 1a4 opens gate 1a2 and opens bidirectional gate l.
Open a3 from the bus 3a1 to the signal line 5. Also, B
The system logic circuit 1b4 closes the gate 1b2 and opens the bidirectional gate lb3 from the signal line 5 to the bus 3b.

When the A-system CPU 1a writes data to the A-system main memory 2a or the A-system [0 main 4a, the address signal CAD output by the A-system CPU core 1al), data output signal (Do)
, the output command strobe (WR) is outputted from the bidirectional data line 11a3 to the signal line 5 via the bus 3a1 from 1a2, and is outputted to the bus 3b via the bidirectional gate lb3 of the B system, and is sent to the same address as the A system. The same data as in the A system is written to the corresponding B system main memory 2b or the B system 10 main 4b.

In addition, the A-system CPU 1a is connected to the A-system main memory 2a or the A-system IO
When reading data from the main 4a, the input command strobe (RD) is not output to the B system, and the B system data is given from the A system.

From the IO device 15 to the process, data of the A system on the mask side having control authority is output as process data.

Input data from the process is taken in by ■0 unit W15,
System 10 Outputs to both main 4a and B system [O main 4b. That is, the process input data of system A and system B always match.

Next, a description will be given of an operation in which an abnormality occurs in either the A-system CP Ula, the main memory 2a, or the 10 main 4a, which is currently masked, and the mask is switched to the B-system.

When an abnormality occurs in the A system, the A system CPU 1a stops and the output signal to the signal line 5aI changes from "L" to "11". When the switch 10 detects this, it sends a command signal to the F/F 11. The states of system A and system B are reversed. That is, the B-system logic circuit 1b opens the gate 1b2, and the bidirectional gate H
b3 from the bus 3b in the direction of the signal line 5, therefore,
An output signal from the B-system CPU core 1b flows through the bus 3b and the signal line 5 to the A-system bus 3a1.

The B-system CPU core 1b detects that the B-system has become a mask and starts executing the program. Since the B system was copying the memory contents of the A system during the standby period, the memory contents of the A system and the memory contents of the B system match at the time of switching, and data processing is not interrupted by the switching.

After switching to the B system, the A system constant voltage power supply 6a is turned off, the A system is repaired, replaced, etc. to eliminate the cause of the abnormality, and the A system constant voltage power supply 6a is turned on again. However, even while the cause of the abnormality is removed, the processing of the B system, which is a mask, is progressing, and the memory contents of the A system do not match those of the B system. Therefore, by turning on the transfer switch of the motor switch 13, the B-system CP Ulb, which is a mask, reads the contents of the B-system main memory 2b, and directly transfers this value to the B-system main memory 2b and the B-system 1.
0 Write operation is performed over the entire main 4b. By this write operation, the same content as the B system is written to the A main memory 2a and the A system IO main 4a at the same address as the B system, and the A system is on standby in case of a failure of the B system. It becomes a system.

Next, a case where the B-system constant voltage power supply 6b becomes abnormal while the B-system is in a masked state will be described. When the B-system constant voltage power supply 6b fails, the B-system CPU core 1b1. bidirectional gate lb
Since there is a possibility that the contents of the A master memory 2a may be abnormally rewritten due to abnormal output from the 3rd etc., the constant voltage power supply 6a,
A voltage monitoring circuit (not shown) is provided to monitor the output from 6b. When the output of B system constant voltage voltage #6b becomes abnormal, the voltage monitoring circuit transmits the voltage abnormality signal (BPER) to signal line 5.
a2 to the logic circuit 1a4 and the signal line 1
The output to 2a is set to "L" to indicate the occurrence of an abnormality in logic circuit 1a4.
Let me know. The logic circuit 1a4 closes the bidirectional gate 1a3 according to the applied signal, and transfers the data from the B system to the A system main memory 1.
Writing to a is prohibited. In addition, the switch lO is connected to the signal line 1
2a is detected, the F/F 11 is inverted, and the mask is switched from the B system to the A system.

(2) Attachment/disconnection mode Next, if the switch 10 breaks down, it is necessary to disconnect the switch 10 from the computer for inspection and replacement.0 In the attachment/disconnection mode, the switch 10 is disconnected from the system and the signal line 5a2+ Each logic circuit la via 5b2
The operation is similar to the bank-up mode described above except that the voltage abnormality signal applied to 411b4 is ignored. Note that malfunctions can be prevented by providing an RC filter or the like on the input side of the switching command to F/Fil.

While the switching device 10 is disconnected from the system, the A-system and B-system computers are fixed in the active or standby state before disconnection, but data processing continues and the standby system remains in operation. Copy the system's memory contents. Therefore, even while the switch is disconnected from the computer, data processing will not be hindered.

(3) Single mode When the A system is a mask and the mode switch 13 is set to the single mode, the logic circuit 1a4 of the A system is connected to the gate 1b.
2 and close the two-way gate 1b2.

Further, the B-system logic circuit 1b opens the gate 1b2 and closes the bidirectional gate lb3, thereby prohibiting copying of memory contents from the A-system to the B-system. Therefore, the A-system CPU core lal and the B-system CPU core 1b+ independently execute the programs read by each of them. That is, the A system, which is a mask, has the right to control the process, and the A system 10 main 4a has 10 devices 1.
5 and process input/output data. On the other hand, B series■0
Main 4b does not exchange data with 1015, so B
The system will be able to execute its own program, which is different from the A system.

For example, while the A system, which is a mask, is processing data,
Program debugging can be performed by connecting a terminal device, debugging tool, etc. to the B system. In addition, since the B system can operate independently from the A system, even if the B system is reset or goes down due to the execution of a program with a bug, the A
It has no effect on the system.

In this embodiment, the A system and the B system are switched by an F/F, but the configuration is not limited to this, and the same effect can be obtained even if the configuration is switched by a lanochi relay.

Furthermore, although this embodiment has a configuration in which the internal buses are separated and input/output signals are transferred, the input/output signals do not necessarily need to be transferred using different path lines, and these input/output signals may be transferred using the same path line. Similar effects can be obtained even with a configuration in which

Furthermore, in this embodiment, an example in which the CPLI core, gate, bidirectional gate, and logic circuit are mounted on the same CPU card has been described, but the invention is not limited to this. The same effect can be obtained even if it is installed in

〔Effect of the invention〕

In the computer system of the present invention, each computer and the device that controls the data output of the process are connected without a switch, and each computer is also connected without a switch, and the Data is transferred between the computer and the ■0 device regardless of whether it is disconnected, and the standby system copies the latest data from the active system, so it is possible to change the switch without interrupting data processing. It can be replaced and has the excellent effect of improving data processing efficiency.

Chapter 1 Table

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a computer system according to the present invention, FIG. 2 is a circuit diagram showing a part thereof in detail,
FIG. 3 is a block diagram showing the configuration of a conventional computer system. 1a-A system CPU 1b-B system CPU 2a-A system main memory 2b...B system main memory 3a...Internal bus 3b...Internal bus 4a...A system IO main 4
h...B system IO main 5...Signal In 10.
...Switcher 11...F/F13...Mode switch 15...IO packing device In the diagram, the same symbols are the same,
or a corresponding portion.

Claims (1)

[Claims] (1) One computer is an operating system that mainly processes data input/output via an input/output control device to the outside of the system, and at least one computer other than the above is used to update the latest data of the operating system. When each computer is switched to the active system or the standby system using a switch that can be switched to a standby system that copies the contents and makes it standby, the computer that has been switched to the active system can process data from before switching. In a computer system that continuously performs switching, each computer and input/output control device are connected so that input/output data can be transferred between them, regardless of whether the switching device is disconnected or not. A computer system characterized in that each computer is connected to each other so that data contents can be copied from an active system to a standby system regardless of whether the devices are disconnected.