JPH0335525A - Method of processing both sides of silicon wafer - Google Patents
Method of processing both sides of silicon waferInfo
- Publication number
- JPH0335525A JPH0335525A JP1171511A JP17151189A JPH0335525A JP H0335525 A JPH0335525 A JP H0335525A JP 1171511 A JP1171511 A JP 1171511A JP 17151189 A JP17151189 A JP 17151189A JP H0335525 A JPH0335525 A JP H0335525A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wafer
- resist
- sio2
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明はウェハの両面加工方法に関し、加工工程の簡略
化をはかったものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method for processing both sides of a wafer, and is intended to simplify the processing steps.
〈従来の技術〉
第２図（ａ）〜（ｅ）はウェハの両面加工方法の従来例
を示す概略工程図である。工程に従って説明する。<Prior Art> FIGS. 2(a) to 2(e) are schematic process diagrams showing a conventional method for processing both sides of a wafer. The process will be explained step by step.
（ｉ） ウェハ１の両面に５ｉＯ２１１ｆｉ２および
そのＳｉＯ２膜の上に５１３ＮａＨ３を形成する工程。(i) Step of forming 5iO211fi2 on both sides of the wafer 1 and 513NaH3 on the SiO2 film.
（ｉ１）前記ウェハ１の一方の面Ａにレジスト膜４を塗
布し、そのレジスト膜を所望の形状にパターニングして
５ｉ３Ｎ４１Ｂ！を露出させ、レジスト膜４をベーキン
グする工程。(i1) A resist film 4 is applied to one side A of the wafer 1, and the resist film is patterned into a desired shape, and 5i3N41B! A step of exposing the resist film 4 and baking the resist film 4.
（ｉｉｉ） ウェハｌの他方の面Ｂにレジスト［４を
塗布後ベーキングする工程。(iii) A step of baking after coating the resist [4] on the other side B of the wafer l.
（以上ａ図参照）
（（７）工程（ｉ１）で露出させたＳｔ、Ｎ４膜３をＲ
ＩＥ（リアクティブ・イオン・エツチング）により除去
してＳｉＯ２膜２を露出させた後３両面のレジスト膜４
を除去する工程、 （ｂ図参照）（Ｖ）（（
７）で露出させた５ｉＯ２１模２を含むウェハ１のＡ面
にレジスト膜４を塗布してベーキングを行う工程。(See figure a above) ((7) R the St, N4 film 3 exposed in step (i1)
After removing by IE (reactive ion etching) to expose the SiO2 film 2, the resist film 4 on both sides of 3 is removed.
(see figure b) (V) ((
A step of applying a resist film 4 to the A side of the wafer 1 including the 5iO21 pattern 2 exposed in step 7) and baking it.
Ｏ４） Ｂ面にレジスト膜４を塗布し１所望の形状に
パターニングしてＳｉ３Ｎ４膜３を露出させ、この面を
ベーキングする工程、 （以上０図参照）■ 工程
（７）で露出させた５ｉ３Ｎ４１摸３をＲＩＥにより除
去し、５ｉＯ２１摸２を露出させた後両面のレジスト膜
４を除去する工程、 （ｄ図参照）■ｌ Ｓｉ３
Ｎ４膜３をマスクとして両面に露出させたＳｉＯ２１模
を２をウェットエツチングにより除去する工程、
（ｅ図参照）〈発明が解決しようとす
る課題〉
しかしながら、上記従来の製造方法においては次のよう
な問題があった。O4) A step of applying a resist film 4 to the B side and patterning it into a desired shape to expose the Si3N4 film 3, and baking this surface (see Figure 0 above) ■ A replica of the 5i3N41 exposed in step (7) Step of removing resist film 4 on both sides after removing 3 by RIE and exposing 5iO21 sample 2 (see figure d) ■l Si3
a step of removing the SiO pattern exposed on both sides by wet etching using the N film 3 as a mask;
(See Figure e) <Problems to be Solved by the Invention> However, the above conventional manufacturing method has the following problems.
■ 」−程（ｌｌ） 、 （ｌｉｔ） 、 （Ｖ） 、
（Ｖ＞でレジスト膜を４回ベーキングするが、このベ
ーキングは１００〜１４０゛Ｃで３０分程度程度の加熱
が必要であり回数は少ない方が望ましい。■ ”-Cheng (ll), (lit), (V),
(V) The resist film is baked four times at 100 to 140° C. for about 30 minutes, and it is preferable to bake the resist film less frequently.
■ レジスト膜をウェハに塗布する際は表面に均一に付
着させる為に一面を真空チャックで吸着して回転させな
がら行うが、工程（ｉｉ）ではすでにパタニングしたＡ
面を吸着してＢ面の塗布を行うのでＡ面に形成したパタ
ーンが損傷する恐れがある。■ When applying a resist film to a wafer, one side is adsorbed with a vacuum chuck and rotated to ensure uniform adhesion to the surface.
Since the B side is coated by adsorbing the side, there is a risk that the pattern formed on the A side may be damaged.
本発明は上記従来技術の問題点にに鑑みて成されたもの
で、レジスト塗布／ベーキング工程を２回に減らすとと
もにパターン損傷の恐れのないウェハの両面加工方法を
提供する事を目的とする。The present invention has been made in view of the problems of the prior art described above, and it is an object of the present invention to provide a method for processing both sides of a wafer, which reduces the number of resist coating/baking steps to two and eliminates the risk of pattern damage.
く課題を解決するための手段〉
上記課題を解決するための本発明の構成は、シリコンウ
ェハの両面にＳｉＯ２ＭおよびそのＳｉＯ２膜の上にＳ
ｉ３Ｎ４膜を形成する工程と。Means for Solving the Problems> The structure of the present invention for solving the above problems is such that SiO2M is formed on both sides of a silicon wafer and S is formed on the SiO2 film.
and a step of forming an i3N4 film.
前記ウェハの一方の面ＢにＳｉＯ２ＣＶＤ膜を形成する
工程と。forming a SiO2CVD film on one side B of the wafer;
前記Ｂ面にレジスト膜を形成し、そのレジスト膜を所望
の形状にパターニングする工程と。forming a resist film on the B side and patterning the resist film into a desired shape;
前記レジスト膜をマスクとしてＳｉＯ２ＣＶＤ膜をエツ
チングにより除去する工程と。a step of removing the SiO2CVD film by etching using the resist film as a mask;
前３己ウエハの他方の面Ａにレジスト膜を形成し。Step 3: Form a resist film on the other side A of the wafer.
そのレジスト膜４ 工程と。The resist film 4 With the process.
前記Ａ面のレジスト膜およびＢ面のＳｉＯ２ＣＶＤ膜を
マスクとして両面のＳｉ３Ｎ４膜をエツチングにより除
去する工程と。A step of removing the Si3N4 film on both sides by etching using the resist film on the A side and the SiO2CVD film on the B side as masks.
前記Ａ面のレジスト膜を除去し、Ｓｉ３Ｎ４Ｍをマスク
としてＡ面の５ｉｚ２１ｅ！およびＢ面のＳｉＯ２膜、
Ｓ ｉ ０２ ＣＶＤＭ！、をエツチングにより除去
する工程。The resist film on the A-side was removed, and using Si3N4M as a mask, the A-side 5iz21e! and SiO2 film on the B side,
S i 02 CVDM! , is removed by etching.
を含む事を特徴とするものである。It is characterized by including.
〈実施例〉
以下１本発明のウェハの両面加工方法について図面を参
照して説明する。第１図（ａ）〜（ｄ）は本発明の一実
施例の構成を示す概略製作工程図である。<Example> Hereinafter, a method for processing both sides of a wafer according to the present invention will be described with reference to the drawings. FIGS. 1(a) to 1(d) are schematic manufacturing process diagrams showing the configuration of an embodiment of the present invention.
コニ程（ｉ）
シリコンウェハ１の両面にＳｉＯ２膜２およびそのＳ
ｉ ０２膜の−Ｌに５ｉ３Ｎ４１摸３を形成する。(i) SiO2 film 2 and its S
5i3N41 sample 3 is formed on -L of the i02 film.
工程（ｉ１）
ウェハ１の一方（７）面ＢニＳ ｉ Ｏ２ＣＶ Ｄ膜１
゜を３０００膜程度の厚さに形成する。Step (i1) One (7) side B of wafer 1 S i O2CV D film 1
The film is formed to have a thickness of about 3000°.
（この工程はＣＶＤ装置が立上がっていれば数分間で終
了する）
工程（２）
ＳｉＯ２ＣＶＤ膜１０が形成されたウェハ１のＢ面にレ
ジスト膜４！４を形成し、そのレジスト膜を所望の形状
にパターニングしてＳｌＯ□ＣＶＩ）膜ＩＯを露出させ
た後ベーキングを行う。(This step can be completed in a few minutes if the CVD equipment is started up.) Step (2) A resist film 4!4 is formed on the B side of the wafer 1 on which the SiO2 CVD film 10 has been formed, and the resist film is shaped into a desired shape. After patterning into a shape to expose the SlO□CVI) film IO, baking is performed.
（以上ａ図参照）
工程（（イ）
レジスト膜４をマスクとして工程（ＨＤで露出させたＳ
ｉ ０２ ＣＶＤＭ １０を弗酸（ＨＦ）のウェット
エツチングにより除去した後（この場合Ａ面に露出して
いるＳｉ：＋Ｎ４１摸はエツチングされない）レジスト
膜４除去する。 （ｂ図参照）工程〈切
ウェハ１の他方の面Ａにレジスト膜４を塗布し。(See figure a above) Process ((a) Process using the resist film 4 as a mask (S
After removing the i 02 CVDM 10 by wet etching with hydrofluoric acid (HF) (in this case, the Si:+N 41 exposed on the A side is not etched), the resist film 4 is removed. (See figure b) Process <A resist film 4 is applied to the other surface A of the cut wafer 1.
そのレジスト膜４所望の形状にパターニングして５１３
０４膜３を露出させた後ベーキングを行う。The resist film 4 is patterned into a desired shape 513
After exposing the 04 film 3, baking is performed.
工程（ｌＡ）
ウェハ１のＡ面のレジスト膜４をマスクとしてＡ面に露
出したＳｉ３ｏ４ｇ３をＲＩＥにより除去した後、８面
に露出した５ｉ３０４膜３を５ｌｏ２ＣＶＤ １０をマ
スクとしてＲＩＥにより除去する。
（ｃ図参照）工程（Ｖｌｉ）
ウェハ１のＡ面のレジスト膜４を除去し、Ａ面のＳｉＯ
２膜および８面のＳ ｉ ０２ ＣＶＤ膜、ＳｉＯｚＭ
をエツチングにより除去する。Step (lA) After removing Si3o4g3 exposed on the A side of the wafer 1 by RIE using the resist film 4 on the A side as a mask, the 5i304 film 3 exposed on the 8th side is removed by RIE using the 5lo2CVD 10 as a mask.
(See figure c) Step (Vli) The resist film 4 on the A side of the wafer 1 is removed, and the SiO
2-film and 8-sided S i 02 CVD film, SiOzM
is removed by etching.
上記実施例によればレジストの塗布およびベキング工程
が２回となる。According to the above embodiment, the resist coating and baking steps are performed twice.
〈発明の効果〉
以上、実施例とともに具体的に説明したように本発明の
両面加工方法によれば、ベーキング工程が２回で良いの
でその分工程が簡単になり加工時間を短縮する事が出来
る。また、従来の様にパタニングした面を吸着してレジ
ストを塗布する工程がないのでバターニングが損傷する
恐れがない。<Effects of the Invention> As specifically explained above in conjunction with the examples, according to the double-sided processing method of the present invention, only two baking steps are required, which simplifies the process and shortens the processing time. . Furthermore, since there is no step of sucking the patterned surface and applying resist as in the conventional method, there is no risk of damage to the patterning.
第１図は本発明のウェハの加工方法の一実施例の概略工
程を示す図、第２図は従来の加工方法の概略工程を示す
図である。
１・・・シリコンウェハ、２・・・ＳｉＯ２１１ｆｉ、
３・・・Ｓ’ ３０ａ ＪＢ％ ＋ ４・・・フォトレ
ジスト、１０・・・ＳｉＯ１寸「つ Ｎ
〜 「ｎマ
マ ”１ 〜
〜〜 勺 寸
、ＯFIG. 1 is a diagram showing a schematic process of an embodiment of the wafer processing method of the present invention, and FIG. 2 is a diagram showing a schematic process of a conventional processing method. 1... Silicon wafer, 2... SiO211fi,
3...S' 30a JB% + 4...Photoresist, 10...SiO1 inch
Claims (1)
ｉＯ＿２膜の上にＳｉ＿３Ｎ＿４膜を形成し、それらの
膜を所望のパターンにエッチングしてシリコンウェハを
露出させるシリコンウェハの両面加工方法において、下
記の工程を含んで加工された事を特徴とするシリコンウ
ェハの両面加工方法。 記 （ｉ）シリコンウェハ（以下、単にウェハという）の両
面にＳｉＯ＿２膜およびそのＳｉＯ＿２の上にＳｉ＿３
Ｎ＿４を形成する工程。 （ｉｉ）前記ウェハの一方の面ＢにＳｉＯ＿２ＣＶＤ膜
を形成する工程。 （ｉｉｉ）前記Ｂ面にフォトレジスト（以下、単にレジ
ストという）を形成し、そのレジスト膜を所望の形状に
パターニングしＳｉＯ＿２ＣＶＤ膜を露出させる工程。 （ｉｖ）前記レジスト膜をマスクとしてＳｉＯ＿２ＣＶ
Ｄ膜をエッチングにより除去する工程。 （ｖ）前記ウェハの他方の面Ａにレジスト膜を形成し、
そのレジスト膜を所望の形状にパターニングする工程。 （ｖｉ）前記Ａ面のレジスト膜およびＢ面のＳｉＯ＿２
ＣＶＤ膜をマスクとして両面のＳｉ＿３Ｎ＿４膜をエッ
チングにより除去する工程。 （Ｖｉｉ）前記Ａ面のレジストを除去し、Ｓｉ＿３Ｎ＿
４膜をマスクとしてＡ面のＳｉＯ＿２膜およびＢ面のＳ
ｉＯ＿２膜、ＳｉＯ＿２ＣＶＤ膜をエッチングにより除
去する工程。[Claims] A SiO_2 film is formed on both sides of a silicon wafer, and this S
A silicon wafer double-sided processing method in which a Si_3N_4 film is formed on an iO_2 film and the films are etched into a desired pattern to expose the silicon wafer, and the silicon wafer is processed by the following steps: A method for processing both sides of a wafer. Note (i) SiO_2 film on both sides of a silicon wafer (hereinafter simply referred to as wafer) and Si_3 film on the SiO_2.
Step of forming N_4. (ii) A step of forming a SiO_2CVD film on one side B of the wafer. (iii) A step of forming a photoresist (hereinafter simply referred to as resist) on the B side and patterning the resist film into a desired shape to expose the SiO_2CVD film. (iv) SiO_2CV using the resist film as a mask
Step of removing the D film by etching. (v) forming a resist film on the other side A of the wafer;
A process of patterning the resist film into a desired shape. (vi) The resist film on the A side and SiO_2 on the B side
A step of removing the Si_3N_4 film on both sides by etching using the CVD film as a mask. (Vii) Remove the resist on the A side and Si_3N_
4 film as a mask, SiO_2 film on the A side and S on the B side.
Step of removing the iO_2 film and SiO_2 CVD film by etching.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171511A JPH0335525A (en) | 1989-07-03 | 1989-07-03 | Method of processing both sides of silicon wafer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1171511A JPH0335525A (en) | 1989-07-03 | 1989-07-03 | Method of processing both sides of silicon wafer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0335525A true JPH0335525A (en) | 1991-02-15 |
Family
ID=15924475
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1171511A Pending JPH0335525A (en) | 1989-07-03 | 1989-07-03 | Method of processing both sides of silicon wafer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0335525A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2809532A1 (en) * | 2000-05-23 | 2001-11-30 | St Microelectronics Sa | Simplified method for the photoengraving of photosensitive material allowing simultaneous double face treatment of a semiconductor substrate |
| JP2008125370A (en) * | 2006-11-16 | 2008-06-05 | Water Land:Kk | Scooping tool |
-
1989
- 1989-07-03 JP JP1171511A patent/JPH0335525A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2809532A1 (en) * | 2000-05-23 | 2001-11-30 | St Microelectronics Sa | Simplified method for the photoengraving of photosensitive material allowing simultaneous double face treatment of a semiconductor substrate |
| JP2008125370A (en) * | 2006-11-16 | 2008-06-05 | Water Land:Kk | Scooping tool |
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