JPH0335530A - Bipolar semiconductor device and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a bipolar transistor that miniaturizes the operating region and brings out the base and collector electrodes to the surrounding area, and a method for manufacturing the same, the collector contact region is also provided within the same small window as the base and emitter regions. In order to miniaturize the area and contribute to high-speed operation, one window has a collector contact area provided at one end of the window side part, a base area that includes the center part and extends to the other end of the window side part, and a window side part. It has an active region consisting of a base contact region provided at the other end and an emitter region provided at the center, and each lead electrode leads out of the window from the collector contact region and the base contact region. It is characterized by being provided.

[Industrial Field of Application] The present invention relates to a bipolar semiconductor device and a method for manufacturing the same, and more particularly to a bipolar transistor in which the operating region is miniaturized and a base/collector electric fence is extended to the periphery, and a method for manufacturing the same.

Recently, with the demand for faster computers, IC, LS
Technological developments are progressing in the direction of increasing the speed of semiconductor devices such as I, and in bipolar semiconductor devices, it is desired to reduce parasitic capacitance by forming a fine operating region.

[Prior Art] Fig. 4 shows a structural cross-sectional view of a conventional base extraction electrode type bipolar semiconductor device, in which symbol 1 is a p-type silicon substrate, 2 is an n+ type buried region 3 is an n-type Collector region (epitaxially grown layer).

4 is a p-type base region, and 5 is an n-type emitter region.

6 is a base extraction electrode made of a doped polycrystalline silicon film, C is a collector electrode, and B is a base electrode.

E is an emitter electrode.

Such a semiconductor device has a structure that has been developed in recent years, and has a structure in which the base and emitter regions can be formed by self-alignment (self-alignment), and the element region can be miniaturized to operate at high speed.

[Problem B to be solved by the invention] However, even in the structure of the miniaturized semiconductor device shown in FIG. 4, the collector region is the same as that of a general semiconductor device, and the ratio of the collector region to the entire semiconductor device is As the size increases, the area of the entire device cannot be reduced very much, which poses a problem that impedes the speeding up of the device.

The present invention provides a semiconductor device and its manufacture which aims to reduce such problems, miniaturize the operating region by providing the collector contact region within the same small window as the base/emitter region, and operate at high speed. This paper proposes a method.

[Means for Solving the Problem] The problem is that, in one window, there is a collector contact area provided at one end of the window side part, a base area including the center part and extending to the other end of the window side part, and a collector contact area provided at one end of the window side part. Base contact 3 installed at the end! A bipolar semiconductor device comprising an operating region consisting of an i region and an emitter region provided in the central portion, and provided with lead electrodes extending from the collector contact region and the base contact region to the outside of the window. solved by.

The manufacturing method also includes a step of depositing a three-layer film consisting of an insulating film, a polycrystalline silicon film, and an insulating film on a collector region of one conductivity type, and opening a window in the three-layer film; masking one end of the part with an insulating film to form a base region of different conductivity types in the center part and the other end of the window side part; then, forming a base region of one conductivity type in each of the polycrystalline silicon films in the center of the three-layer film on both sides of the outside of the window; a step of doping an impurity and an impurity of a different conductivity type; then a step of removing an insulating film within the window and forming a polycrystalline silicon film at both ends of the window side portion to be connected to each polycrystalline silicon film on both sides of the window; Next, impurities of one conductivity type are diffused from the doped polycrystalline silicon film of one conductivity type through the polycrystalline silicon film at one end of the window side portion to form a collector contact region, and at the same time, impurities of one conductivity type are diffused from the doped polycrystalline silicon film of a different conductivity type through the polycrystalline silicon film at one end of the window side portion. A process of diffusing impurities of a different conductivity type through the polycrystalline silicon film at the edges to form a pace contact H1 region. Next, after forming an insulating film to cover the polycrystalline silicon films at both ends within the window, The method is characterized in that it includes a step of depositing a doped polycrystalline silicon film of one conductivity type and annealing to diffuse impurities from the doped polycrystalline silicon film of one conductivity type to define an emitter region of one conductivity type.

[Function] That is, since the present invention has a structure in which the collector contact region, base contact region, base region, and emitter region are provided in the same window by self-line, and the operating region is miniaturized, the parasitic capacitance is further reduced. It can be made faster.

[Example] Hereinafter, embodiments will be described in detail with reference to the drawings.

Figures 1 (al) and (b) show a bipolar semiconductor device according to the present invention;
1 is a perspective plan view, and figure (a) is a cross-sectional view taken along line AA in figure (b). In the figure, symbol 10 is a window, and 11 is a p-type silicon substrate.

■2 is an n° type buried region, 13 is an n type collector region (epitaxial growth layer), 14 is a p type base region, 15 is an n type emitter region, 16 is a p′′ base contact region, and 17 is a n′′ collector contact region.

18 is a base extraction electrode from the base contact area;
19 is a collector lead-out electrode from the collector contact region, C is a collector electrode, and B is a base electrode.

E is an emisota electrode. Note that the perspective plan view shown in FIG. 1(b) is a plan view in which the epitaxially grown WI (n-type collector region 13) is exposed.

Inside the window 10, there is a collector contact SJT area 17 provided on the left side of the window side part, a base area 14 that includes the central part of the window and reaches to the right side of the window side part, and a base contact area 16 provided on the right side of the window side part. A bulky ivy area 15 provided in the central portion of the window is formed, and these are mutually formed by self-line. And collector contact region 1
An extraction electrode 19 led out from the window 7 and an extraction electrode 18 led out from the base contact region 16 are provided. With such a structure, the operating areas can be formed extremely finely by mutually forming self-lines.
The collector region can also be made smaller, so parasitic capacitance can be reduced and operation can be made faster.

Next, Figures 2 (al to (rl) show step-by-step cross-sectional views of the manufacturing method according to the present invention, which will be explained step by step. Figures 3 (al) and (b) are plan views in the middle of the process. is shown in the figure, and will be referred to from time to time for explanation.

Refer to FIG. 2(a); an n-type collector layer 13 (epitaxially grown layer) is grown on a p-type silicon substrate 11 via an n-type buried region 12, and an S layer is grown on the n-type collector layer 13.
A three-layer film consisting of an i3Nm (silicon nitride) film 21, a non-doped polycrystalline silicon film 22, and a Si, N, film 23 is deposited. This three-layer film is deposited by CVD (chemical vapor deposition), but after depositing the non-doped polycrystalline silicon film 22 during the process, a resist film pattern 24 shown in FIG. 3 (al) is deposited. Then, the non-doped polycrystalline silicon film 22 is patterned, leaving the non-doped polycrystalline silicon film 22 in the same shape as the resist film pattern 24 and removing other parts.This resist film pattern 24 is the device area, and , Fig. 3 (10 in al is a window to be formed in the next step (several μm in width, tens of μm in length)
It is a rectangular window).

Refer to FIG. 2(b); Next, the above three-layer film is etched away by a photo process to open a window 10, and a cVDsioz film 25 (silicon oxide film formed by CVD method) is formed on the upper surface including the SONO window 10. to adhere to.

? , 2 figure (see 01; next item, so 0) CV DSiOz
1PJ25 is vertically anisotropically etched, and CVD SiO is etched only on the side edge inside the window 10 using the step at the edge.
The z film 25 is left.

Refer to FIG. 2(d); Next, the CVD5t02 film 25 on only the other side edge is removed using a photo process, and the CVD5iOz film 25 on the other side edge is left, and then the entire surface including the window 10 is removed using the CVD method. A BSG film 26 (boron silicate glass film) is deposited on the surface.

FIG. 2 (see el; Next, the BSG film 2 deposited on the top surface
6 is polished and removed, leaving the BSG film 26 only within the window 10, and further annealing is performed at a temperature of 800 to 900° C. to form the base region 14 (internal base region). At this time,
No base region is formed at one side edge within the window 10 covered with the CVD5iOz film 25.

Refer to FIG. 2(f); Next, a resist film pattern 27 is formed on the right half of the window including the other side edge of the window 10 and the St, N, film portion on the right side, and a resist film pattern 27 is formed on the right half of the window including the other side edge of the window 10, Phosphorus;n
type impurity> ions are implanted to transform the left non-doped polycrystalline silicon film 22 into an n-type conductive polycrystalline silicon film (
(becomes the collector lead-out electrode 19).

Refer to FIG. 2(g); Next, the resist film pattern 27 is removed, and a resist film pattern 28 is formed on the left half of the window including one side edge of the window 10 and the left 5i3Na film portion. B''(phosphorous; p-type impurity) ions are implanted from above to transform the non-doped polycrystalline silicon film 22 on the right side into a p-type thermoelectric polycrystalline silicon film (to become the base extraction electrode 18).

Refer to FIG. 2(h); then, after removing the resist film pattern 28, the CVD5iOz film 25 within the window 10 is removed. BSG
Etching and removing the membrane 26 with hydrofluoric acid solution (washout)
do.

See FIG. 2(1); Next, the Siz Na 1121, 23 is subjected to controlled etching by immersion in a boiled phosphoric acid solution to etch the exposed surface. Then, window 10
Inside the window, the polycrystalline silicon film 22 in the three-layer film is not etched, but is formed into a protruding shape at both ends of the window.

Refer to FIG. 2(J); Next, a non-doped polycrystalline silicon film 29 is deposited over the entire surface including the inside of the window 10. Referring to FIG. Then, the non-doped polycrystalline silicon film 29 and the polycrystalline silicon n'122 are connected.

Further, the non-doped polycrystalline silicon film 29 is vertically anisotropically etched to leave the non-doped polycrystalline silicon film 29 only at both ends within the window 10. Refer to FIG.

FIG. 2 (see 11; next, using a photo process, a resist film pattern 30 having a rectangular window pattern penetrating through the window end in the longitudinal direction of the window 10 is formed, and the non-doped polycrystalline silicon exposed within the window pattern is formed. The film 29 is removed by etching.This is to leave the non-doped polycrystalline silicon film 29 only at both ends of the window IO in the longitudinal direction and divide it into two.

FIG. 3(b) shows a plan view of the resist film pattern 30, and also shows the window IO.

FIG. 2 (see ml; next, the surface of the non-doped polycrystalline silicon film 29 remaining at the side edge inside the window IO is thermally oxidized,
Further, a CVD5iO2 film is deposited on the upper surface.

At that time, due to the heating in the thermal oxidation process, phosphorus is diffused from the collector lead electrode 19 through the polycrystalline silicon film 29 to form the collector contact region 17, and at the same time, phosphorus is diffused from the base lead electrode 18 through the polycrystalline silicon film 29. is diffused to form a base contact jJl region 16. Note that 31 indicates a 5iOt film consisting of a thermal oxide film and a CVD 5iO film.

Refer to FIG. 2(n): Further, the 5iOz film 31 is anisotropically etched vertically, so that the entire SiO□ film 31 is formed only on the sides within the window IO.

Refer to FIG. 2(0); Next, an n-type doped polycrystalline silicon film 32 containing phosphorus is deposited over the entire surface of the window 10 including the central portion. This is done by depositing a non-doped polycrystalline silicon film,
The n-type doped polycrystalline silicon film 32 may be formed by implanting n-type impurity ions.

See Figure 2 (p); then, by photoprocessing, n
The type doped polycrystalline silicon film 32 is patterned so that the n type doped polycrystalline silicon 1132 remains only inside the window 10 and on its upper surface.

FIG. 2 (see Ql; next, a window CW for connecting the collector electrode and the base electrode to the 5t2Na film 23, B
The emitter region 15 is defined by opening the W and further annealing.

FIG. 2 (see rl) Finally, a collector electrode C, a base electrode B, and a bottom electrode E made of aluminum are formed to complete the process.

The above is an overview of the method for manufacturing a bipolar semiconductor device according to the present invention, and the main point is that after opening a window by a photo process, the base region, collector contact region, base contact region, and emitter region are all formed without applying a photo process. It is formed using Selfa Line.

As mentioned above, since the manufacturing method according to the present invention can form the operating region within the same small window with a self-line,
It can be extremely miniaturized, and accordingly, the collector region can also be made smaller, reducing parasitic capacitance and increasing speed.

[Effects of the Invention] As is clear from the description of the embodiments above, the bipolar semiconductor device and the manufacturing method thereof according to the present invention have the following effects.
- The collector contact region, base region, base contact region, and emitter region can be formed within the small window using self-alignment lines, and these operating regions are extremely miniaturized, and the collector region is also made smaller, reducing parasitic capacitance. However, a significant effect can be obtained in improving the performance of the semiconductor device, such as increasing the speed of operation.

[Brief explanation of drawings]

1(a) and (bl are diagrams showing a bipolar semiconductor device according to the present invention, FIG. 2 (al to (r) are step-by-step sectional views of the manufacturing method according to the present invention, and FIG. 3 (al, b) is an intermediate plan view of the manufacturing method according to the present invention, and FIG. 4 is a cross-sectional view of the structure of a conventional base extraction electrode type bipolar semiconductor device. In the figure, lO is a window, 11 is a p-type silicon substrate, and 12 is an n-type buried layer, 13 is an n-type collector layer (epitaxial growth layer), and 14 is an n-type buried layer.
is a p-type base layer, 15 is an n°-type emitter layer, 16 is a p3-type base contact region, 17 is an n0-type collector contact region, 18 is a base extraction electrode, 19 is a collector extraction electrode, C is a collector electrode, and B is a base Electrodes, E is an emitter electrode, 21, 23 are 5i3Na films, 22, 29 are polycrystalline silicon films, 24, 27, 28, 30 are resist film patterns, 25 is a CVD SiO2 film, 26 is a BSG film, 31 is a 5in2 film, 32 indicates an n-type doped polycrystalline silicon film. /￥Ryoan 1;0・〃3Kindochihano Kosha Gug Watama No. 2
Figure (Uke no 32 Figure 2 (吃の4)
@afr#M Figure 2 (provisional ＾5)

Claims (2)

[Claims] (1) In one window, a collector contact area provided at one end of the window side part, a base area including the central part and reaching the other end of the window side part, a base contact area provided at the other end of the window side part, and the base area provided at the other end of the window side part; A bipolar semiconductor device comprising an operating region including an emitter region provided in the center, and lead electrodes extending from the collector contact region and the base contact region to the outside of the window. . (2) A step of depositing a three-layer film consisting of an insulating film, a polycrystalline silicon film, and an insulating film on the collector region of one conductivity type, and opening a window in the three-layer film, and then opening one end of the window side portion. Step of forming base regions of different conductivity types in the central part and the other end of the window side part by masking with an insulating film. Next, impurities of one conductivity type and different conductivity are added to the polycrystalline silicon film at the center of the three-layer film on both sides of the outside of the window. a step of doping type impurities, a step of removing the insulating film within the window, and forming a polycrystalline silicon film at both ends of the window side portion to be connected to each polycrystalline silicon film on both sides of the window; One conductivity type impurity is diffused from the doped polycrystalline silicon film through the polycrystalline silicon film at one end of the window side part to form a collector contact region, and at the same time, the impurity of one conductivity type is diffused from the doped polycrystalline silicon film of a different conductivity type to the polycrystalline silicon film at the other end of the window side part. A process of diffusing impurities of different conductivity type through the silicon film to form a base contact region. Next, after forming an insulating film covering the polycrystalline silicon film at both ends within the window, a doped impurity of one conductivity type is formed in the center of the window. A bipolar semiconductor device comprising the steps of depositing a polycrystalline silicon film and annealing to diffuse impurities from the doped polycrystalline silicon film to define an emitter region of one conductivity type. Production method.