JPH0336629A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the quantity of a hardware, to simplify control and structure and to improve speed for processing by providing a stack pointer equipped with the register of one bit to be inverted corresponding to a write/read signal for specifying two stacks. CONSTITUTION:A stack pointer 3 is equipped with a register 4 of one bit to be inverted according to the input of the read/write signal and an instruction signal output means 5 to specify the stack and to output a signal for instructing the read/write of the stack based on the read/write signal and the output of the register 4. When the read/write signal of the stack is inputted to an information processor 1, the means 5 specifies either a stack 2A or 2B according to the combination of the register and inputted signal and the signal to instruct the read/write of the stack is outputted. Then, the signal returns to the stack and address data are written or read.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to an information processing device that uses microinstructions for internal sequence control of a microprocessor, etc.
To provide an information processing device that reduces the amount of hardware when there are two stacks, has simple control and structure, and improves processing speed, regarding a microcontroller having a subroutine branching function of a microprogram used in an LSI. In an information processing device having two stacks and a stack pointer for specifying the stack, the stack pointer is a 1-bit register that is inverted according to a write signal or a read signal of the stack. and instruction signal output means for outputting a write instruction signal or a read instruction signal according to the write signal or read signal and the value of the register.

[Industrial application field]

The present invention relates to an information processing device that uses microinstructions for internal sequence control of a microprocessor, and in particular,
The present invention relates to a microcontroller having a subroutine branching function for microprograms used in t and st.

In a microcontroller, when branching to subroutine processing during execution of a certain routine processing, a register is used to store address data (hereinafter referred to as return address data) for returning to the original routine processing after the subroutine processing is completed. Is required. In such subroutine branch processing, if the branch has a hierarchical structure (nested structure), there are multiple registers in the stack structure (hereinafter referred to as stacks) to hold return address data, and in order to specify the stack, A stack pointer is provided.

In general, the stack pointer requires a one-to-one correspondence between the value indicated by the pointer and the stack, so the nested structure is
If it is a structure, the value of the stack pointer must indicate n+1.

[Conventional technology]

When there is a subroutine branch instruction with the stack pointer,
After adding (or subtracting) the pointer by 1, the microcontroller returns to the stack corresponding to the pointer and writes address data. Furthermore, when there is a return instruction, the pointer is subtracted (or added) by 1, and the microcontroller reads return address data from the stack corresponding to the pointer.

On the other hand, in VLSI and the like, there is a limit to the number of stacks due to hardware scale limitations, and the number of stacks is often two. Therefore, the case where there are two stacks will be described below.

FIG. 9 shows an explanatory diagram of how the stacks are used when there are two stacks. Hereinafter, each stack will be referred to as a first stack and a second stack, and it is assumed that the stack pointer is composed of a 2-bit counter register.

If the stack pointer value is 00, it indicates that the stack is not in use and the main routine is processing. If the stack pointer value is 01, the first stack is This indicates that subroutine processing (hereinafter referred to as the first subroutine processing) is being performed.The value of the stack pointer is "10".
'' indicates that the second stack is also being used, and subroutine processing (hereinafter referred to as second subroutine processing) is being performed in addition to the first subroutine processing.

[Problem to be solved by the invention]

In the conventional information processing device described above, when the stack pointer is configured with a counter register, a 2-bit counter register is required even if there are two stacks, which increases the amount of hardware required and complicates the control and structure. At the same time, there was a problem in that the processing speed decreased.

In view of the above problems, an object of the present invention is to provide an information processing device that reduces the amount of hardware when there are two stacks, has simple control and structure, and improves processing speed.

[Means to solve the problem]

Focusing only on the case where there are two nested structures, that is, when there are two stacks, if one of the two stacks is not selected, it is univocally determined that the other stack is selected.

As a result, the value of the stack pointer only needs to indicate two values.

Therefore, as shown in the principle explanatory diagram of FIG.
In an information processing device 1 comprising two stacks 2A and 2B and a stack pointer 3 for specifying the stack, the stack pointer 3 is a 1-bit register that is inverted according to a write signal or a read signal of the stack. 4, and an instruction signal output means 5 for outputting a write instruction signal or a read instruction signal based on the write signal or the read signal and the value of the register 4.

[Effect]

Since the present invention is configured as described above, the instruction signal output means 5 can easily specify the stack by a combination of the write signal or read signal of the stack and the value of the 1-bit register. It is possible to output a write instruction signal or a read instruction signal for.

〔Example〕

Embodiments of the present invention will be described in detail with reference to FIGS. 1 to 8.

As shown in FIG.
The stack pointer 3 includes two stacks, A and a second stack 2B, and a stack pointer 3 that specifies the stack and instructs reading or writing of the stack.

The stack pointer 3 identifies a stack based on a 1-bit register 4 that is inverted by the input of a read signal or a write signal, the read signal or write signal, and the output signal of the register 4, and instructs reading or writing of the stack. and an instruction signal output means 5 for outputting an instruction signal.

When a stack read signal or a write signal is manually input to the information processing device 1, the instruction signal output means 5 identifies the stack by a combination of the register and the input signal, and outputs an instruction to read or write the stack. Outputs signal 6. As a result, return address data is written to or read from the stack. FIG. 2 shows a block diagram when the present invention is applied to a drawing processing device.

The drawing processing device 7 is a host C that controls the entire system.
A PU 8, a system memory 9 that stores control data for the entire system, a drawing processor IO that controls drawing processing, a graphic memory 11 that stores graphic data, and a display device that performs display based on the graphic data. 12, a host bus 13 for exchanging system control data, and a graphic bus 14 for exchanging graphic data.

The drawing processing processor 10 includes a host bus interface section 15 that performs an interface operation for exchanging data with the host bus 13, a drawing operation section 16 that performs operations on graphic data, etc., and an interface operation for exchanging data with the graphic bus 14. A graphic bus interface unit 17 is provided.

As shown in FIG. 3, the drawing calculation unit 16 includes a microcontroller 40 that controls the entire drawing calculation unit 16 by control signals, a calculation lid group such as an adder 41, a multiplier 42, a shifter 43, and a workpiece. It is configured to include a register 44 and an internal bus 45 for exchanging data internally.

Here, the operation of the drawing processing device 7 will be explained.

The host CPU 8 outputs drawing commands and parameters to the drawing calculation section 16 via the host bus 13 and the host bus interface section 15 based on data etc. in the system memory 9. The drawing calculation unit 16 analyzes the command, generates a drawing address for a circle, etc. based on the parameters, and outputs it to the graphic memory 1 via the graphic path interface unit 17 and the graphic bus 14. Furthermore, the display device 12 performs display based on the data in the graphic memory 11.

As shown in FIG. 4, the microcontroller 40 of the drawing calculation unit 16 includes a command decoder 18 that generates the start address of a microinstruction from a command from the host CPU 8 or the like;
A selector 19 that selects a read address of a microinstruction to be processed next based on an output signal of a branch control circuit 20 (described later), a branch control circuit 20 that performs branch control based on a code of a microinstruction register (described later), and a selector 1
an address register 21 that stores address data selected by 9; and a micro ROM that stores microinstructions corresponding to the address data in the address register 21.
22, a microinstruction register 23 for storing microinstructions read from the microROM 22, an incrementer 24 for incrementing addresses, and a stack circuit 25 having a stack pointer and stacking return addresses.

In the microcontroller 40, the command decoder 18 analyzes the command given from the host CPU 8, etc.
A start address of a microinstruction is generated and output to the selector 19. The selector 19 selects the read address of the next microinstruction from the output of the command decoder 18, the output of the incrementer 24, the output of the stack circuit 25, or the branch address of the microinstruction register 23 and the output of the branch control circuit 20, Output to address register 21. At this time, the incrementer 24 adds 1 to the value of the address register and outputs the result. The micro ROM 22 reads a micro instruction based on the output of the address register 21 and outputs it to the micro instruction register 23. The data stored in the microinstruction register 23 is output as a control signal for each arithmetic unit.

On the other hand, when a subroutine branch instruction is executed by a microinstruction, the stack circuit 25 takes in the output of the incrementer 24 as a return address.

Furthermore, when a return instruction is executed as a microinstruction, the stack circuit 25 outputs a return address to the selector 19.

FIG. 5 shows a block diagram of the stack pointer in the stack circuit 25.

When a write signal or a read signal is input into the stack pointer 26 , the OR circuit 27 takes the logical sum of the write signal and the read signal, and outputs the result to the delay circuit 28 . The delay circuit 28 outputs the output signal of the OR circuit 27 to the T flip-flop circuit 29 after the stack write process or read process is completed. The T flip-flop circuit 29 inverts the output every time the output signal of the delay circuit 28 is output, and connects one input terminal of the first AND circuit 30, one input terminal of the second AND circuit 31, and the input terminal of the inverter 32. Output the output signal to. The output signal of the inverter 32 is the third AND circuit 3
3 and one input terminal of the fourth AND circuit 34. Furthermore, a write signal is input to the other input terminal of the second LAND circuit 30 and the other input terminal of the third AND circuit 33, and the other input terminal of the second AND circuit 31 and the other input terminal of the fourth AND circuit 34 are input. A read signal is input. In this case, the first to
The fourth AND circuit outputs a second stack write instruction signal 35, a first stack read instruction signal 36, a first stack write instruction signal 37, and a second stack read instruction signal 38, respectively.

FIG. 6 shows an explanatory diagram of the operating state of the drawing calculation section.

For example, when the output of the T flip-flop circuit 29 is "1" and the write signal becomes "1", the second stack 2B
Address data will be written to.

FIG. 7 shows an explanatory diagram of the processing state of the drawing calculation section.

Here, the number before the colon (:) indicates the output of the T flip-flop circuit 29 after processing.

For example, when a write signal is input in the initial state, address data is written to the first stack 2A, and the output of the T flip-flop circuit 29 becomes 1". Next, in this state, a further write signal is input. In the case of manual operation, the process proceeds counterclockwise, address data is written to the second stack 2B, and the output of the T flip-flop circuit 29 becomes "0".

Further, when a read signal is input, the process proceeds clockwise, the address data of the two people in the first stack are read out, and the output of the T flip-flop circuit 29 becomes 'O'.

Next, an example of the operation will be described with reference to the processing timing chart of the drawing calculation unit shown in FIG.

Here, in the initial state, that is, the start state of the main routine processing, the output of the T flip-flop circuit 29 is "0".
A case will be described in which, after performing the second subroutine process in the first subroutine process, the process returns to the main routine process, assuming that the write signal and the read signal are not input.

First, when a subroutine branch instruction is executed in main routine processing, the microcontroller sends a write signal to “1”.
”, the output of the OR circuit 27 becomes “1”. On the other hand, T
Since the output of the flip-flop circuit 29 is "0", the output of the input circuit 32 is "1", and the inputs of the third AND circuit 33 are both "1", and the output of the third AND circuit 32 is "1".
The output of 3 becomes “■”. That is, since the first star/socket write signal is output, the return address is written to the first star/socket 2A, and the process is shifted to the first subroutine.

After returning to the first stack 2A and finishing writing the address, the output of the delay circuit 28 becomes "■", and as a result, the output of the T flip-flop circuit 29 is inverted and becomes "1". Furthermore, along with this, the output of Inno Kui becomes '0'.

Next, when the subroutine branch instruction is executed in the first subroutine, the 74 microcontroller sets the write signal to “1”.
”, the output of the OR circuit 27 becomes “1”. On the other hand, T
Since the output of the flip-flop circuit 29 is "1", the output of the inverter 32 is "0", the inputs of the first AND circuit 30 are both "1", and the output of the first AND circuit 30 is "1". That is, since the second stack write instruction signal 35 is output, the return address is written to the second stack 2B, and the process is shifted to the second subroutine.

After returning to the second stack 2B and writing the address, the output of the delay circuit 28 becomes "■", and the output of the T flip-flop circuit 29 is thereby inverted and becomes "O". Furthermore, along with this, the output of the inverter becomes "■".

Thereafter, when the processing of the second subroutine is completed and a return instruction is executed in the second subroutine, the microcontroller sets the read signal to "1", and the output of the OR circuit 27 becomes "1".
1". On the other hand, the output of the T flip-flop circuit becomes "
0", the output of the inverter 32 becomes "1n,
The inputs of the fourth AND circuit 34 are all "■", and the output of the fourth AND circuit 34 is "1".

That is, since the second stack read instruction signal 38 is output, the return address is read from the second stack 2B.
The process will be moved to the first subroutine.

After the readout of the return address from the second stack 2B is completed, the output of the delay circuit 28 becomes 1'', and as a result, the output of the T flip-flop circuit 29 is inverted and becomes 1''.

After that, the processing of the first subroutine ends, and the first
When the return command is executed in the subroutine, the microcontroller sets the read signal to "1" and outputs the OR circuit 27.
The output of will be 11. On the other hand, T flip-flop circuit 2
Since the output of inverter 9 is 0'', the output of inverter 32 is 1''.
The inputs of the second AND circuit 31 are both "
1", and the output of the second AND circuit 31 becomes "1'. That is, since the first stack read instruction signal 36 is output, the return address is read from the first stack readout 2A, and the processing is shifted to the main routine processing.

After reading the return address from the first stack 2A, the output of the delay circuit 28 becomes "1", and the output of the T flip-flop circuit 29 is thereby inverted and becomes '1'. The output of <- data becomes 0''.

As described above, main routine processing, first subroutine processing, second subroutine processing, first subroutine processing,
Processing will be performed in the order of main routine processing.

〔Effect of the invention〕

Since the present invention is configured as described above, it is possible to specify two stacks using only a 1-bit register, which reduces the amount of hardware, simplifies control and structure, and improves processing speed. It has the effect of being able to do it.

[Brief Explanation of the Drawings] Figure 2 is a diagram explaining the principle of the present invention, Figure 2 is a block diagram of a drawing processing device according to the present invention, Figure 3 is a block diagram of a drawing calculation unit according to the present invention, and Figure 4 is a block diagram of a drawing processing unit according to the present invention. Figure 5 is a block diagram of the microcontroller, Figure 5 is a block diagram of the stack pointer in the present invention, Figure 6 is an explanatory diagram of the operating state of the drawing calculation unit in the invention, and Figure 7 is the processing of the drawing calculation unit in the invention. FIG. 8 is a processing timing chart of the drawing calculation unit according to the present invention, and FIG. 9 is an explanatory diagram of the conventional stack usage state. 1... Information processing device 2A... First stack 2B... Second stack 3... Stack pointer 4... Register 5... Instruction signal output means 6... Instruction signal 7... Drawing processing device 8...Host CPU 9...System memory 10...Drawing processing processor 11...Graphic memory 12...Display device 13...Host bus 14...Graphic bus 15... Host bus interface unit 16...Drawing 71-stroke calculation unit 17...Graphic bus interface unit 18.
...Command decoder 19...Selector 20...Branch control circuit 21...Address register 22...Micro ROM 23...Micro instruction register 24...Incrementer 25...Stack circuit 26...・Stack pointer 27...OR circuit 28...Delay circuit 29...T flip-flop circuit 30...First AND circuit 31...Second AND circuit 32...Inverter 33...Third AND circuit 34... ...First AND circuit 35...Second stack write instruction signal 36...First stack read instruction signal 37...First stack write instruction signal 38...Second stack read instruction signal 40...・Micro control unit 41... Adder 42... Multiplier 43... Thick 44... Register 45... Internal bus

Claims (1)

[Scope of Claims] An information processing device (1) comprising two stacks (2A, 2B) and a stack pointer (3) that specifies the stack, wherein the stack pointer (3) specifies the stack (2A,
It has a 1-bit register (4) that is inverted according to the write signal or read signal of 2B), and the write instruction signal or read instruction signal ( 6). An information processing apparatus comprising: an instruction signal output means (5) for outputting the instruction signal output means (5).