JPH0337075Y2 - - Google Patents
Info
- Publication number
- JPH0337075Y2 JPH0337075Y2 JP1989128499U JP12849989U JPH0337075Y2 JP H0337075 Y2 JPH0337075 Y2 JP H0337075Y2 JP 1989128499 U JP1989128499 U JP 1989128499U JP 12849989 U JP12849989 U JP 12849989U JP H0337075 Y2 JPH0337075 Y2 JP H0337075Y2
- Authority
- JP
- Japan
- Prior art keywords
- switch
- input terminal
- sampling
- switches
- operational amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Landscapes
- Measurement Of Resistance Or Impedance (AREA)
Description
【考案の詳細な説明】
本考案は、インピーダンス測定器に使用するサ
ンプリング積分回路に関し、特に、オフセツト電
圧補償回路を具備しサンプリングパルスの影響を
軽減したサンプリング積分回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sampling and integration circuit used in an impedance measuring instrument, and more particularly to a sampling and integration circuit that is equipped with an offset voltage compensation circuit to reduce the influence of sampling pulses.
従来、サンプリング積分回路を使用したインピ
ーダンス測定器（特願昭56−173854号参照）にお
いては、サンプリングパルスが発生するノイズの
影響によつてオフセツト電圧が生じ、測定誤差を
生じるという点があつた。 Conventionally, impedance measuring instruments using sampling and integrating circuits (see Japanese Patent Application No. 173,854/1982) have had the problem that offset voltages are generated due to the influence of noise generated by sampling pulses, resulting in measurement errors.
本考案は上記欠点に鑑みなされたもので、測定
系のオフセツト電圧を、サンプリングパルスによ
るノイズの影響をも含めて補償することにより、
誤差の生じないサンプリング積分回路を提供する
ことを目的とする。 The present invention was developed in view of the above drawbacks, and by compensating the offset voltage of the measurement system, including the influence of noise caused by sampling pulses,
The object of the present invention is to provide a sampling integration circuit that does not cause errors.
以下、本考案の一実施例を用いて詳説する。 Hereinafter, the present invention will be explained in detail using one embodiment.
第１図は本考案のサンプリング積分回路のブロ
ツク図である。第１図において、増幅器１の入力
端子と接地電位間にはスイツチSW1が設けられて
いる。増幅器１の出力端子は他の増幅器等（図示
せず）、位相検波器２、FET等の半導体によつて
構成されたスイツチSW2および抵抗R4を介して
演算増幅器３の反転入力端子に接続されている。
又、位相検波器２には発振回路（図示せず）から
被測定信号Vsと同相若しくは90゜移相した基準信
号Vrが入力される。演算増幅器３は抵抗R4、反
転入力端子および出力端子間に接続されたコンデ
ンサC2と共に積分器を構成している。コンデン
サC2の両端にはスイツチSW4が接続されている。
演算増幅器３の出力端子は抵抗R1を介して演算
増幅器４の反転入力端子に接続されている。演算
増幅器４の非反転入力端子は接地されている。演
算増幅器４は抵抗R1，R2と共に反転増幅器を構
成している。演算増幅器４の出力端子は抵抗R3、
スイツチSW3を介して演算増幅器３の非反転入力
端子に接続されている。演算増幅器３の非反転入
力端子はコンデンサC1を介して接道されている。
コンデンサC1は抵抗R3と共に平滑回路を構成し
ている。又、各スイツチSW1，SW2，SW3，SW4
は制御回路５によつて開閉制御される。 FIG. 1 is a block diagram of a sampling and integrating circuit according to the present invention. In FIG. 1, a switch SW 1 is provided between the input terminal of an amplifier 1 and ground potential. The output terminal of the amplifier 1 is connected to the inverting input terminal of the operational amplifier 3 via another amplifier (not shown), a phase detector 2, a switch SW 2 composed of a semiconductor such as an FET, and a resistor R 4 . has been done.
Further, a reference signal Vr which is in phase with the signal under test Vs or whose phase is shifted by 90 degrees is inputted to the phase detector 2 from an oscillation circuit (not shown). The operational amplifier 3 forms an integrator together with a resistor R 4 and a capacitor C 2 connected between the inverting input terminal and the output terminal. A switch SW4 is connected to both ends of the capacitor C2 .
The output terminal of the operational amplifier 3 is connected to the inverting input terminal of the operational amplifier 4 via a resistor R1 . A non-inverting input terminal of operational amplifier 4 is grounded. The operational amplifier 4 constitutes an inverting amplifier together with resistors R 1 and R 2 . The output terminal of the operational amplifier 4 is a resistor R 3 ,
It is connected to the non-inverting input terminal of the operational amplifier 3 via the switch SW3. The non-inverting input terminal of operational amplifier 3 is connected via capacitor C1 .
Capacitor C 1 and resistor R 3 constitute a smoothing circuit. Also, each switch SW 1 , SW 2 , SW 3 , SW 4
The opening/closing is controlled by the control circuit 5.
次に本考案のサンプリング積分回路の動作を説
明する。 Next, the operation of the sampling integration circuit of the present invention will be explained.
第２図は第１図に示すサンプリング積分回路の
タイミング図である。第１図および第２図におい
て、初期状態としてスイツチSW1，SW2，SW3は
開状態、スイツチSW4は閉状態にある。時刻t0に
おいて、オフセツト電圧補償が開始される。即
ち、制御回路５によつて、スイツチSW1，SW3は
閉、SW4は開にされる。スイツチSW2は閉時間
τ1、開時間τ2の間隔で開閉制御される。スイツチ
SW2の開閉周期は可変である。前記状態では、被
測定信号Viは増幅器１に入力されない。コンデ
ンサC1へは、増幅器１および演算増幅器３等の
オフセツト電圧、スイツチSW2の開閉によつて生
じるノイズによるオフセツト電圧が抵抗R3、ス
イツチSW3を介して充電される。コンデンサC1
は演算増幅器３等のオフセツト電圧およびスイツ
チSW2の開閉によつて生じるパルスノイズによつ
て充電され、その両端電圧は徐々に上昇し、遂に
一定電圧となる。出力電圧V0も同時に一定とな
る。この電圧は増幅器１、演算増幅器３等のオフ
セツト電圧およびスイツチSW2開閉に起因するオ
フセツト電圧等を補償する。その後、時刻t1にお
いてスイツチSW1，SW3制御回路５によつて開状
態にされ、被測定信号Viのサンプリング積分が
開始される。被測定信号Viは増幅器１およじ他
の増幅器等（図示せず）を介して、被測定信号
Vsとして位相検波器２に入力される。今、信号
Vsと同位相の基準信号Vrを位相検波器２に供給
すると、位相検波器２の出力端子には正の信号Ｖ
が得られる。スイツチSW2が閉状態のとき信号Ｖ
は演算増幅器３、コンデンサC2から成る積分回
路によつて積分された後、演算増幅器４を介して
出力電圧V0として出力される。スイツチSW2が
開状態の時、出力電圧V0は前の電圧に保持され
る。スイツチSW2の開閉によつて前記動作がくり
返され、その結果、入力信号Viを積分した出力
電圧V0が得られる。 FIG. 2 is a timing diagram of the sampling and integration circuit shown in FIG. 1. In FIGS. 1 and 2, the switches SW 1 , SW 2 , and SW 3 are in the open state and the switch SW 4 is in the closed state in the initial state. At time t0 , offset voltage compensation is started. That is, the control circuit 5 closes the switches SW 1 and SW 3 and opens the switches SW 4 . The switch SW 2 is controlled to open and close at intervals of a closing time τ 1 and an opening time τ 2 . switch
The opening/closing cycle of SW 2 is variable. In the above state, the signal under test Vi is not input to the amplifier 1. The capacitor C1 is charged with the offset voltage of the amplifier 1, the operational amplifier 3, etc., and the offset voltage due to noise caused by the opening and closing of the switch SW2 via the resistor R3 and the switch SW3 . Capacitor C 1
is charged by the offset voltage of the operational amplifier 3 etc. and the pulse noise generated by the opening and closing of the switch SW 2 , and the voltage across it gradually rises and finally reaches a constant voltage. The output voltage V 0 also becomes constant at the same time. This voltage compensates for offset voltages of the amplifier 1, operational amplifier 3, etc., and offset voltages caused by opening / closing of the switch SW2. Thereafter, at time t1 , the switches SW1 and SW3 are opened by the control circuit 5, and sampling and integration of the signal under test Vi is started. The signal under test Vi is converted to the signal under test via amplifier 1 and other amplifiers (not shown).
It is input to the phase detector 2 as Vs. Now the signal
When a reference signal Vr having the same phase as Vs is supplied to the phase detector 2, the output terminal of the phase detector 2 receives a positive signal V.
is obtained. Signal V when switch SW 2 is closed
is integrated by an integrating circuit consisting of an operational amplifier 3 and a capacitor C2 , and then outputted as an output voltage V0 via an operational amplifier 4. When switch SW 2 is open, the output voltage V 0 is kept at the previous voltage. The above operation is repeated by opening and closing the switch SW2 , and as a result, an output voltage V0 obtained by integrating the input signal Vi is obtained.
本考案の目的に、前記のように、サンプリング
パルスによるノイズが積分値に与える誤差を軽減
することにがる。また、この目的を達成するため
の動作時間が短いことは常に好ましい。 As mentioned above, an object of the present invention is to reduce errors caused by noise caused by sampling pulses on integral values. Also, a short operating time to achieve this objective is always preferred.
しかし、本考案の上述の実施例ではオフセツト
電圧補償期間と入力の積分期間でのサンプリング
パルス数が等しいことも当然望ましい。 However, in the above-described embodiment of the invention, it is also desirable that the number of sampling pulses in the offset voltage compensation period and the input integration period be equal.
以上述べた如く本考案によれば、オフセツト電
圧補償時、スイツチSW2は開閉動作を行なつてい
るので、サンプリング積分時、スイツチSW2の開
閉によるノイズの影響を除去でき、極めて誤差の
少ないサンプリング積分回路を構成できる。ま
た、オフセツト補償期間に積分器はリセツトされ
ないので、補償速度が上る。 As described above, according to the present invention, switch SW 2 opens and closes during offset voltage compensation, so during sampling and integration, the influence of noise due to the opening and closing of switch SW 2 can be removed, resulting in sampling with extremely small errors. Integrating circuits can be constructed. Also, since the integrator is not reset during the offset compensation period, the compensation speed is increased.
第１図は本考案のサンプリング積分回路のブロ
ツク図。第２図は本考案のサンプリング積分回路
のタイミング図。
１：増幅器、２：位相検波器、３，４：演算増
幅器、５：制御回路、SW1〜SW4：スイツチ。
FIG. 1 is a block diagram of the sampling integration circuit of the present invention. FIG. 2 is a timing diagram of the sampling integration circuit of the present invention. 1: Amplifier, 2: Phase detector, 3, 4: Operational amplifier, 5: Control circuit, SW 1 to SW 4 : Switch.
Claims (1)
ツチと、前記伝送路と積分手段の第１入力端子と
の間に接続された第２スイツチと、前記積分手段
の出力部と前記積分手段の第２入力端子との間に
設けられた第３スイツチと、前記積分手段の第２
入力端子と接地間に設けられたコンデンサと、前
記第１、第２、第３スイツチを制御する制御回路
とから成り、前記制御回路は前記第１、第３スイ
ツチを閉じてオフセツト補償するための第１モー
ドおよび前記第１、第３スイツチを開いて前記被
測定信号のサンプリング積分をおこなうための第
２モードを有し、前記第１、第２モードのいずれ
のモードにおいても前記積分手段をリセツトする
ことなくそれぞれ同じ回数づつ前記第２スイツチ
をくり返し開閉してサンプリングすることを特徴
とするサンプリング積分回路。 a first switch for grounding the electrical transmission line of the signal to be measured; a second switch connected between the transmission line and the first input terminal of the integrating means; a third switch provided between the second input terminal and the second input terminal of the integrating means;
It consists of a capacitor provided between the input terminal and ground, and a control circuit for controlling the first, second, and third switches, and the control circuit is configured to close the first and third switches to compensate for offset. The device has a first mode and a second mode for performing sampling and integration of the signal under test by opening the first and third switches, and resets the integrating means in either the first or second mode. 2. A sampling and integration circuit characterized in that the second switch is repeatedly opened and closed the same number of times to sample each time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128499U JPH0337075Y2 (en) | 1989-11-02 | 1989-11-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989128499U JPH0337075Y2 (en) | 1989-11-02 | 1989-11-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0267451U JPH0267451U (en) | 1990-05-22 |
| JPH0337075Y2 true JPH0337075Y2 (en) | 1991-08-06 |
Family
ID=31381894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989128499U Expired JPH0337075Y2 (en) | 1989-11-02 | 1989-11-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337075Y2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5595180A (en) * | 1979-01-10 | 1980-07-19 | Toshiba Corp | Error correcting unit of integrator |
| US4365204A (en) * | 1980-09-08 | 1982-12-21 | American Microsystems, Inc. | Offset compensation for switched capacitor integrators |
-
1989
- 1989-11-02 JP JP1989128499U patent/JPH0337075Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0267451U (en) | 1990-05-22 |
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