JPH0337207B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a sequence control device, particularly to each peripheral device (hereinafter referred to as a device) constituting a computer system when turning on and turning off the power of a computer system. The present invention relates to a sequence control device for controlling the order in which power is turned on or turned off.

[Prior Art] In general, in a computer system, when power is turned on to all the devices that make up the system at the same time, an excessive inrush current is generated, which has a negative effect on the power supply side. In addition, in order to ensure that the system starts up stably and disconnects without malfunction, a sequence control device is installed in the system, and the sequence control device turns on and off the power to each device in the system. I try to do that.

Even if the power of such a sequential control device itself is turned off due to an accident, etc., in order to have as little impact on the system in operation as possible, it is necessary to prevent the power of the sequential control device itself from being turned off. must be controlled as follows.

That is, it is necessary to maintain the power on/off state of each device in the system before the sequential control device is powered off even when the sequential control device itself is powered off.

Conventionally, in order to perform this kind of control, as will be explained in detail later, the break contact of the relay provided in the sequential control device (breaks (off) when coil current flows, and mechanically closes (turns off) when coil current disappears). A current loop is formed to flow a self-holding current that keeps the relay, which is a switch that turns on/off the power on the device side, in the on state. Even if the power is turned off, devices that are turned on will remain powered on.

[Problem that the invention seeks to solve]

However, with this method, as described later,
At least two control relays are required per device, thus requiring twice as many relays as there are devices in the system.

In general, relays are larger in size and more expensive than ICs or LSIs, so as the number of devices in a system increases, the advantages of relays in terms of mounting space and price become more noticeable. begins to appear.

On the other hand, even if you try to realize this kind of relay function using logic gates, the relay will not be able to function without power supply.
While logic gates have the function of mechanically maintaining a specific connection state when the power is turned off, logic gates lose their function when the power is turned off. It is not easy to substitute such a holding action.

The purpose of the present invention is to solve such problems and to maintain the power on/off state for each device even when the sequential control device itself is powered off.
An object of the present invention is to provide a sequence control device that does not use relays.

[Means for solving problems]

The device of the present invention is a sequence control device for controlling the order of power on/off of a plurality of devices, each of which has a relay for turning on/off its own power, via the relay. A self-holding current for self-maintaining the make state of each of the relays is connected in series to a control power source for a device including the relay, and a make-type contact corresponding to the coil of the relay, and a make-type contact corresponding to the coil; A diode for rectifying and combining the self-holding current of each device and the output of a power-on reset circuit included in the sequential control device control the conduction on and off of the diode, so that the rectified and combined self-holding current can be conducted. did
This is achieved through an SCR circuit composed of a PNP type transistor and an NPN type transistor.

〔Example〕

Next, the present invention will be explained with reference to the drawings. For ease of understanding, a conventional example will be explained first.

FIG. 5 is a block diagram for explaining a conventional example. This conventional example is a system including a sequence control device 1' and m devices 2'-1 to 2'-m.

For example, device 2'-1 has its own control power supply V _d ' ₁ , and uses this control power supply V _d ' ₁ to turn on (turn on) the power supply to device 2'-1.
and relay for executing OFF (disconnection)
It has RL′ ₁ and r _l ′ ₁ . Relay contact r _l ′ ₁ is a make type contact, and when a current (above a certain value) flows through relay coil RL ′ _1, it makes (ON) the corresponding relay contact r _l ′ ₁ and turns on relay coil RL ′ ₁ . When the current (above a certain value) stops flowing, the corresponding contact r _l ′ ₁ is mechanically broken (turned OFF). and for the power supply (not shown) of device 2'-1.
ON/OFF is performed by another contact (not shown) whose make/break is controlled in exactly the same way as contact r _l ' ₁ by the current flowing through relay coil RL' ₁ .
For example, when current flows through relay coil RL′ ₁ , the contact
r _l ′ ₁ is turned on, and at the same time, device 2 ′-1 is turned on to the power supply by another power ON/OFF relay contact that operates in the same way as r _l ′ ₁ . Also, when current no longer flows through coil RL' ₁ , contact r _l ' ₁ is mechanically turned OFF, and at the same time, this power ON/OFF relay contact, which operates in the same way as r _l ' ₁ , disconnects device 2-1 from the power supply. It will be turned off.

All devices other than device 2'-1 have exactly the same configuration as above.

On the other hand, the sequence control device 1' is provided with two relays for controlling device power on/off, corresponding to each of the devices 2'-1 to 2'-m.

For example, for device 2'-1, a make type relay that starts powering on device 2'-1
ON ₁ , on ₁ and break-type relays OFF ₁ , off ₁ are provided for starting power-off of the device 2'-1. And each of these relay coils ON ₁ ,
One end of OFF ₁ is connected to the power supply voltage _V'cc of the sequential control device 1', and the other end is connected to the outputs of NAND gates 14'-1 and 15'-1, respectively. Each of these NAND gates 14'-1 and 15'-1 similarly receives the power supply V' _cc of the sequence control device 1'.
is driven by.

The configurations of these relays and NAND gates are exactly the same for other devices.

Furthermore, a power-on reset circuit (POR) 12' is provided in the sequence control device 1'.
This power-on reset circuit (POR) 12' is
When the power supply _V'cc is higher than a certain threshold voltage _E'1 , the output _V'p of the circuit (POR) 12' assumes a high logic level (hereinafter referred to as H level), and
When it is lower than _E'1 , _V'p assumes a low logic level (hereinafter referred to as L level).

The output V′ _p of this power-on reset circuit 12′
are each of the above-mentioned NAND gates 14'-1 to 14'-m
and 15'-1 to 15'-m, respectively.

These NAND gates are connected to the power supply V′ _cc as mentioned above.
Since V′ _cc is driven by a specific voltage E′ ₂
If it drops below 1, it loses its function as a logic element, but power-on reset circuit (POR)1
2' threshold E' ₁ is chosen so that E' ₁ >E' ₂ , so that V' _cc
When a voltage drop occurs, before each NAND gate loses its function as a logic element, an L level is first applied to one input of these gates, turning off all these gates. .

Now, the operation of this conventional example when the power supply V' _cc of this sequential control device 1' is normal is as follows.

The control for the device 2'-1 will be explained as an example. The control for other devices is exactly the same.

Control inputs PON' ₁ and POFF' 1 of NAND gates 14'-1 and 15'- ₁ are normally maintained at L level.

When the power of device 2'-1 is currently OFF, in order to turn on this power, input the control input PON' ₁
is set to H level for a specific time period. As a result, the output of the NAND gate 14'-1 becomes L level, current flows through the relay coil ON ₁ , and the corresponding contact ON ₁
make up. Then, the control power supply V _d ′ ₁ and the coil
Current flows through RL′ ₁ , contact ON ₁ , contact OFF ₁ ,
Make contact r _l ′ ₁ .

In this way, the device 2'-1 is powered on, but once the contact r _l ' ₁ is made, the power is turned on via the control power supply V' _d1 , the coil RL' ₁ , the contact r _l ' ₁ , and the contact off ₁ . A current loop is formed, and a self-holding current flows through this loop to self-maintain the make state of the relays RL' ₁ and r _l ' ₁ , so that the control input PON' ₁ returns to the normal L level again. contact
Even if on ₁ is broken, the power-on state of device 2'-1 is maintained.

Next, in order to turn off the power to the device 2'-1 that has been turned on in this way, the control input _POFF1 of the NAND gate 15'-1 is set to H level for a specific time period. As a result, current flows through the coil OFF ₁ , breaking the break point OFF ₁ , and the above-mentioned coil RL′ ₁
As a result, the current flowing through coil RL′ ₁ is cut off, the make contact r _l ′ ₁ mechanically breaks, and device 2′-
1 power is turned off. In this way,
If contact r _l ′ ₁ breaks, the control input
POFF′ ₁ returns to the normal L level again, and contact OFF ₁
Even if the coil RL'- ₁ is formed, the aforementioned current loop including the coil RL'1 is no longer formed, and the power OFF state of the device 2'-1 is maintained as it is.

In this way, when the power supply V' _cc of the sequential control device 1' is normal, the power supply of the device 2'-1 is controlled by setting the control inputs PON' ₁ and POFF' ₁ to H level for a specific time period. ON/OFF can be controlled freely.

Next, when the power supply _V'cc of the sequence control device 1' changes from the normal state to the OFF state, the operation is as follows.

During the process in which the voltage of the power supply _V'cc drops from the normal value to 0, the power-on reset circuit (POR) described above
When it falls below the threshold value E′ ₁ of 12′,
The circuit (POR) 12' has its output as described above.
Immediately drop _V'p to L level. As a result, while the outputs of both NAND gates 14'-1 and 15'-1 are maintained at the H level side, the power supply voltage _V'cc decreases, and eventually reaches a voltage value at which these logic gates cannot operate as logic elements. It decreases to less than E′ ₂ .

As a result, during the process of decreasing the power supply V' _cc mentioned above, no current flows through either the coil ON ₁ or the coil OFF ₁ to change the states of the respective contacts ON ₁ and OFF ₁ , so that the device 2'- The ON/OFF state of the power supply No. 1 is maintained exactly the same as when the power supply _V'cc is in a normal state. It is clear that this works not only for device 2'-1, but also for all other devices in exactly the same way.

In addition, in this conventional example, the power supply voltage V' _cc and the output voltage of the power-on reset circuit (POR) 12'
The operations of V' _p , contacts on ₁ , off ₁ , and r _l ' ₁ of each relay are shown in FIGS. 6 and 7 as time charts.

Figure 6 shows how the power supply V′ _cc is turned on from the initial OFF state.
The device 2'-1 is powered on with _V'cc set to a normal value, and _V'cc is turned off while the device 2'-1 is powered on.

In addition, Fig. 7 shows the device 2'- with V' _cc turned ON.
The case is shown in which the device 2'-1 is powered on, then the device 2'-1 is powered off, and then _V'cc is turned off.

As is clear from these time charts,
The ON/OFF state of the power supply of the device is completely unaffected by the ON/OFF state of the power supply _V'cc of the sequence control device 1'.

In this way, in the prior art, two relays are provided for each device in the sequence control device 1', and these relays control the power on/off of the device and the sequence control device 1'. 'The purpose of this device is to maintain the power on/off status of the device even if the device itself loses power.

However, as described above, when the number of devices increases, the disadvantages of using such a relay become significant in terms of the mounting space and cost of the relay.

Next, the present invention which eliminates the above drawbacks will be explained.

FIG. 1 is a block diagram showing one embodiment of the present invention.

This embodiment includes a sequence control device 1 and m devices 2-1 to 2-m.

Furthermore, this sequence control device 1 includes an SCR circuit 11,
Power-on reset circuit (POR) 12, inverter 13, and each of the aforementioned m devices 2-1
~2-m, respectively, NAND gate 14
-1 to 14-m, and gate 15-1 to 15-
diodes 16-1 to 16-m corresponding to the devices 2-1 to 2-m. Each of these gates uses an open collector type gate to allow wired OR operation with respect to the L level.

In addition, each of the devices 2-1 to 2-m is provided with a control power supply for each device in exactly the same way as in the conventional example described above.
V _d1 to V _do1 , and relays RL ₁ , r _l1 to RL _n , rl _n for turning on/off the power supply to each device using these control power supplies, and the configuration on the device side is exactly the same as the conventional example described above.

Now, details of the SCR circuit 11 are shown in FIG.
This SCR circuit 11 uses a PNP type transistor Q ₁ and an NPN type transistor Q ₂ which have complementary characteristics to each other. Basically, the collector of Q ₁ is used as the base of Q ₂ , and the collector of Q 2 is used as the base of Q ₂ . This circuit connects the collector to the base of _Q1 to provide SCR characteristics. Furthermore, resistors R ₁ and R ₂ are inserted as necessary to balance the collector currents of transistors Q ₁ and Q ₂ , and transistor Q ₂
When transistor Q2 is off, a resistor _R3 is inserted to prevent transistor _Q1 from turning on due to its leakage current, and when transistor _Q2 is off, the potential difference between the emitter and base of transistor _Q1 is Set near 0 and turn off transistor _Q1 as well.
I try to keep it in good condition.

In this SCR circuit 11, when the input voltage Vi is lower than a specific threshold value _E3 , both the transistor _Q1 and the transistor _Q2 are turned off, so that no current flows between the supply voltage Vs and the ground. The input voltage Vi is this threshold E ₃
Transistors Q ₁ and Q ₂
becomes conductive at the same time, and shortens between Vs and ground with low impedance. Along with this,
Connect Vs and Vi with low impedance to bring the potential of Vi closer to the potential of Vs.

This shot effect due to the low impedance between Vs and ground is established as long as the SCR circuit 11 is turned on and Vs has a voltage equal to or higher than the threshold _E3 described above.

Now, next is the power-on reset circuit (POR) 1.
This circuit is exactly the same as 2', and when the power supply voltage _Vcc is higher than a specific threshold value _E1 , it outputs an H level as its output _Vp , and the power supply voltage _Vcc is higher than this threshold value. This is a threshold circuit that outputs an L level as its output _Vp when it becomes lower than _E1 .

This threshold value _E1 is the SCR circuit 1 mentioned above.
The voltage V cc is set so that E ₁ >E ₃ for the threshold value E ₃ of 1, and as described later, when the power supply V _cc of the sequential control device 1 is cut off, the voltage V _cc drops. In the _{process of}
(When the SCR circuit 11 is within the voltage range in which it can function as described above), first, by cutting the threshold value _E1 of the power-on reset circuit 12, its output _Vp is forcibly dropped to the L level. There is.

Furthermore, the logic elements used in this embodiment include NAND gates 14-1 to 14-m, AND gates 15-1 to 15-m, and inverter 1.
3, but since they are all driven using the power supply voltage V _cc , if V _cc drops below a certain level, they will lose their function as logic elements. This V _cc threshold voltage
Assuming E ₂ , each threshold value mentioned above is E ₁ >
It is set so that E ₂ > E ₃ .

First, the operation when the power supply voltage V _cc of the sequence control device 1 is in a normal state will be described.

As described above, when _Vcc is in a normal state, the output _Vp of the power-on reset circuit (POR) 12 is maintained at the H level. This becomes an L level signal via the inverter 13 and is supplied as an input to the SCR circuit 11, so that the input
Vi is kept below the threshold value _E3 of the SCR circuit 11. Therefore, in the normal state of the power supply voltage _Vcc , the SCR circuit 11 is completely OFF, and the connection between Vs and ground is essentially opened, so there is no effect on the operation of the sequential control device 1. I won't give it.

In addition, the power-on reset circuit (POR) 12
The output V _p maintained at H level is supplied as one input to each of the NAND gates 14-1 to 14-m and AND gates 15-1 to 15-m, and the other input of these gates It is kept in a state that allows it to pass through as is.

Now, the control input of each NAND gate 14-1 to 14-m corresponding to each device 2-1 to 2-m
PON ₁ ~ _{PON n} and each AND gate 15-1~
Control inputs POFF ₁ to POFF _n of 15-m are all kept at L level in the normal state. As a result, the output of each NAND gate 14-1 to 14-m goes to H level, and each AND gate 15-1 to
The output of 15-m is maintained at L level.

For example, device 2-
The power supply to 1 is performed as follows.

That is, when the control input PON ₁ of the NAND gate 14-1 corresponding to the device 2-1 is set to H level for a specific time width, this NAND gate 14-1
As a result, the output of device 2-1 falls to L level.
Sufficient current flows through the relay coil RL ₁ to make the corresponding make contact r _l1 , thereby turning on the power to the device 2-1. At the same time, the contact r _l1 closes, and the AND gate 14-1 is connected from the H side of the control power supply V _d1 via the coil RL ₁ and the contact r _l1 .
A current path is generated in the L-level output of the relays RL _{1 and} r l1 , thereby self-maintaining the relays RL 1 and r _l1 in the make state, and the power-on state of the device 2-1 is maintained.

Next, turn off the power to device 2-1 in this state.
In order to do this, the control input of AND gate 15-1
Set POFF ₁ to H level for a specific time period. As a result, the output side of the AND gate 15-1 becomes H level, the current flowing through the coil _RL1 is cut off, and the contact _rl1 is mechanically broken. When the contact r _l1 breaks in this way, the self-holding current becomes 0, so even if the control input POFF ₁ returns to the L level again, the contact r _l1 is held in the broken state and the device 2-1 is in the power OFF state. is maintained.

As described above, when the power supply V _cc of the sequential control device 1 is normal, the device 2-1 is powered on by setting the control input PON ₁ or POFF ₁ to the H level for a specific time period. Or you can cut freely. After turning on or turning off the power to device 2-1 in this way,
By holding the control inputs PON ₁ and POFF ₁ at L level, the power on/off state of the device 2-1 can be maintained as it is.

The above operation is not limited to Device 2-1.
All other devices can also be freely controlled independently of each other using corresponding control inputs. The outputs of the AND gates 15-1 to 15-m are rectified and combined via diodes 16-1 to 16-m and connected to the output side Vs of the SCR circuit 11, so they interfere with each other in the above operations. It is clear that there is no such thing.

Next, a case will be described in which a power failure occurs in the power supply V _cc of the sequence control device 1 itself.

Initially, the power of device 2-1 is on, so contact r _l1 is made, and the control power
V _d1 , coil RL ₁ , contact r _l1 and AND gate 1
A case will be explained in which a power cut occurs in the power supply V _cc while a self-holding current is flowing through 5-1.

When the power supply _Vcc is cut off and its voltage value drops, it first crosses the threshold _E1 of the power-on reset circuit (POR) 12 on the way.
When this occurs, the power-on reset circuit (POR) 12 immediately brings its output voltage V _p to the L level as described above. As mentioned above, E ₁ > E ₂ is set, so at this point, NAND gate 14
-1 to 14-m and AND gate 15-1 to 1
5-m also has a function as a logic element, so from then on until V _cc falls below E ₂ ,
The effects of the control inputs of PON ₁ to PON _n and POFF ₁ to POFF _n are disabled to maintain the current logic level.

On the other hand, when the output voltage V _p of the power-on reset circuit (POR) 12 reaches the L level, the inverter 13, which is still functioning as a logic element at this point, changes its output from the L level to the H level. to be reversed. As a result, SCR circuit 12
The input Vi for SCR circuit 12 is definitely higher than the aforementioned threshold value _E3 of SCR circuit 12.
2 becomes conductive and connects the output Vs and ground with low impedance. As a result, the device 1
A current loop is formed in which the control power supply V _d1 , the relay coil RL ₁ , the contact r _l1 , the diode 16-1, and the SCR circuit 11 are connected in series, and until then,
The self-holding current loop formed by the power supply V _d1 , the coil RL ₁ , the contact r _l1 and the AND gate 15-1 is taken over by the newly formed self-holding current loop. Moreover, since E ₁ > E ₂ is set, before AND gate 15-1 loses its function, AND gate 15-1
The continuity between the return wire 1000-1 of the contact _rl1 and the ground to flow the self-holding current held by the diode 16-1 has become conductive.
The SCR circuit 11 ensures that the holding current is not cut off during the handover process. As a result, the power-on state of device 2-1 is V _cc
It is reliably held even if becomes 0.

Note that even if V _cc becomes 0, power to the SCR circuit 11 is supplied from the control power supply V _d1 of the device 2-1 via the diode 16-1, so that the SCR circuit 11 can maintain a conductive state. .

The above explanation is for device 2-1, but the same applies to other devices, and even if there are multiple devices in the power-on state in the system, the power-on state of each of these devices It is also clear that holds for V _cc OFF.

Next, a case will be described in which the power supply V _cc is cut off while the device 2 - 1 is powered off, that is, r _l1 is broken and no current flows through the coil RL ₁ .

When the power supply _Vcc is turned off and its voltage drops beyond _E1 , the output _Vp of the power-on reset circuit (POR) 12 becomes L level, as described above.
As a result, the NAND gate 14-1 receives the control input
The control function of PON ₁ is disabled and its output is held at its previous high level state (relatively high output impedance) while this logic element has its function, which is further reduced by V _cc
Even if the voltage decreases and the NAND gate 14-1 loses its function as a logic element, the state of high output impedance is maintained as it is. Therefore, at any point during which V _cc falls from the normal state to 0, the current that makes the contact r _l1 does not flow through the coil RL ₁ . As a result, the power-off state of the device 2-1 is maintained as it is.

The above explanation is for device 2-1, but the same applies to other devices, and even if there are multiple devices in the power-off state, each of these _devices will be It is also clear that the powered off state of the device is maintained.

In addition, in FIG. 3 and FIG. 4, V _cc , V _p , NAND gate 14-1, AND gate 15-1, SCR
Changes in the state of circuit 11 and relay r _l1 are shown as time charts.

Figure 3 shows that V _cc is first turned on, and after V _cc reaches the normal voltage, the device 2-1 is powered on.
This is a time chart showing the changes when _Vcc is turned off while the device 2-11 is powered on.
After V _cc is in a normal state and device 2-1 is powered on, the power to device 2-1 is turned off while V _cc is in a normal state, and V _cc is turned on while device 2-1 is powered off. This is a time chart showing the changes when turned off.

From these time charts, turn off the power supply V _cc .
In contrast, it can be seen that the power on/off state of the device 2-1 is maintained unchanged.

In addition, in these time charts, NAND gate 14-1 and AND gate 15-
1 indicates a state in which the output is at H level and the impedance between the ground and the ground is high, and an OFF state, and an ON state in which the output is at the L level and the impedance between the ground and the ground is low. Also, the SCR circuit 11
The ONENABLE state is the output Vs of the SCR circuit 11.
This indicates that it can be turned on if the necessary voltage is applied to it.

These figures 3 and 4 show the device 2-1.
Although this example shows how to turn on/off power to a device, it is clear that the same applies to other devices as well.

In this way, this embodiment can maintain the power on/off state of each device controlled by itself even if the device itself is powered off.

Note that the above is one embodiment of the present invention, and the present invention is not limited to the above embodiment.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to configure a sequence control device that can maintain the power on/off state of each device controlled by itself even if its own power is cut off, without using a relay. Moreover, the device of the present invention has only one diode for each device instead of two relays provided for each device, and only one SCR circuit provided regardless of the number of devices, compared to the conventional example. Therefore, the advantages of small mounting space and low cost become increasingly noticeable as the number of devices increases.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
Fig. 2 is a diagram showing an example of the SCR circuit used in this embodiment, Figs. 3 and 4 are time charts for explaining the operation of this embodiment, and Fig. 5 is a block diagram for explaining the conventional example. Figures 6 and 7
The figure is a time chart for explaining the operation of the conventional example. In the figure, 1... Sequence control device, 2-1 to 2-
m...device, 11...SCR circuit, 12...power-on reset circuit (POR), 13...inverter,
14-1~14-m...Nand Gate, 15-1~
15-m...and gate, 16-1 to 16-m...
Diode, RL ₁ , r _l1 ~ RL _n , r _ln ...Relay, V _d1
~V _dn …Control power supply.

Claims (1)

[Claims] 1. Sequence control of a plurality of devices each having a relay for turning on/off its own power, controlling the order of turning on/off the power of the devices including the relay via the relay. In the device, a self-holding current for self-maintaining the make state of each of the relays is supplied to a coil of the relay and a make-type contact corresponding to the coil, which are connected in series to a control power source for a device including the relay. , a diode for rectifying and combining the self-holding current of each device;
an SCR circuit composed of a PNP transistor and an NPN transistor, whose conduction is controlled by the output of a power-on reset circuit included in the sequence control device, and is configured to conduct the rectified and combined self-holding current; A sequence control device characterized in that the sequence control device can be obtained through.