JPH0337529U - - Google Patents
Info
- Publication number
- JPH0337529U JPH0337529U JP1989096748U JP9674889U JPH0337529U JP H0337529 U JPH0337529 U JP H0337529U JP 1989096748 U JP1989096748 U JP 1989096748U JP 9674889 U JP9674889 U JP 9674889U JP H0337529 U JPH0337529 U JP H0337529U
- Authority
- JP
- Japan
- Prior art keywords
- data
- cpu
- protection circuit
- command
- floppy disk
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Storage Device Security (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
Description
第１図は本考案の一実施例についてａはフロツ
ピーデイスク装置に組込んだ概略構成図、ｂは実
施例の配線図、第２図はデータビツト列の変換の
１例を示す図である。
１…ＣＰＵ、２…メモリ、３…ＦＤＣ（フロツ
ピーデイスクコントローラ）、４…フロツピーデ
イスク装置、１０…データ保護回路、１１…コマ
ンド／ステータス用バツフア、１２…データ用バ
ツフア、１３…ＮＯＴ回路、１４…制御信号。
Fig. 1 shows an embodiment of the present invention; a is a schematic diagram of the structure incorporated into a floppy disk device; b is a wiring diagram of the embodiment; and Fig. 2 is a diagram showing an example of data bit string conversion. . 1... CPU, 2... Memory, 3... FDC (floppy disk controller), 4... Floppy disk device, 10... Data protection circuit, 11... Command/status buffer, 12... Data buffer, 13... NOT circuit, 14...Control signal.
Claims (1)
のデータバスに、ＣＰＵからの制御信号により導
通・不導通状態が互いに相反的に定められるコマ
ンド／ステータス用バツフアおよびデータ用バツ
フアを並列に介在してなるデータ保護回路であつ
て、 前記データ用バツフアは、ライトコマンドおよ
びリードコマンドの実行時にのみ導通状態となさ
れ、結線手段によりライトコマンドではＣＰＵか
らの信号データビツト列を変換して書込みデータ
となし、リードコマンドでは前記書込みデータを
信号データに復原してＣＰＵへ送出する ことを特徴とするフロツピーデイスク装置のデ
ータ保護回路。[Claims for Utility Model Registration] Parallel command/status buffers and data buffers whose conducting/non-conducting states are determined reciprocally by control signals from the CPU on the data bus to the CPU side of the floppy disk controller. The data protection circuit is interposed in the data protection circuit, and the data buffer is made conductive only when a write command and a read command are executed, and the wiring means converts and writes a signal data bit string from the CPU in the write command. A data protection circuit for a floppy disk device, characterized in that in a read command, the write data is restored to signal data and sent to a CPU.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989096748U JPH0337529U (en) | 1989-08-21 | 1989-08-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989096748U JPH0337529U (en) | 1989-08-21 | 1989-08-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0337529U true JPH0337529U (en) | 1991-04-11 |
Family
ID=31645931
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989096748U Pending JPH0337529U (en) | 1989-08-21 | 1989-08-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0337529U (en) |
-
1989
- 1989-08-21 JP JP1989096748U patent/JPH0337529U/ja active Pending
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