JPH0337533U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of a data conversion circuit according to an embodiment of this invention, Fig. 2 is a memory map of the data conversion table of Fig. 1, and Fig. 3 is a data conversion circuit in which a full adder is added to Fig. 1. , FIG. 4 is a conversion diagram showing the relationship between the input data value in FIG. 3 and the gradation level converted into data, FIG. 5 is a memory map of the data conversion table in FIG. A schematic circuit diagram showing a conventional data conversion circuit, FIG. 7 is a conversion diagram showing the relationship between the input data value of FIG. 6 and the gradation level of data conversion, and FIG. 8 is a data conversion circuit of FIG. This is the memory map of In the figure, 1 is a ROM/RAM, 3 is a range decoder, 4 is a pull-up means, 5 is a pull-down means, and 9 is a full adder. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims for Utility Model Registration] (1) In a data conversion circuit that inputs input data to a storage means storing a data conversion table, converts the data, and outputs the data, if the input data is within a certain range, the storage means a range decoder that outputs a signal to stop the input data, and outputs a signal to activate the storage means when the input data is outside the predetermined range; the storage means for reading out a data conversion value corresponding to the input data and outputting the conversion data in response to an actuation signal from the decoder; 1. A data conversion circuit comprising pull-up/pull-down means for outputting constant data based on a valid signal. (2) The data conversion circuit according to claim 1, further comprising a full adder for adding the input data and a constant offset value on the input side of the range decoder and the storage means.