JPH0337732A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To easily test a semiconductor integrated circuit device by automatically setting a common circuit to the test mode of a microcomputer core and the test mode of a logic circuit part by second and third mode setting signals generated from a signal generating means. CONSTITUTION:The second mode setting signal is generated by a signal generating means 8 at the time of testing a microcomputer core 2. In this case, only the microcomputer core 2 is coupled to shared circuits 4 and 5 and signals for the test are inputted and outputted through shared circuits 4 and 5. A third mode setting signal is generated by the signal generating means 8 at the time of testing a logic circuit part 3. In this case, only the logic circuit part 3 is coupled to shared circuits 4 and 5 and signals for the test are inputted and outputted through shared circuits 4 and 5. Thus, the microcomputer core 2 and the logic circuit part 3 are individually tested.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to an ASIC (integrated circuit for specific applications) using a microcomputer core.

[Prior Art] In recent years, as electronic devices have become more sophisticated, smaller, and cheaper, there has been a growing demand for developing LSIs including microcomputers for each application product. Furthermore, it is required to develop such LSIs quickly and reliably.

An example of a technique for developing an ASIC using a microcomputer as its core is shown in FIG. 20.

This technology uses 20 CPU (central processing unit) cores.
1. ROM (read only memory) 202, RAM
A one-chip microcomputer 208 including (random access memory) 20B, I/F circuit (interface circuit) 2○4, timer 205, I10 port (human output port) 206, and bus 207 contains logic specific to the user's system. A circuit 209 is incorporated and these are integrated on one chip. As shown in FIG. 20, logic circuit 209 is connected to bus 207 within microcomputer 208.

Further, as another method for developing an ASIC having a microcomputer as its core (hereinafter referred to as a microcomputer core ASIC), there is an example of a technique as shown in FIG. In this technique, a microcomputer chip 301 and a logic circuit chip 302 are placed on a chip 303, and new pads 304 necessary to integrate them into one chip are provided. And the microcomputer chip 301
pad 305 on top, pad 30 on logic circuit 302
6 and the newly provided pad 304 to integrate them into one chip.

According to these techniques, a general-purpose microcomputer and a user-specific logic circuit are integrated into one chip, making it easy to downsize the system and reduce costs.

[Problems to be Solved by the Invention] However, in the technique shown in FIG. 20, in order to incorporate the logic circuit 209 into the one-chip microcomputer 208, the layout needs to be changed and added, and the microcomputer chip 208 is The entire structure will be remodeled. Therefore, chip development, comprehensive timing verification, test program development, and debugging take time. Additionally, chip development requires engineers who are familiar with everything about microcomputers, including their patterns, circuit configurations, timing, and testing methods.

Furthermore, test programs, software development/debugging tools, etc. that have already been developed for microcomputer chips cannot be used. Therefore, new software development and debugging tools must be developed.

On the other hand, in the technology shown in FIG. 21, a number of chips are integrated into one chip by wiring between them, so pads 301 and 302 are placed on each chip 301 and 302.
5,306, input/output circuits 307, 308, etc. Therefore, pads, driver circuits, etc. are duplicated, resulting in waste and increasing chip size. Furthermore, since the microcomputer chip 301 and the logic circuit chip 3゜2 cannot be electrically separated, test programs, software development/debugging tools, etc. that have already been developed for the microcomputer chip or logic circuit chip, etc. cannot be used.

Therefore, new test programs, software development/debugging tools, etc. must be developed.

An object of the present invention is to provide a semiconductor integrated circuit device that can realize a microcomputer core ASIC in a short time with less development effort and cost.

[Means for Solving the Problems] A semiconductor integrated circuit device according to the present invention is a semiconductor integrated circuit device formed on one chip, which includes a microcomputer core including a central processing unit and a storage device,
It includes a logic circuit section controlled by a microcomputer core, a signal generation means, a shared circuit, and a selection means.

The signal generating means generates a first mode setting signal, a second mode setting signal and a third mode setting signal. The shared circuit has input/output means for inputting or outputting signals to or from the microcomputer core and logic circuit section.

The selection means selectively couples the microcomputer core and the logic circuit section to the driver means in response to the first mode setting signal, and couples the microcomputer core to the driver means in response to the second mode setting signal. , 3rd
The logic circuit portion is coupled to the logic means in response to the mode setting signal.

[Operation] During normal operation, the first mode setting signal is generated by the signal generating means. In this case, a shared circuit is commonly used by the microcomputer core and the logic circuit section, and signals are input and output to and from the microcomputer core and the logic circuit section via this common circuit.

When testing the microcomputer core, the second mode setting signal is generated by the signal generating means. In this case, only the microcomputer core is coupled to the shared circuit, and signals for testing are output via this shared circuit. On the other hand, when testing the logic circuit section, the third mode setting signal is generated by the signal generating means. in this case,
Only the logic circuit section is coupled to a shared circuit, and signals for testing are outputted via this shared circuit.

In this way, the microcomputer core and logic circuit section can be tested individually, making it possible to use test programs and software development/debugging tools that have already been developed for general-purpose microcomputers and logic circuits. I can do it.

Furthermore, since the pads and driver means are not included in the microcomputer core and logic circuit section but are included in the shared circuit, the chip size is smaller than in the conventional example. Furthermore, the logic circuit section can be designed according to specifications without changing or adding to the layout of the microcomputer core.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a plan view showing a schematic configuration of a semiconductor integrated circuit device according to an embodiment of the present invention. A microcomputer core (or microcontrol unit core; hereinafter referred to as microcomputer core) 2 and a random logic circuit 3 are provided on a semiconductor chip 1 . A common shared terminal circuit 4, a selective shared terminal circuit 5, a dedicated terminal circuit 6 for a microcomputer core, and a dedicated terminal circuit 7 for a random logic circuit are provided on the peripheral portion of the semiconductor chip 1. Further, a mode setting signal generation circuit 8 and a mode signal input circuit 9 are provided on the semiconductor chip 1.

As shown in FIG. 2, the microcomputer core 2 is a CPU core 2
1, ROM 22, RAM 23, I/F circuit 24, timer 25, I10 port 26, and bus 27, but does not include input/output circuits such as human output drivers and pads.

The random logic circuit 3 includes various gates, counters,
A logic circuit consisting of flip-flops, etc.
Designed according to specific application specifications.

Next, referring to FIG. 3, the common terminal circuit 4 is normally coupled to the microcomputer core 2 and the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The selective common terminal circuit 5 is normally fixedly coupled to either the microcomputer core 2 or the random logic circuit 3, and is selectively coupled to the microcomputer core 2 or the random logic circuit 3 during testing. The dedicated terminal circuit 6 is fixedly coupled only to the microcomputer core 2, and the dedicated terminal circuit 7 is fixedly coupled only to the random logic circuit 3.

The mode signal input circuit 9 is configured to operate the semiconductor integrated circuit device in a normal mode and a test mode of the microcomputer core 2 (hereinafter referred to as M
A mode signal for setting the random logic circuit 3 to a test mode (hereinafter referred to as an R/L test mode) is provided. In response to the output of the mode signal input circuit 9, the mode setting signal generation circuit 8 outputs the common terminal circuit 4 and the selected common terminal circuit 5.
Give a mode setting signal to.

FIG. 4 is a block diagram showing the configurations of the common terminal circuit 4 and the selective common terminal circuit 5. As shown in FIG. Common shared terminal circuit 4
consists of a switching circuit 41 and an input/output circuit 42, and the selection common terminal circuit 5 similarly consists of a switching circuit 51 and an input/output circuit 52. The switching circuit 41 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal line LR. Similarly, the switching circuit 51 is connected to the microcomputer core 2 by a signal line LM and to the random logic circuit 3 by a signal line LR. Furthermore, a mode setting signal is applied to the switching circuit 41 and the switching circuit 51 from the mode setting signal generation circuit 8 via the signal line LC.

5A, 5B, and 5C are schematic diagrams for explaining the functions of the common terminal circuit 4. FIG.

In the normal mode, the input/output circuit 42 is coupled to the microcomputer core 2 and the random logic circuit 3 by the switching circuit 41, as shown in FIG. 5A.

In the MCU test mode, as shown in FIG. 5B, the input/output circuit 42 is switched to the microcomputer core 2 by the switching circuit 41.
is combined with In R/L test mode, the 5th C
As shown in the figure, an input/output circuit 42 is coupled to the random logic circuit 3 by a switching circuit 41.

FIG. 6 is a schematic diagram for explaining the function of the selection common terminal circuit 5. In the normal mode, as shown in FIG. 6, the input/output circuit 52 is fixedly coupled to either the microcomputer core 2 or the random logic circuit 3 by the changeover switch 5.

Which of the microcomputer core 2 and the random logic circuit 3 it is coupled to is determined by the specifications of the semiconductor integrated circuit device.

In the MCU test mode, as in the case of the common terminal circuit 4, the input/output circuit 52 is coupled to the microcomputer core 2 by the switching circuit 51. Also in the R/L test mode, the input/output circuit 52 is coupled to the random logic circuit 3 by the switching circuit 51, as in the case of the common terminal circuit 4.

FIG. 7 is a diagram showing the configuration of the mode setting signal generation circuit 8 and the mode signal manual circuit 9. As shown in FIG. Mode signal input circuit 9
includes pads 91.92 and input buffers 93.94. Mode setting signal generation circuit 8 is supplied with mode signal φO via pad 91 and input buffer 93, and mode signal φ1 via pad 92 and input buffer 94. The mode setting signal generation circuit 8 is
Mode signal φ0. Mode setting signal TN based on φ1,
Generates TM and TR. The mode setting signal TN is active in the normal mode, the mode setting signal TM is active in the MCU test mode, and the mode setting signal TR is active in the R/L test mode.

FIG. 8 is a diagram showing the configuration of the signal lines in detail.

The signal line LM consists of a data line for transmitting output data DOM, a data line for transmitting manual data DIM, and 19 lines for transmitting control signal CM. This signal line LM is connected to the I10 port 26 of the microcomputer core 2 (see FIG. 2).

The signal line LR includes a data line for transmitting output data DOR, a data line for transmitting input data DIR, and a control line for transmitting control signal CR. Further, the signal line LC includes three signal lines for transmitting mode setting signals TN, TM, and TR.

FIG. 9 is a diagram showing the configuration of the common shared terminal circuit 4. Output circuit 42 includes a pad 43 and an output driver 44.

In the normal mode, the mode setting signal TN becomes active. Thereby, the switching circuit 41 controls the control signals CM, C
one of R and output data DOM.

One side of DOR is provided to output driver 44. The output driver 44 outputs output data to the pad 43 in response to the control signal.

In the MC1J test mode, the mode setting signal TM becomes active. Thereby, the switching circuit 41 provides the control signal CM and the output data DOM to the output driver 44. The output driver 44 outputs output data DOM to the pad 43 in response to the control signal CM.

In the R/L test mode, the mode setting signal TR becomes active. Thereby, the switching circuit 41 receives the control signal C.
R and output data DOR are provided to the output driver 44. The output driver 44 outputs output data DOR to the pad 43 in response to the control signal CR.

Further, the human input data DIM is input from the pad 43 to the microcomputer core 2, and the input data DIR is input from the pad 43 to the random logic circuit 3.

The configuration of the selection common terminal circuit 5 is also similar to the configuration shown in FIG. However, in the selection common terminal circuit 5, the output data is 700M in the normal mode.

Predetermined output data of the DOR is always output.

FIG. 10 is a diagram showing the configuration of the dedicated terminal circuit 6. Dedicated terminal circuit 6 includes a pad 61 and an output driver 62. The output driver 62 has a control signal CM and an output data 7.
00M is given. Input data DIM is also input from the pad 61 .

The configuration of the dedicated terminal circuit 7 is also similar to the configuration of the dedicated terminal circuit 6.

11A, 12A, and 13A are diagrams showing specific configuration examples of the switching circuit 41 in the common terminal circuit 4, and FIGS. 11B, 12B, and mlBB explain their operations. FIG. 2 is a diagram showing a truth table for

The switching circuit 41 shown in FIG. 11A includes a switching signal generation circuit 45, selectors 46, 47, and an OR gate 48. The switching signal generation circuit 45 generates mode setting signals TN, T
The switching signals MSB and MSS are generated in response to the control signal CR from the random logic circuit 3 and the random logic circuit 3. The selector 46 selects inputs A, B,
Select one of C and output. Selector 47 selects and outputs one of inputs A and B in response to switching signal MSS. In this example, microcomputer core 2
and random logic circuit 3 both perform input/output operations.

FIG. 11B shows which of the selectors 46 and 47 the switching signals MSB and MSC select depending on the mode. As shown in the figure, in the normal mode, the manual power C of the selector 46 is selected by the switching signal MSB. As a result, the output driver 44 is given a signal obtained by ORing the control signal CM from the microcomputer core 2 and the control signal CR from the random logic circuit 3. When the control signal CR is "01", the input A of the selector 47 is selected by the switching signal MSS.

As a result, output data 700M from the microcomputer core 2 is given to the output driver 44. As a result, the output driver 44 outputs output data 700M to the pad 43 in response to the control signal CM. On the other hand, when the control signal CR is "1°," the switching signal MSS selects the manual input B of the selector 47. Thereby, the output data DOR from the random logic circuit 3 is given to the output driver 44. Therefore, the output The driver 44 outputs output data DOR to the pad 43.

In particular, in the MCUC strike mode, the manual power A of the selector 46 is selected by the switching signal MSB, and the manual power A of the selector 47 is selected by the switching signal MSS.

Thereby, the control signal CM and output data D.

M is provided to output driver 44.

In the R/L test mode, input B of selector 46 is selected by switching signal MSB, and input B of selector 47 is selected by switching signal MSS.

As a result, the output driver 44 is provided with the control signal CR and the output data DOR.

On the other hand, input data DIM is applied from the pad 43 to the microcomputer core 2, and input data DIR is applied from the pad 43 to the random logic circuit 3.

The switching circuit 41 shown in FIG. 12A includes a switching signal generation circuit 45a and selectors 46 and 47. In this example, microcomputer core 2 performs input/output operations,
Random logic circuit 3 performs only output operation.

As shown in FIG. 12B, in the normal mode, the manual power B of the selector 46 is selected by the switching signal MSB.

Input B is "1". Therefore, the output driver 44 becomes conductive. Furthermore, input B of the selector 47 is selected by the switching signal MSS. Thereby, the output data DOR is output to the pad 43 via the output driver 44. In this case, the microcomputer core 2 performs only manual operation. Therefore, the human power data 501M is given to the microcomputer core 2 from the pad 43.

In the MCUC strike mode, the switching signal MSB selects the manual input A of the selector 46, and the switching signal MSS selects the input A of the selector 47.

Thereby, the output driver 44 outputs output data 200M to the pad 43 in response to the control signal CM.

In the R/L test mode, input B of selector 46 is selected by switching signal MSB, and input B of selector 47 is selected by switching signal MSS.

As a result, the output driver 44 outputs data D.

Output R to the bad 43.

The switching circuit 41 shown in FIG. 13A includes a switching signal generation circuit 45b and a selector 46. In this example, the microcomputer core 2 performs input/output operations, and the random logic circuit 3 performs only input operations.

As shown in FIG. 13B, in the normal mode, input A of the selector 46 is selected by the switching signal MSH.

Thereby, the output driver 44 outputs output data 200M to the pad 43 in response to the control signal CM. In this case, the microcomputer core 2 performs an output operation. Random logic circuit 3 receives human data D from bad 43.
IR will be done manually.

In the MCU test mode, input A of the selector 46 is selected by the switching signal MSB. Thereby, the output driver 44 outputs output data 200M to the pad 43 in response to the control signal CM.

In the R/L test mode, input B of the selector 46 is selected by the switching signal MSH. Input B of selector 46
is "O". Therefore, the output driver 44 becomes non-conductive. In this case, the random logic circuit 3
The human power data DIR is inputted from the pad 43.

14A, 15, and 16 are diagrams showing specific configuration examples of the switching circuit 51 in the selection terminal circuit 5, and FIG. 14B is a diagram showing truth values for explaining their operation. It is a figure showing a table.

The switching circuit 51 shown in FIG. 14A includes a switching signal generation circuit 55 and selectors 56 and 57.

The switching signal generation circuit 55 generates a mode setting signal TN.

A switching signal MSC is generated in response to TM, TR and switch signal SO. The switch signal SO is fixedly set in advance to m12 or m01 before the switch S. In this example, both the microcomputer 2 and the random logic circuit 3 perform input/output operations.

In the normal mode, the selector 56 is controlled by the switching signal MSC.
Input A or input B of the selector 57 is selected, and input A or input B of the selector 57 is selected.

Thereby, the output driver 54 outputs the control signal CM or C.
Bad 5 output data 200M or DOR in response to R
Output to 3.

In the MCU test mode, the human power A of the selector 56 is selected by the switching signal MSC, and the human power A of the selector 57 is selected. Thereby, the output driver 54 outputs output data 200M to the pad 53 in response to the control signal CM.

In the R/L test mode, the manual input B of the selector 56 is selected by the switching signal MSC, and the input B of the selector 57 is selected. Thereby, the output driver 54 outputs the output data DOR to the pad 53 in response to the control signal CR.

On the other hand, input data DIM is input from the pad 53 to the microcomputer core 2, and input data DIR is input from the pad 53 to the random logic circuit 3.

In the example of FIG. 14A, the switch signal SO is generated before the switch S connected to the power supply terminal or the ground terminal, but as shown in FIG. 14C, the switch signal SO is generated by the pad 58 and the manual buffer It may also be applied from the outside via 59. Alternatively, the switch signal SO may be generated from a register R within the random logic circuit 3, as shown in FIG. 14D.

The switching circuit 51 shown in FIG. 15 includes a switching signal generation circuit 55 and selectors 56 and 57, similar to the switching circuit 51 shown in FIG. 14A. However, the input B of the selector 56 is set to '1'.
The IM is manually input from the pad 53 to the microcomputer core 2 only.

In this example, the microcomputer core 2 performs a human output operation, and the random logic circuit 3 performs only an output operation.

The switching circuit 51 shown in FIG. 16 includes a switching signal generation circuit 55 and a selector 56. Input B of selector 56
is set to "O". In this example, the microcomputer core 2 performs input/output operations, and the random logic circuit 3 performs only input operations.

FIG. 17A shows the selector 46.4 shown in FIG. 11A.
FIG. 7 is a circuit diagram showing a specific configuration of No. 7;

Selector 47 includes transfer gates Gl, G2 and buffer B1, and selector 46 includes transfer gates G3 . G4. G5 and buffer B2. Switching signals a, a'we, and e are applied to the transfer gates 61 to G5, respectively, from the switching signal generation circuit 45 (FIG. 11A). Switching signals a, b, c, d,
e is the mode setting signal TN as shown in FIG. 17B.
, TM, TR and a control signal CR.

FIG. 18A shows the selector 56.5 shown in FIG. 14A.
FIG. 7 is a circuit diagram showing a specific configuration of No. 7;

The selector 56 is a transfer gate G6. G7 and buffer B3, and selector 57 includes transfer gates G8. G9 and buffer B4. Transfer gate gate G6. G8 has a switching signal generation circuit 55
(FIG. 14A), switching signals f and f are given.

Transfer game) G7. G9 has a switching signal generation circuit 5
Switching signals g and T are applied from 5 to 5.

The switching signals f and g are as shown in FIG. 18B.
It is obtained by a logical operation using mode setting signals TN, TM, and TR.

Next, the operation of the semiconductor integrated circuit device of this embodiment will be explained.

In the normal mode, the common shared terminal circuit 4 is commonly used by the microcomputer core 2 and the random logic circuit 3, and signals are input and output to and from the microcomputer core 2 and the random logic circuit 3 via the common shared terminal circuit 4. . Further, signals are output to the microcomputer core 2 via the dedicated terminal circuit 6, and signals are input to and output from the random logic circuit 3 via the dedicated terminal circuit 7. When the selective common terminal circuit 5 is coupled to the microcomputer core 2, a signal is outputted to the microcomputer core 2 via the selective common terminal circuit 5. Conversely, when the selective common terminal circuit 5 is coupled to the random logic circuit 3, signals are inputted to and output from the random logic circuit 3 via the selective common terminal circuit 5.

In the MCU test mode, the common shared terminal circuit 4 and the selected shared terminal circuit 5 are coupled only to the microcomputer core 2. In this case, the common shared terminal circuit 4, the selected shared terminal circuit 5
Alternatively, a test signal is outputted to the microcomputer core 2 via the dedicated terminal circuit 6.

In the R/L test mode, the common shared terminal circuit 4 and the selected shared terminal circuit 5 are coupled only to the random logic circuit 3. In this case, a test signal is outputted to the random logic circuit 3 via the common terminal circuit 4, the selective common terminal circuit 5, or the dedicated terminal circuit 7.

As mentioned above, each of the microcomputer core 2 and random logic circuit 3 can be tested individually, so test programs and software development that have already been developed for general-purpose microcomputers and logic circuits can be used. can be used.

Further, since the pads and drivers are not included in the microcomputer core 2 and the random logic circuit 3, but are included in the common shared terminal circuit 4 and the selected shared terminal circuit 5, the chip size is reduced.

Furthermore, the configuration of the random logic circuit 3 can be designed according to specifications without changing or adding to the layout of the microcomputer core 2.

Next, an example of use of the semiconductor integrated circuit device of this embodiment will be explained with reference to FIG.

Normally, arithmetic processing is performed in the microcomputer core 2,
The random logic circuit 3 performs high-speed processing that cannot be processed by the microcomputer core 2.

For example, if the random logic circuit 3 is designed to serve as a general-purpose bus controller, the dedicated terminal circuit 7 may be connected to a plurality of personal computers 1 via the bus 100.
01, a disk device 106, etc. are connected.

Furthermore, the random logic circuit 3 is configured to control a specific control target 102.
If it is designed to be a dedicated controller for
A controlled object 102 is connected to the dedicated terminal circuit 7 .

For example, an external memory 103 is connected to the common terminal circuit 4. For example, the selection common terminal circuit 5 includes a CPU 10.
4 is connected to the dedicated terminal circuit 6, and a disk controller 105, for example, is connected to the dedicated terminal circuit 6. Selection (phase terminal circuit 5
can also be coupled to the random logic circuit 3 according to the user's order.

As mentioned above, according to this embodiment, the microcomputer core ASC
I can be realized at low cost and in a short period of time with little development effort.

[Effects of the Invention] As described above, according to the present invention, test programs and software development/debugging tools that have already been developed for microcomputers or logic circuits can be used, and the chip size can be reduced. be converted into Furthermore, even if one is not familiar with microcomputer patterns, circuit configurations, timings, testing methods, etc., the logic circuit section can be easily designed according to the user's requirements.

In particular, the shared circuit is automatically set to the normal mode, the microcomputer core test mode, and the logic circuit section test mode by the first, second, and third mode setting signals generated by the signal generating means. Therefore, testing of semiconductor integrated circuit devices can be easily performed.

Therefore, it is possible to realize an ASIC using a microcomputer in a short period of time and with less development effort and cost.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention. FIG. 2 is a functional block diagram showing the configuration of the same embodiment. FIG. 3 is a schematic diagram for explaining the features of the main parts of the embodiment. FIG. 4 is a block diagram showing the configuration of the common shared terminal circuit and the selected shared terminal circuit. 5A, 5B, and 5C are schematic diagrams for explaining the functions of the common terminal circuit, with FIG. 5A showing the normal mode, FIG. 5B showing the MCU test mode, and FIG. Figure 5C is a diagram showing the R/L test mode. FIG. 6 is a schematic diagram for explaining the function of the selective common terminal circuit. FIG. 7 is a diagram showing the configuration of a mode setting signal generation circuit and a mode signal input circuit. FIG. 8 is a diagram showing a specific configuration of signal lines. FIG. 9 is a diagram showing the configuration of the common shared terminal circuit. FIG. 10 is a diagram showing the configuration of the dedicated terminal circuit. 11th
FIG. A is a diagram showing an example of the configuration of a switching circuit in the common terminal circuit. FIG. 11B is a diagram for explaining the operation of the switching circuit shown in FIG. 11A. FIG. 12A is a diagram showing another example of the configuration of the switching circuit in the common terminal circuit. 1st
FIG. 2B is a diagram for explaining the operation of the switching circuit of FIG. 12A. FIG. 13A is a diagram showing still another example of the configuration of the switching circuit in the common terminal circuit. FIG. 13B is a diagram for explaining the operation of the switching circuit shown in FIG. 13A. FIG. 14A is a diagram showing an example of the configuration of a switching circuit in the selection common terminal circuit. FIG. 14B is a diagram for explaining the operation of the switching circuit shown in FIG. 14A. FIG. 14C is a diagram showing an example of a method of generating a switch signal. FIG. 14D is a diagram showing another example of a method of generating a switch signal. FIG. 15 is a diagram showing another example of the configuration of the switching circuit in the selection common terminal circuit. FIG. 16 is a diagram showing still another example of the configuration of the switching circuit in the selection common terminal circuit. FIG. 17A is a specific circuit diagram of the selector included in the switching circuit in the common terminal circuit. FIG. 17B is a diagram for explaining logical operations for obtaining the switching signal applied to the selector of FIG. 17A. FIG. 18A is a specific circuit diagram of the selector included in the switching circuit in the selection common terminal circuit. FIG. 18B is a diagram for explaining a logical operation for obtaining a switching signal applied to the selector of FIG. 18A. FIG. 19 is a diagram for explaining an example of use of the embodiment. Figure 20 shows a conventional microcomputer core ASIC.
It is a top view showing an example. FIG. 21 is a functional block diagram showing another example of a conventional microcomputer core ASIC. In the figure, 1 is a semiconductor chip, 2 is a microcomputer core, 3 is a random logic circuit, 4 is a common shared terminal circuit, 5 is a selection shared terminal circuit, 6.7 is a dedicated terminal circuit, 8 is a mode setting signal generation circuit, 9 is a mode signal input circuit, 41.51 is a switching circuit, 43.53 is a pad, 44
．． 54 is an output driver. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device formed on a chip, comprising: a microcomputer core including a central processing unit and a storage device; a logic circuit section controlled by the microcomputer core; A shared circuit comprising a signal generating means for generating a mode setting signal, a second mode setting signal and a third mode setting signal, and an input/output means for manually or outputting signals to the microcomputer core and the logic circuit section;
and selectively coupling the microcomputer core and the logic circuit section to the input/output means in response to the first mode setting signal, and causing the microcomputer core to move forward in response to the second mode setting signal. A semiconductor integrated circuit device, comprising a selection means coupled to an input/output means and for coupling the logic circuit section to the input/output means in response to the third mode setting signal.