JPH0337768B2 - - Google Patents
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- Publication number
- JPH0337768B2 JPH0337768B2 JP58076454A JP7645483A JPH0337768B2 JP H0337768 B2 JPH0337768 B2 JP H0337768B2 JP 58076454 A JP58076454 A JP 58076454A JP 7645483 A JP7645483 A JP 7645483A JP H0337768 B2 JPH0337768 B2 JP H0337768B2
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- Prior art keywords
- potential
- mosfet
- logic
- substrate
- circuit
- Prior art date
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET
- H03K19/0948—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET using CMOS or complementary insulated gate field-effect transistors
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Electronic Switches (AREA)
- Logic Circuits (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体集積回路に係るもので、特
にSOI（Silicon−On−Insulation）構造のCMOS
論理回路に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a semiconductor integrated circuit, and particularly to a CMOS having an SOI (Silicon-On-Insulation) structure.
Regarding logic circuits.
従来のCMOS論理回路、たとえばノア回路は
第１図に示すように構成されている。すなわち、
電源電圧VCCが印加される電源端子１１に、入力
信号Ａで導通制御されるＰチヤネル形の
MOSFET Q1の一端が接続され、この
MOSFETQ1の他端には入力信号Ｂで導通制御さ
れるＰチヤネル形のMOSFET Q2の一端が接続
される。上記MOSFET Q2の他端は、入力信号
Ａ，Ｂで導通制御されるＮチヤネル形の
MOSFET Q3，Q4を並列に介して接地点GNDに
接続される。そしてMOSFET Q2とMOSFET
Q3，Q4との接続点から出力信号＋を得る。
なお、MOSFET Q1，Q2の基板端子は電源端子
１１に、MOSFET Q3，Q4の基板端子に接地点
GNDに接続される。
A conventional CMOS logic circuit, such as a NOR circuit, is configured as shown in FIG. That is,
A P-channel type terminal whose conduction is controlled by the input signal A is connected to the power supply terminal 11 to which the power supply voltage V CC is applied.
One end of MOSFET Q 1 is connected and this
One end of a P-channel type MOSFET Q 2 whose conduction is controlled by input signal B is connected to the other end of MOSFET Q 1 . The other end of MOSFET Q 2 is an N-channel type whose conduction is controlled by input signals A and B.
Connected to ground point GND via MOSFET Q 3 and Q 4 in parallel. And MOSFET Q 2 and MOSFET
Output signal + is obtained from the connection point with Q 3 and Q 4 .
In addition, the board terminals of MOSFET Q 1 and Q 2 are connected to the power supply terminal 11, and the board terminals of MOSFET Q 3 and Q 4 are connected to the ground point.
Connected to GND.
第２図は、上記第１図の回路をSOI構造（たと
えばSOS：Silicon−On−Sapphire）で形成した
場合の回路図を示している。図において、第１図
と同一構成部には同じ符号を付す。図示するよう
に、SOS構造の回路では各MOSFET Q1〜Q4の
基板端子はフローテイング状態となる。 FIG. 2 shows a circuit diagram when the circuit shown in FIG. 1 is formed using an SOI structure (for example, SOS: Silicon-On-Sapphire). In the figure, the same components as in FIG. 1 are given the same reference numerals. As shown in the figure, in the SOS structure circuit, the substrate terminals of each MOSFET Q 1 to Q 4 are in a floating state.
ところで、上記第２図に示したSOS構造の
CMOS論理回路においては、チヤージポンピン
グによつて基板に少数キヤリアが注入され、基板
−ソース間が逆バイアスされるためしきい値電圧
が高くなり、各MOSFETのターンオン時間が長
くなる。このため、動作速度が低下する欠点があ
る。
By the way, the SOS structure shown in Figure 2 above
In a CMOS logic circuit, minority carriers are injected into the substrate by charge pumping, and the substrate-source relationship is reverse biased, which increases the threshold voltage and lengthens the turn-on time of each MOSFET. Therefore, there is a drawback that the operating speed is reduced.
また、基板がフローテイング状態のため、ドレ
イン−基板間の空乏層中で発生した多数キヤリア
が基板中に蓄えられ、基板−ソース間が電源に対
して順方向となり、リーク電流が流れる欠点があ
る。これは主に、トランスフアゲート等を形成し
た場合、そのオフ状態時にソース・ドレイン間の
電位差が大きいと現われ、消費電流の増加をもた
らす。 In addition, since the substrate is in a floating state, many carriers generated in the depletion layer between the drain and the substrate are stored in the substrate, and the direction between the substrate and the source is in the forward direction with respect to the power supply, resulting in the flow of leakage current. . This mainly occurs when a transfer gate or the like is formed and the potential difference between the source and drain is large in the off state, resulting in an increase in current consumption.
この発明は上記のような事情に鑑みてなされた
もので、その目的とするところは、高速動作で低
消費電流なSOI構造のCMOS論理回路を提供する
ことである。
The present invention has been made in view of the above circumstances, and its purpose is to provide a CMOS logic circuit with an SOI structure that operates at high speed and has low current consumption.
すなわち、この発明においては、第１導電形の
MOSFETで構成され第１電位供給源の電位が印
加される第１の論理設定回路、およびこの第１論
理設定回路と相補的に第２導電形のMOSFETに
よつて構成され第２電位供給源の電位が印加され
る第２の論理設定回路を同一の絶縁基板上に有
し、上記第１，第２論理回路の接続点から出力を
得るSOI構造のCMOS論理回路において、前記第
１論理設定回路を構成する各MOSFETの基板端
子と第１電位供給源との間に前記第１，第２の論
理設定回路の接続点の電位で導通制御される第１
導電形のMOSFET（第１の基板電位設定手段）
を接続するとともに、前記第２論理設定回路を構
成する各MOSFETの基板端子と第２電位供給源
との間に前記第１，第２の論理設定回路の接続点
の電位で導通制御される第２導電形のMOSFET
（第２の基板電位設定手段）を接続したものであ
る。
That is, in this invention, the first conductivity type
A first logic setting circuit made up of MOSFETs and to which the potential of the first potential supply source is applied; and a first logic setting circuit made up of MOSFETs of a second conductivity type complementary to the first logic setting circuit, In a CMOS logic circuit having an SOI structure, which has a second logic setting circuit to which a potential is applied on the same insulating substrate and obtains an output from a connection point between the first and second logic circuits, the first logic setting circuit A first circuit whose conduction is controlled by the potential of the connection point of the first and second logic setting circuits between the substrate terminal of each MOSFET constituting the circuit and the first potential supply source.
Conductivity type MOSFET (first substrate potential setting means)
, and conduction is controlled by the potential at the connection point of the first and second logic setting circuits between the substrate terminal of each MOSFET constituting the second logic setting circuit and the second potential supply source. 2 conductivity type MOSFET
(second substrate potential setting means) is connected thereto.
以下、この発明の一実施例について図面を参照
して説明する。第３図において前記第２図と同一
構成部には同じ符号を付す。１２は第１導電形
（Ｐチヤネル形）のMOSFET Q1，Q2から構成さ
れ、第１電位供給源の電位VCCが印加される第１
の論理設定回路、１３は上記第１の論理設定回路
１２と相補的に、第２導電形（Ｎチヤネル形）の
MOSFET Q3，Q4によつて構成され、第２電位
供給源の電位VSSが印加される第２の論理設定回
路で、上記第１，第２の論理設定回路１２，１３
の接続点ａから出力信号＋を得る。Q5は第
１の基板電位設定手段として働くＰチヤネル形の
MOSFETで、第１論理設定回路１２を構成する
各MOSFET Q1，Q2の基板端子SPと電源端子１
１との間に接続され、前記接続点ａの電位で導通
制御される。また、Q6は第２の基板電位設定手
段として働くＮチヤネル形のMOSFETで、第２
論理設定回路１３を構成する各MOSFET Q3，
Q4の基板端子SNと第２電位供給源VSS（接地点）
との間に接続され、前記接続点ａの電位で導通制
御されるようになつている。
An embodiment of the present invention will be described below with reference to the drawings. In FIG. 3, the same components as those in FIG. 2 are given the same reference numerals. Reference numeral 12 is composed of MOSFETs Q 1 and Q 2 of the first conductivity type (P channel type), and the first
The logic setting circuit 13 is a second conductivity type (N channel type) complementary to the first logic setting circuit 12.
A second logic setting circuit configured by MOSFETs Q 3 and Q 4 and to which the potential V SS of the second potential supply source is applied, which is connected to the first and second logic setting circuits 12 and 13.
An output signal + is obtained from connection point a. Q5 is a P-channel type that serves as the first substrate potential setting means.
The substrate terminal SP and power supply terminal 1 of each MOSFET Q 1 and Q 2 that constitute the first logic setting circuit 12 are MOSFETs.
1, and conduction is controlled by the potential of the connection point a. Q6 is an N-channel MOSFET that serves as a second substrate potential setting means.
Each MOSFET Q 3 configuring the logic setting circuit 13,
Q4 board terminal S N and second potential supply source V SS (ground point)
The conduction is controlled by the potential of the connection point a.
上記のような構成において第４図のタイミング
チヤートを参照して動作を説明する。入力信号
Ａ，Ｂが共に“０”レベル（VSSレベル）の時、
出力信号＋は“１”レベル（VCCレベル）で
あるので、MOSFET Q5はオフ状態、Q6はオン
状態である。従つて、第１論理設定回路１２を構
成するMOSFET Q1，Q2の基板端子SPはフロー
テイング状態、第２論理設定回路１３を構成する
MOSFET Q3，Q4の基板端子SNは第２電位供給
源に接続される。次に、入力信号Ａが“０”レベ
ルから“レベルへ変化すると、MOSFET Q1の
ゲート−基板間の容量結合によつて基板端子SPの
電位は「VCC＋ΔVSP」（ΔVSP：Ｐチヤネル形
MOSFETの基板端子の逆バイアス電圧）とな
り、基板電位がVCCより高くなるため、
MOSFET Q1，Q2の基板−ソース間は逆バイア
スされる。従つて、MOSFET Q1，Q2のしきい
値電圧｜VTH1｜、｜VTH2｜が上昇し、この
MOSFET Q1，Q2が高速にターンオフされる。
一方、第２論理設定回路１３を構成する各
MOSFET Q3，Q4の基板端子SNはMOSFET Q6
を介して第２電位供給源VSSに接続されているの
で、MOSFET Q3は第１図の回路における
MOSFET Q3，Q4と同様に高速にターンオンす
る。MOSFET Q1がターンオフし、Q3がターン
オンすることにより、出力信号＋は“０”レ
ベルとなり、MOSFET Q5がオン状態、Q6がオ
フ状態となるので、基板端子SPの電位はVCCに戻
る。次に、入力信号Ａが“１”レベルから“０”
レベルに変化すると、基板端子SPはVCCに固定さ
れており基板端子SNはフローテイング状態であ
るから、MOSFET Q3のゲートと基板間の容量
結合によつて基板端子SNの電位はVSSより低く
（VSS−ΔVSN）なり、MOSFET Q3，Q4の基板−
ソース間は逆バイアスされる。なお、ΔVSNはＮ
チヤネル形MOSFETの基板端子の逆バイアス電
圧である。この時、基板端子SPの電位はVCCのま
まである。従つて、MOSFET Q3，Q4のしきい
値電圧VTH3，VTH4が上昇し、MOSFET Q3は高
速にターンオフする。これによつて接続点ａの電
位はVCCレベルとなり、MOSFET Q5がオフ、Q6
がオンし、基板端子SNは電位VSSに戻る。 The operation of the above configuration will be explained with reference to the timing chart of FIG. When input signals A and B are both “0” level (V SS level),
Since the output signal + is at the "1" level (V CC level), MOSFET Q 5 is in the off state and MOSFET Q 6 is in the on state. Therefore, the substrate terminals S P of MOSFETs Q 1 and Q 2 forming the first logic setting circuit 12 are in a floating state, forming the second logic setting circuit 13.
The substrate terminals S N of MOSFETs Q 3 and Q 4 are connected to the second potential supply source. Next, when the input signal A changes from the " 0 " level to the "level", the potential of the substrate terminal SP becomes "V CC + ΔV SP " (ΔV SP : P channel shape
(reverse bias voltage of the MOSFET substrate terminal), and the substrate potential becomes higher than V CC , so
The substrates and sources of MOSFETs Q 1 and Q 2 are reverse biased. Therefore, the threshold voltages |V TH1 |, |V TH2 | of MOSFETs Q 1 and Q 2 rise, and this
MOSFETs Q 1 and Q 2 are turned off quickly.
On the other hand, each of the components constituting the second logic setting circuit 13
The board terminal S N of MOSFET Q 3 and Q 4 is MOSFET Q 6
MOSFET Q 3 is connected to the second potential supply source V SS through
Turns on quickly like MOSFETs Q 3 and Q 4 . When MOSFET Q 1 turns off and Q 3 turns on, the output signal + goes to “0” level, MOSFET Q 5 turns on and Q 6 turns off, so the potential of the substrate terminal S P becomes V CC Return to Next, input signal A changes from “1” level to “0”
Since the substrate terminal S P is fixed at V CC and the substrate terminal S N is in a floating state, the potential of the substrate terminal S N changes due to capacitive coupling between the gate of MOSFET Q 3 and the substrate. It is lower than V SS (V SS −ΔV SN ), and the substrate of MOSFET Q 3 and Q 4 −
The sources are reverse biased. Note that ΔV SN is N
This is the reverse bias voltage of the substrate terminal of the channel MOSFET. At this time, the potential of the substrate terminal SP remains at V CC . Therefore, the threshold voltages V TH3 and V TH4 of MOSFETs Q 3 and Q 4 rise, and MOSFET Q 3 turns off quickly. As a result, the potential at connection point a becomes V CC level, MOSFET Q 5 turns off, and Q 6
is turned on, and the substrate terminal S N returns to the potential V SS .
上述したように、このような構成によれば、
MOSFETがターンオフする時に基板−ソース間
が逆バイアスされるのでしきい値電圧が高くな
り、ターンオフ時間を短縮でき、高速化を図れ
る。また、SOI構造の従来の回路では、基板が常
にフローテイング状態であり、MOSFETがオフ
状態のとき、基板−ソース間が順方向バイアスと
なるとドレインリークによつてリーク電流が流れ
る。これに対し、上記第３図の回路では、
MOSFETがオフ状態のとき、基板−ソース間が
順方向にバイアスされることはなく、リーク電流
は流れない。 As mentioned above, with this configuration,
When the MOSFET turns off, the substrate and source are reverse biased, which increases the threshold voltage, shortens the turn-off time, and increases speed. Furthermore, in conventional circuits with an SOI structure, the substrate is always in a floating state, and when the MOSFET is off and the substrate-source is forward biased, leakage current flows due to drain leakage. On the other hand, in the circuit shown in Figure 3 above,
When the MOSFET is off, there is no forward bias between the substrate and the source, and no leakage current flows.
第５図は、この発明の他の実施例を示すもの
で、MOSFETのターンオフ時間のみならずター
ンオン時間をも短縮するための回路で、第２の基
板電位設定手段として複数（２個）のＮチヤネル
形MOSFETを設けたものである。１２は入力信
号Ａ〜Ｄが供給されるＰチヤネル形のMOSFET
Q7〜Q10から成る第１論理設定回路、１３は入力
信号Ａ〜Ｄが供給されるＮチヤネル形の
MOSFET Q11〜Q14から成る第２論理設定回路、
Q5は第１の基板電位設定手段として働くＰチヤ
ネルのMOSFET Q15，Q16は第２の基板電位設
定手段として働くＮチヤネル形のMOSFETで、
MOSFET Q15はMOSFET Q12とQ13との接続点
NBとMOSFET Q11，Q12の基板端子SNB間に接続
され、MOSFET Q16はMOSFET Q13，Q14の基
板端子SNDと第２電位供給源VSS間に接続される。
そして、第１，第２論理設定回路１２，１３の接
続点ａから出力信号・・・を得る。 FIG. 5 shows another embodiment of the present invention, which is a circuit for shortening not only the turn-off time but also the turn-on time of a MOSFET, in which a plurality of (two) N It is equipped with a channel type MOSFET. 12 is a P-channel MOSFET to which input signals A to D are supplied.
The first logic setting circuit consists of Q 7 to Q 10 , and 13 is an N-channel type circuit to which input signals A to D are supplied.
a second logic setting circuit consisting of MOSFETs Q 11 to Q 14 ;
Q 5 is a P-channel MOSFET that serves as the first substrate potential setting means; Q 15 and Q 16 are N-channel MOSFETs that serve as the second substrate potential setting means;
MOSFET Q 15 is the connection point between MOSFETs Q 12 and Q 13
MOSFET Q 16 is connected between the substrate terminal S ND of MOSFET Q 13 , Q 14 and the second potential supply source V SS .
Then, an output signal is obtained from the connection point a between the first and second logic setting circuits 12 and 13.
上記のような構成において、第６図のタイミン
グチヤートを参照して動作を説明する。入力信号
Ｂ〜Ｄが“１”レベルで、入力信号Ａが“０”レ
ベルから“１”レベルへ変化すると、MOSFET
Q11〜Q14の直列回路に電流が流れる。この時、
MOSFET Q11のソース側接続点NAの電位は、電
位VSSよりも高くなり、もし、基板端子SNBが第２
電位供給源VSSに接続されていると基板電位がソ
ース電位よりも低くなり、逆バイアス状態とな
り、MOSFET Q11のターンオン時間が長くなる
ので、これを防止するためにMOSFET Q11，
Q12の基板端子SNBをMOSFET Q15を介して接続
点NBに接続することにより、MOSFET Q11の逆
バイアス電圧を低くおさえMOSFET Q11のター
ンオン時間を短縮している。なお、ΔVSNBP，
ΔVSNBN，ΔVSNDNおよびΔVSPDPはそれぞれ基板電
位の変動量を示している。 The operation of the above configuration will be explained with reference to the timing chart of FIG. When input signals B to D are at “1” level and input signal A changes from “0” level to “1” level, MOSFET
Current flows in the series circuit of Q11 to Q14 . At this time,
The potential of the source side connection point N A of MOSFET Q 11 becomes higher than the potential V SS , and if the substrate terminal S NB
If it is connected to the potential supply source V SS , the substrate potential will be lower than the source potential, creating a reverse bias state and prolonging the turn-on time of MOSFET Q 11. To prevent this, MOSFET Q 11 ,
By connecting the substrate terminal S NB of Q 12 to the connection point NB via MOSFET Q 15 , the reverse bias voltage of MOSFET Q 11 is kept low and the turn-on time of MOSFET Q 11 is shortened. Note that ΔV SNBP ,
ΔV SNBN , ΔV SNDN and ΔV SPDP each indicate the amount of variation in substrate potential.
このような構成によれば、チヤージポンピング
による少数キヤリアの基板中への注入を利用して
MOSFETのターンオフ時間を短縮できるととも
に、チヤージポンピングによる少数キヤリアの基
板中への蓄積によるMOSFETのターンオン時間
の増大を防止できる。また、論理設定回路１２，
１３を構成するMOSFETの遮断時に基板端子を
基準となる電位に設定することにより、基板端子
がフローテイング状態で発生するリーク電流も防
止できる。 According to this configuration, injection of minority carriers into the substrate by charge pumping is used to
The turn-off time of the MOSFET can be shortened, and the turn-on time of the MOSFET can be prevented from increasing due to accumulation of minority carriers in the substrate due to charge pumping. Further, the logic setting circuit 12,
By setting the substrate terminal to a reference potential when the MOSFET constituting the MOSFET 13 is cut off, leakage current that occurs when the substrate terminal is in a floating state can also be prevented.
〔発明の効果〕
以上説明したようにこの発明によれば、高速動
作で低消費電流なSOI構造のCMOS論理回路が得
られる。[Effects of the Invention] As described above, according to the present invention, a CMOS logic circuit with an SOI structure that operates at high speed and has low current consumption can be obtained.
第１図および第２図はそれぞれ従来のCMOS
論理回路を説明するための図、第３図はこの発明
の一実施例に係るCMOS論理回路を示す図、第
４図は上記第３図の回路の動作を説明するための
タイミングチヤート、第５図および第６図はそれ
ぞれこの発明の他の実施例を説明するための図で
ある。
１２……第１の論理設定回路、１３……第２の
論理設定回路、Q5……MOSFET（第１の基板電
位設定手段）、Q6……MOSFET（第２の基板電位
設定手段）、VCC……第１電位供給源の電位、VSS
……第２電位供給源の電位。
Figures 1 and 2 are respectively conventional CMOS
3 is a diagram for explaining a logic circuit, FIG. 3 is a diagram showing a CMOS logic circuit according to an embodiment of the present invention, FIG. 4 is a timing chart for explaining the operation of the circuit shown in FIG. 3, and FIG. 6 and 6 are diagrams for explaining other embodiments of the present invention, respectively. 12...First logic setting circuit, 13...Second logic setting circuit, Q5 ...MOSFET (first substrate potential setting means), Q6 ...MOSFET (second substrate potential setting means), V CC ...the potential of the first potential supply source, V SS
...The potential of the second potential supply source.
Claims (1)
供給源の電位が印加される第１の論理設定回路、
およびこの第１論理設定回路と相補的に第２導電
形のMOSFETによつて構成され第２電位供給源
の電位が印加される第２の論理設定回路を同一の
絶縁基板上に有し、上記第１，第２論理設定回路
の接続点から出力を得るSOI構造のCMOS論理回
路において、前記第１論理設定回路を構成する各
MOSFETの基板端子と第１電位供給源との間に
配設され前記第１，第２論理設定回路の接続点の
電位で制御される第１の基板電位設定手段と、前
記第２論理設定回路を構成する各MOSFETの基
板端子と第２の電位供給源との間に配設され前記
第１，第２論理設定回路の接続点の電位で制御さ
れる第２の基板電位設定手段とを具備し、前記第
１，第２基板電位設定手段はそれぞれ前記第１あ
るいは第２論理設定回路の各MOSFETの導通時
は基板端子をフローテイング状態に設定し、各
MOSFETの遮断時は基板端子をそれぞれの論理
設定回路に印加される電位に設定する如く構成し
たことを特徴とするCMOS論理回路。 ２ 前記第１の基板電位設定手段は、第１導電形
のMOSFETから成り、前記第２の基板電位設定
手段は、第２導電形のMOSFETから成ることを
特徴とする特許請求の範囲第１項記載のCMOS
論理回路。 ３ 前記第２の論理設定回路は直列接続された複
数の論理設定用のMOSFETから成り、これら直
列接続されたMOSFETが複数のブロツクに分割
され、前記第２の基板電位設定手段は、前記第２
の論理設定回路の各ブロツクにそれぞれ対応して
設けられ、前記第１，第２論理設定回路の接続点
の電位で導通制御される複数の基板電位設定用の
MOSFETから成り、これら複数の基板電位設定
用のMOSFETはそれぞれ、対応するブロツクの
論理設定用のMOSFETの基板端子とこれら論理
設定用のMOSFETの内で前記第２電位供給源側
に位置するMOSFETのソース間に接続されるこ
とを特徴とする特許請求の範囲第１項記載の
CMOS論理回路。[Claims] 1. A first logic setting circuit configured with a first conductivity type MOSFET and to which a potential of a first potential supply source is applied;
and a second logic setting circuit complementary to the first logic setting circuit, which is constituted by a second conductivity type MOSFET and to which a potential of a second potential supply source is applied, is provided on the same insulating substrate, In a CMOS logic circuit with an SOI structure that obtains an output from a connection point between the first and second logic setting circuits, each
a first substrate potential setting means arranged between a substrate terminal of the MOSFET and a first potential supply source and controlled by a potential at a connection point of the first and second logic setting circuits; and the second logic setting circuit. a second substrate potential setting means disposed between the substrate terminal of each MOSFET constituting the MOSFET and a second potential supply source and controlled by the potential of the connection point of the first and second logic setting circuits. The first and second substrate potential setting means each set the substrate terminal in a floating state when each MOSFET of the first or second logic setting circuit is conductive, and each
A CMOS logic circuit characterized in that, when a MOSFET is cut off, a substrate terminal is set to a potential applied to each logic setting circuit. 2. Claim 1, wherein the first substrate potential setting means comprises a MOSFET of a first conductivity type, and the second substrate potential setting means comprises a MOSFET of a second conductivity type. CMOS listed
logic circuit. 3. The second logic setting circuit consists of a plurality of MOSFETs for logic setting connected in series, these MOSFETs connected in series are divided into a plurality of blocks, and the second substrate potential setting means
A plurality of substrate potential setting circuits are provided corresponding to each block of the logic setting circuit, and conduction is controlled by the potential of the connection point of the first and second logic setting circuits.
Each of these MOSFETs for setting the substrate potential has a substrate terminal of the MOSFET for setting the logic of the corresponding block, and a terminal of the MOSFET located on the second potential supply source side among these MOSFETs for logic setting. According to claim 1, the device is connected between sources.
CMOS logic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58076454A JPS59201526A (en) | 1983-04-30 | 1983-04-30 | Cmos logical circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58076454A JPS59201526A (en) | 1983-04-30 | 1983-04-30 | Cmos logical circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59201526A JPS59201526A (en) | 1984-11-15 |
| JPH0337768B2 true JPH0337768B2 (en) | 1991-06-06 |
Family
ID=13605593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58076454A Granted JPS59201526A (en) | 1983-04-30 | 1983-04-30 | Cmos logical circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59201526A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4439031B2 (en) | 1999-04-15 | 2010-03-24 | 株式会社ルネサステクノロジ | Semiconductor device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5929025B2 (en) * | 1975-12-08 | 1984-07-17 | ソニー株式会社 | TV synopsis Oyobi Kirokusouchi |
-
1983
- 1983-04-30 JP JP58076454A patent/JPS59201526A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59201526A (en) | 1984-11-15 |
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