JPH0337892A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent wasteful power consumption by adjusting the boost level of a signal line by detecting a source voltage and controlling a capacitor circuit. CONSTITUTION:A reference voltage Vref is compared with the source voltage Vo at a power source level detection circuit 3, and when the fact that the voltage Vo is higher than the Vref is detected, the capacitor circuit 4 which outputs a boost voltage VB is controlled with the detection output D of the circuit 3. Then, the voltage VC of the signal line connected to the gate of a transistor Q in the memory cell of a memory cell array 1 is adjusted to a low level via a level setting circuit 2, which prevents a power consumed wastefully and improves reliability for a semiconductor memory device.

Description

[Detailed Description of the Invention] [Summary] A semiconductor memory device, especially an MO used for a cell array.
S) Regarding technology for limiting the voltage level of signal lines connected to the gates of transistors (MIS) transistors, this technology limits the boost level of the signal lines, eliminates excess power consumption, and improves operational reliability. A level setting circuit that sets the voltage level of the signal line connected to the gate of the MIS transistor used in the cell array to a level corresponding to the size of the boost voltage, and a level setting circuit that sets the power supply voltage to a predetermined reference level. a power supply level detection circuit that outputs a detection signal when the level of the power supply voltage exceeds the reference level; and a capacitor circuit that includes a plurality of capacitors and outputs the boost voltage based on the capacitance of the capacitors. and the capacitor circuit adjusts the capacitance of the capacitor in response to the detection signal. configured to reduce pressure.

[Industrial application field]

The present invention relates to semiconductor memory devices, and in particular to the voltage of signal lines connected to the gates of metal-oxide-semiconductor (MOS) transistors used in cell arrays, and more broadly metal-insulator-semiconductor (MIS) transistors. Φ regarding techniques that limit the level.

In recent years, as semiconductor memory devices have become faster, the channel length of transistors has been shortened and gate oxide films have been made thinner. However, as the gate oxide film becomes thinner, a problem arises in that the withstand voltage of the oxide film decreases accordingly. In particular, since a signal boosted to a high voltage is input to the gate of the transistor via the I≧ line (word line), the breakdown voltage of the gate oxide film of the transistor is a problem. Therefore, there is a need to limit the boost level of the signal line to a predetermined level, thereby preventing the gate oxide film from becoming an F film and thereby reducing the breakdown voltage of the oxide film.

[Conventional technology]

FIG. 8 shows a circuit configuration of a semiconductor memory device as an example of a conventional type.

In the figure, 10 is a memory cell array in which dynamic cells are arranged in a matrix; 5 is a row decoder that selects a word line in response to an address signal ADD;
6 is a column decoder that selects a bit line in response to the address signal ADD; 7 is a multiplexer and sense amplifier (S/Δ) circuit that activates the selected bit line and amplifies the level of the signal on the bit line; 8 is a 30 is a boost capacitor circuit that generates a boost voltage φb in response to a control signal φa; 40 is a boost circuit that generates a boost output φC based on the boost voltage φb; Reference numeral 9 indicates a boost level clamp circuit that clamps the boost output φC to a predetermined level.

The circuit configuration in FIG. 8 includes word lines WL+, WLj,...
This shows the case where the voltage level of ... is boosted, and the transfer gate transistor Q of a dynamic cell is boosted.
In order to reduce the voltage applied to the gate oxide film of the boost output φC, the level of the boost output φC is clamped to Vcc+3Vth. Here, vth represents the threshold level of the transistor Ql-03 constituting the clamp circuit 9.

FIG. 9(a) shows how the boost output φC changes in a steady state with respect to the change in the power supply voltage Vcc.

In this example, the size of the boost capacitor 35 is set so that the boost level is five times Vccxl. Assuming that there is no boost level clamp circuit 9 in FIG. 8, the boost output will be φC=φ,
If VCC = 7 V, φ = 7VXl, 5 times =
It becomes 10.5V. On the other hand, when there is a clamp circuit 9 as illustrated in FIG. 8, the boost output φC is (V
cc+3Vth), so Vc
When c=7V, it becomes φCξ9v, and the clamp circuit 9
10.5V - 9V = 1.5V (7
) improved tonal.

Figure 9(b) shows each signal voltage φ when Vcc=7V.
The waveforms of a, φb and φC are shown.

As shown in the figure, the boost output φC is temporarily boosted by φk to 7V x 1.5 times = IO, 5V due to the shortage of g due to the series connection of transistors 01 to Q3, and then the transistor 01 It is pulled by ~Q3 and clamped to the level of (Vcc+3Vth).

[Problem to be solved by the invention]

According to the conventional method described above, the clamp level is a level higher than the power supply voltage Vcc (Vcc + 3Vth).
Therefore, a correspondingly high voltage is applied to the gate oxide film of the memory cell transistor. This is undesirable because it goes against the problem of thinning the gate oxide film, that is, lowering the withstand voltage.

In addition, when the boost level clamp circuit 9 clamps the output φC of the boost circuit 40 to the level of νcc+3Vth, the boost level is temporarily reduced to the clamp level (Vcc knee 3νtit) due to the insufficient gs amount of the transistors 01 to Q3. (See Figure 9(b)). This causes the inconvenience that power is consumed unnecessarily.

Furthermore, since the clamping transistors 01 to 03 act as a load when viewed from the boost circuit 40, there arises a problem that the boost output φC does not quickly rise to a predetermined level and the rising waveform becomes dull. This leads to, for example, cell selection not being performed properly when reading or writing data, which is not desirable from the viewpoint of operational reliability as a memory.

The present invention was created in view of the above-mentioned problems in the prior art, and it limits the boost level of the signal line connected to the gate of the MTS transistor, eliminates unnecessary power consumption, and improves operational reliability. It is an object of the present invention to provide a semiconductor memory device that can be improved.

[Means to solve the problem]

As shown in the principle block diagram of FIG.
A level setting circuit 2 that sets the voltage level VC of the signal line connected to the gate of the Ranjisk Q to a level corresponding to the magnitude of the boost voltage VB, and a power supply voltage V. a power supply level detection circuit 3 which compares the power supply voltage with a predetermined reference level Vref and outputs a detection signal when the level of the power supply voltage exceeds the reference level; and a plurality of capacitors; Said boost 41! The capacitor circuit 4 outputs a voltage, and the capacitor circuit adjusts the capacitance of the capacitor in response to the detection signal to reduce the boost voltage.

[For production]

According to the above-described configuration, when the power supply voltage reaches the reference level voltage or higher, the output of the power supply level detection circuit causes the
The capacitor circuit 4 adjusts the capacitance of a plurality of capacitors to reduce the magnitude of the boost voltage. Therefore, due to this reduction in the boost factor, the magnitude of the voltage level VC of the signal applied to the gate of the MTS transistor Q is also reduced to a corresponding level. This makes it possible to reduce the thickness of the gate oxide film of the MIS transistor and to cope with the reduction in breakdown voltage of the oxide film.

Furthermore, since the boost level of the signal line is limited to a low level by adjusting the capacitance of the capacitor, the boost level will not rise above this limited level unless the power supply voltage fluctuates. Therefore, it is possible to reduce power consumption compared to the conventional example.

Furthermore, since there is no extra load such as a boost level clamp circuit as seen in the conventional type, the boost voltage on the signal line can rise sharply. This contributes to the reliability of operation as a memory.

Note that other structural features and details of the operation of the present invention will be explained using the embodiments described below with reference to the accompanying drawings.

〔Example〕

FIG. 2 shows a circuit configuration of a semiconductor memory device as an embodiment of the present invention. Note that in the following description, unless otherwise specified, the term "transistor" refers to an n-channel transistor.

In the figure, numeral 10 indicates a memory cell array, which includes a plurality of word lines WL, 1IILj, . . . and bit lines BLt, BLi.

. . . are arranged in a matrix, and one transistor (Q) and one capacitor (C) type dynamic cell is provided at each intersection using a folded bit line method. A row decoder 5 has a function of selecting one of a plurality of word lines in response to, for example, a plurality of upper bits of an address signal ADD. It has a function of selecting one of a plurality of bit lines in response to a signal of a plurality of lower bits of ADD. Further, 7 indicates a multiplexer and sense amplifier (S/A) circuit, and column decoder 6
It has a function of activating the bit line selected by the bit line and amplifying the level of the signal on the bit line. 8 is a data input/output (Ilo) buffer, which transfers input/output data D□1 between the multiplexer and S/A circuit 7 and the outside.
This is for buffering 1/DOUT.

20 indicates a power level detection circuit. Resistor ■1 and four p-channel transistors 12 to 15 are connected between the high potential power line Vcc and the low potential power line Vss (OV).
are connected in series, and the gate of each transistor is connected to the drain. The source potential of transistor 12 defines reference voltage Vref. Letting each threshold level of transistors 12 to 15 be vth, the reference voltage Vref is expressed as 4Vth. Similarly, resistors 26 and 27 are connected in series between the power supply line CC and the power supply line Vss, and the potential at the connection point of the resistors is the voltage V. stipulates.

In addition, the p-channel transistor 21 and the transistor 23
, the p-channel transistor 22 and the transistor 24 are connected in series, the sources of the transistors 21 and 22 are connected to the power supply line Vcc, and the sources of the transistors 23 and 24 are connected to the power supply line Vss via the transistor 25. has been done.

The gate of transistor 22 is connected to its drain as well as to the gate of transistor 21.

A voltage V is applied to the gates of transistors 23 and 24, respectively. , the reference voltage Vref is applied, and the transistor 25
Power supply voltage Vcc is applied to the gate of . A detection signal φd is taken out from the drain of the transistor 23.

In the power level detection circuit 20, the transistor 25 constitutes a constant current source, and the transistors 21, 23 and 22
．． 24 constitutes a current switching type switch. Therefore, the voltage V. When the level of Vref is lower than the level of the reference voltage Vref, the transistor 24 is on and the transistor 23 is off, and the drain potential of the transistor 23 (detection signal φd) is at the "H" level. , voltage V. exceeds the level of reference voltage Vref, transistor 23 is turned on, transistor 24 is turned off, and the level of detection signal φd becomes L''.
be lowered to the level.

30 indicates a boost capacitor circuit, and the detection signal φd
an inverter 31 that responds to the input voltage, a NOR gate 32 that responds to the control signal φa generated internally based on the address change and the output of the impark 31, an inverter 33 that responds to the control signal φa, and a drain connected to the power supply line CC. M connected between the source of the transistor 34 and the output terminal of the inverter 33
A MO connected between the OS capacitor 35 and the source of the transistor 34 and the output terminal of the NOR gate 32
It is composed of an S capacitor 36. capacitor 3
A boost voltage φb is taken out from the ends of transistors 5 and 36 (sources of transistors 34).

The capacitor circuit 30 has a function of changing the magnitude of the boost voltage φb according to the level of the detection signal φd.

That is, when the detection signal φd is at the "H" level, the output of the inverter 31 is at the "L" level, and the NOR gate 3
2 functions as an inverter. In this state, when the control signal φa is changed from the "H" level to the "'L" level,
The level at the other end of the capacitors 35 and 35 (the output end of the inverter 33 and the NOR gate 32 output it) is “
The level of the boost voltage φb changes from low to high. As a result, the level of the boost voltage φb is boosted to a level corresponding to the capacitance of both capacitors.

On the other hand, when the detection signal φd is at the pass''' level, the output of the inverter 31 becomes the IIH'' level, and the level at the other end of the capacitor 36 (the output end of the NOR gate 32) is "IIH" level.
It is fixed at the "L" level. In other words, it is not affected by the level change of the control signal φa. Therefore, when the control signal φa is changed from the rr Hu level to the "L" level in this state, only the capacitor 35 becomes effective. boost voltage φ
The level of b also corresponds to the capacitance of the capacitor 35. If the capacitances of the capacitors 35 and 36 are the same, this boost level will be 1/2 of the boost level when the detection signal φd is at the "H" level.

40 indicates a boost circuit. Transistors 42 and 43 are connected in series between the power line Vcc and the power line Vss, and the gate of the transistor 42 is connected to the capacitor circuit 30.
The gate of the transistor 43 is connected to the node N1 through the inverter 41 in the opposite direction.

The connection point of transistors 42 and 43 is assumed to be node N2.

Similarly, transistors 44 and 45 are connected in series between the power supply line Vcc and the power supply line VssO, and the gate of the transistor 44 is connected to the output terminal of the inverter 41.
The gate of transistor 45 is connected to node N2. The connection point of transistors 44 and 45 is designated as node N3.

Transistors 46 and 47 are connected in series between power supply line Vcc and node N3, the gate of transistor 46 is connected to the output terminal of inverter 41, and the gate of transistor 47 is connected to node N1.

The connection point of transistors 46 and 47 is designated as node N4.

A transistor 48 is connected between the node N1 and the power supply line Vss.
and 49 are connected in series, the gate of transistor 48 is connected to node N4, and the gate of transistor 49 is connected to the output terminal of impark 41.

The connection point of transistors 48 and 49 is designated as node N5.

Further, between the source of the transistor 34 in the capacitor circuit 30 and the power supply line Vss, transistors 51 and 5 are connected.
2. Transistors 53 and 54 are connected in series, each gate of transistor 51.53 is connected to node N5, and each gate of transistor 52.54 is connected to node N5.
Connected to 3. The connection point of transistors 51 and 52 is designated as node N6. There is a MOS between nodes N5 and N6.
A capacitor 50 is connected.

Boost output φC from the connection point of transistors 53 and 54
is taken out, and this boost output φC is sent to the row decoder 5
The selected word line is supplied to the selected word line.

FIG. 3 shows signal waveforms at various parts of the boost circuit 40. To simplify the explanation, it is assumed that only the capacitor 35 contributes to the boost voltage φb.

When the control signal φa is at the "H" level, the node N1 becomes the 11 L1 level via the inverter 33, and the output terminal of the inverter 41 becomes the "H" level, so that the transistors 43, 49 are turned on, and the node N2. N5 is set to high level. When transistors 44 and 46 are turned on, nodes N3 and N4 are set to "H" level. Node N
3 becomes "H" level, the transistor 50
．． 54 is turned on, and node N6 and boost output φC become "L" level. Further, due to the transistor 34 being turned on, the boost voltage φb is at the "H1+ level".

In this state, a voltage φb is applied to both ends of the capacitor 35.

In this state, when the control signal φa falls to the "L11 level", the level at the output end of the inverter 33 (the end of the capacitor 35) changes to the "H" level, and this change causes the level at the other end of the capacitor (boost voltage φb side) and raises the level of boost voltage φb. Further, the node N1 changes to the ``H1l level'' through the inverter 33, and the level of the output end of the inverter 41 changes to the IIL1 level.
The potential at 5 begins to rise towards the rr Hn level.

Further, when the transistor 42 is turned on, the potential of the node N2 becomes the "H" level, and when the transistor 45 is turned on, the potential of the node N3 falls to the L" level.

The level of the node N4 rises once due to the rise in the potential of the node N1, but then falls to the II L II level as the transistor 47 is turned on. The potential of node N3 is 111. ” level, the transistor 52.5
4 is turned off, the potential between the nodes and the boost output φC
begins to rise toward the "H11" level. Also, when the potential of the node N4 reaches the "L" level, the transistor 48
is cut off, and the potential of node N5 further increases due to the action of capacitor 50. In this case, the potential of node N6 and boost output φC rise to a level defined by boost voltage φb.

As mentioned above, the magnitude of the boost voltage φb changes depending on the level of the detection signal φd, so in that case, the potential of the node N6 and the level of the boost output φC will of course also increase or decrease according to the change. It is.

In the embodiment described above, each threshold level V th of the p-channel transistors 12 to 15 in the power level detection circuit 20 is set to -1, Ov, and the resistors 26, 27
If the resistance ratio is 1:4, the reference voltage Vref is 4ν
, voltage V. becomes 415 Vccm. Therefore, the detection signal φd goes "L" when the power supply voltage Vcc exceeds 5ν.
The level changes (see Figure 4(a)). At this time, as described above, the level at the other end of the capacitor 36 (the output end of the NOR gate 32) is fixed at the "L" level, and is not affected by the level change of the control signal φa. Therefore, even if the control signal φa is changed from the "H" level to the "B" level in this state, only the capacitor 35 contributes to the magnitude of the boost voltage φb, so as shown in FIG. 4(a).
The boost rate of the boost output φC is reduced as shown in FIG. In the illustrated example, the boost rate decreases to approximately 1.5 times - 1.2 times when Vcc = 5V.

This reduction in boost rate causes Mis) in the cell array to
The magnitude of the voltage level of the signal applied to the gate of transistor Q is also reduced to a corresponding level. by this,
It is possible to cope with a decrease in breakdown voltage of the gate oxide film of the transistor.

In addition, the level of boost output φC is limited by adjusting the capacitance of capacitors 35 and 36, so the conventional type (
Compared to the present embodiment (see FIG. 4(b)), the voltage can be limited to a lower level by 1.2 times -8,4V+. Therefore, if the power supply voltage Vcc does not fluctuate, the boost level will be at this limited level (8,
It does not rise above 4V). Therefore, it is possible to reduce power consumption compared to the conventional type.

Furthermore, since there is no extra load such as a ramp circuit as seen in the conventional type at the next stage of the boost circuit 40, the boost output φC quickly rises to a predetermined level, solving the problem that the rising waveform becomes dull. I can do it. As a result, cell selection is performed appropriately, and the operational reliability of the memory is increased.

FIG. 5 shows a circuit configuration according to another embodiment.

The feature of this embodiment is that the voltage V is based on the power supply voltage Vcc.
. with two different reference voltages Vref1. Vref2
compared to the voltage ν. When the voltage exceeds the level of each reference voltage, a detection signal φd1φe of "H1+ level" is outputted, thereby adjusting the capacitance of the capacitor in two stages.

Therefore, in the power level detection circuit 20a, the p-channel transistors 21a, 22a and the transistor 23 constituting the current switching type switch and the constant current source.
a, 24a, 25a, and the second reference voltage Vref2
resistor 11a and five p-channel transistors 12a, 13a, 14a, 15a,
16a is added. Transistor 12a~
Letting each threshold level of 16a be νth,
The reference voltage Vref2 is expressed as 5Vth. Further, the detection signal φe is taken out from the drain of the transistor 23a. On the other hand, in the boost capacitor circuit 30a, an inverter 31a responsive to the detection signal φe;
A NOR gate 32a responsive to the output of the inverter and control signal φa, and a MOS capacitor 36a connected between the source of transistor 34 and the output terminal of NOR gate 32a are added.

The structure and operation of other circuits are the same as in the embodiment shown in FIG. 2, and therefore their explanation will be omitted.

According to the configuration of this embodiment, when the power supply voltage Vcc is lower than 5V, the detection signals φd and φe are both at the "H" level, so the capacitors 35, 36, and 36a all contribute to the magnitude of the boost voltage φb. are doing. When the power supply voltage Vcc rises and exceeds 5V, the detection signal φd changes to the "L" level (see FIG. 6). As a result, the level at the other end of the capacitor 36 (output end of the NOR gate 32) is “
The capacitors 35 and 36 are fixed at L'' level and are not affected by level changes of the control signal φa.
Only a is related to the magnitude of boost voltage φb. When the power supply voltage Vcc further increases and exceeds about 6V, the detection signal φe also changes to the "L" level. As a result, the level at the other end of the capacitor 36a (the output end of the NOR game 32a) is no longer affected by the level change of the control signal φa.
As a result, only the capacitor 35 is related to the magnitude of the boost voltage φb. In other words, the boost rate of the boost output φC is reduced in two stages. In the example shown, beam CC=5
At the time of VO, the boost rate decreases from about 1.5 times to 1.2 times, and further decreases from 1.2 times to 1 time at Vccξ6v.

In each of the embodiments described above, the boost output φC of the boost circuit 40 is configured to be supplied to the selected word line via the row decoder 5, but the destination of this boost output φC is not limited to the word line.

For example, as shown in a modified example in FIG.
It may be input to each gate of j. In this configuration, "H'" to be supplied from the S/A circuit 7 to the cell
Level voltage compensation can be performed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to limit the booth level of the signal line connected to the gate of the MIS transistor used in the cell array. As a result, the voltage applied to the gate oxide film of the transistor can be reduced, making it possible to reduce the thickness of the gate oxide film and, in turn, cope with a reduction in the withstand voltage of the oxide film. Moreover, it greatly contributes to eliminating unnecessary power consumption and increasing the operational reliability of the entire device.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a semiconductor memory device according to the present invention, FIG. 2 is a circuit diagram showing the configuration of a semiconductor memory device as an embodiment of the present invention, and FIG. 3 is a diagram showing various parts of the boost circuit in FIG. Signal waveform diagrams, Figures 4(a) and (b) are diagrams showing the relationship between the power supply voltage and each signal voltage in the embodiment in Figure 2, and Figure 5 is a circuit diagram showing the configuration of another embodiment of the present invention. , FIG. 6 is a diagram showing the relationship between the power supply voltage and each signal voltage in the embodiment shown in FIG. 5, FIG. 7 is a circuit diagram showing the configuration of the main part in still another embodiment of the present invention, and FIG. FIGS. 9(a) and 9(b) are diagrams showing the relationship between the power supply voltage and each signal voltage in the circuit of FIG. 8. FIGS. (Explanation of symbols) 1...Cell array, 2...Level setting circuit, 3...
・Power level detection circuit, 4... Capacitor circuit, Q・
・・MIS transistor, vo・power supply voltage, VB・
...Boost voltage, VC...Voltage level of signal line, V
ref...Reference level, D...Detection signal. N! of the semiconductor memory device according to the present invention! ! Block diagram Figure Other 5 of the present invention! Figure 5 shows the configuration of the embodiment. Figure 5 shows the relationship between the power supply voltage and each signal voltage. Figure 6 shows the relationship between the power supply voltage and each signal voltage. Power supply voltage Vcc (V) (a) Figure 8 Circuit 1 When Vcc = 7 V (b) '3 (7) Figure 9 shows the relationship between the power supply voltage and each signal voltage.

Claims (1)

[Claims] 1. Voltage level (VC) of the signal line connected to the gate of the MIS transistor (Q) used in the cell array (1)
) to a level corresponding to the magnitude of the boost voltage (VB), and a level setting circuit (2) that compares the power supply voltage (V_0) with a predetermined reference level (Vref), and sets the level of the power supply voltage to a level corresponding to the reference level. Power level detection circuit (3) that outputs a detection signal (D) when the level is exceeded
and a capacitor circuit (4) having a plurality of capacitors and outputting the boost voltage based on the capacitance of the capacitor, the capacitor circuit adjusting the capacitance of the capacitor in response to the detection signal. A semiconductor memory device characterized in that the boost voltage is reduced. 2. The power supply level detection circuit is characterized in that it compares the power supply voltage with a plurality of different reference levels (Vref_1, Vref_2), and outputs a detection signal when the level of the power supply voltage exceeds each reference level. Semiconductor memory device.