JPH0338022A - Manufacture of semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a method for manufacturing a semiconductor device, and the purpose is to provide a method for manufacturing a semiconductor device that allows mass exposure without requiring a mask alignment pattern. A mold region or a carrier concentration varying region having a carrier concentration different from that of the substrate is provided, and an electrode is provided on the side surface of the substrate, and electromagnetic waves are scanned along the X and Y directions from the top of the substrate or the bottom of the substrate. irradiate the substrate, measure the potential within the substrate due to the irradiation of the electromagnetic wave between the electric fence, and measure the P-N of the boundary position between the opposite conductivity type regions of the substrate and the substrate.
By measuring the potential fluctuation within the substrate due to the internal electric field generated at the junction or the boundary position between the substrate and the carrier concentration fluctuation region, the position where the internal electric field is generated within the substrate is detected and the P- Detecting the position of the N junction or the boundary position between the substrate and the carrier concentration fluctuation region, and detecting the position of the boundary between the P-N junction and the substrate and the carrier concentration fluctuation region, It is configured by performing exposure to the applied resist film or positioning for ion implantation into the semiconductor substrate.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device.

In the manufacture of semiconductor devices such as ICs and LSIs, for example, a silicon dioxide film (Si
ng), the 5jOJl is opened in a predetermined pattern, and impurity atoms of a conductivity type opposite to that of the substrate are introduced through the opening by a method such as ion implantation to form a PN junction to form a semiconductor device. is forming.

[Conventional technology]

Conventionally, as a method for forming an opening in such an S30g film, a SiO□ film is formed on a Si substrate by thermal oxidation of the substrate, a resist film is applied on the substrate, and a predetermined portion is opened from above the substrate. A photomask with openings is installed, and light such as ultraviolet rays is irradiated from above the photomask to expose the resist film in a predetermined pattern. For example, unexposed areas are removed to form a resist film with openings in a predetermined pattern. do.

Next, using this resist film as a mask, the SiO□ film is opened in a predetermined pattern by ethoching.

[Problem to be solved by the invention]

In the conventional method, a mark corresponding to the cross-shaped reference alignment mark of the photomask is etched into the Si substrate in advance in the form of a recess. Then, a 5i(h film is formed on this substrate, and the Si
The mark carved into the substrate forms a recessed region in the SiO□ film formed on the substrate, and the photomask is aligned by aligning the reference alignment mark of the photomask with this recessed region.

However, when a resist film is applied to a predetermined thickness on 5iOJ51, the resist film is often colored, and it is difficult to detect the concave areas of the SiO□ film from above the resist film using a mirror. This was difficult and caused problems in fitting masks.

Furthermore, if the method of forming the above-mentioned alignment marks on the Si substrate is adopted, the semiconductor element forming area is narrowed by the area where the alignment marks are formed, so there is a problem that the degree of integration of the formed semiconductor device is reduced. .

Further, there is a problem in that distortion occurs in the Si substrate during the thermal oxidation step when forming the 5i02 film on the Si substrate, and the accuracy of the alignment marks formed on the Si substrate decreases.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a method for manufacturing a semiconductor device in which exposure positions can be easily aligned with high precision without using alignment marks.

[Means to solve the problem]

As shown in the principle diagram of FIG. 1, the method for manufacturing a semiconductor device of the present invention includes providing a semiconductor substrate 1 with a region 2 of the opposite conductivity type of the substrate, or a carrier concentration varying region 3 having a carrier concentration different from that of the substrate. An electrode 4 is provided on the side surface of the substrate, and electromagnetic waves are irradiated while scanning along the X and Y directions from the top of the substrate or the bottom of the substrate, and the potential within the substrate due to the irradiation of the electromagnetic waves is changed between the electrodes. P-N at the boundary position between the substrate and the opposite conductivity type region 2 of the substrate.
The generation of an internal electric field within the substrate is measured by measuring the potential fluctuation within the substrate 1 due to the internal electric field generated at the junctions 2A, 2B or at the boundary positions 3A, 3B between the substrate and the carrier concentration variation region 3. detecting the positions of the P-N junctions 2A, 2B, or the boundary positions 3A, 3B between the substrate 1 and the carrier concentration variation region 3; Based on the detection information of the boundary positions 3A and 311 of the carrier concentration variation region 3, exposure of the resist film coated on the semiconductor substrate or positioning of ion implantation into the semiconductor substrate is performed.

[For production]

As shown in the principle diagram in Fig. 1 and in Fig. 2, which is a cross-sectional view taken along the line 1-1' in Fig. 1, for example, N-type impurity atoms are ion-implanted into a P-type Si substrate l. A region 2 or a P'' region 3 into which P-type impurities are introduced at a higher concentration than the substrate is formed, and the Si substrate 1 is irradiated with an electron beam while scanning in the X direction and the Y direction.

As shown in the figure, when the surface of the St substrate l is irradiated with an electron beam while scanning along the X and Y directions, pairs of electrons and holes are generated at the P-N junction 2A at one end of the N-type region 2. However, these electrons pass through the N-type region 2 in the direction indicated by the arrow, and form a P-N junction 2B at the other end of the N-type region 2.
It is released onto the Si substrate 1 of the mold.

Therefore, as shown in the potential distribution diagram generated between the electrodes 4 provided at the side ends of the base film when the electron beam is scanned as shown in FIG. 3, an internal electric field is generated at the P-N junction. At 2A, holes become excessive, and a medium potential peak value of 11A occurs in the potential distribution curve 11.

The P-N junction 2B at the other end of the N-type region 2 in the X direction, where an internal electric field is generated, becomes electron-excessive due to the emitted electrons, and that part is at one potential in the potential distribution curve 11. A peak value of 11B occurs.

Further, at the boundary value 13A between the P″ region 3 and the substrate shown in FIG. 2, electron and hole pairs are generated, and the holes among these are p 6 ?
They pass through the I region 3 and are emitted to the substrate at another boundary position 3B of the P'' region 3. Therefore, at the boundary position 3A where the internal electric field of the P1 region 3 is generated, there are excess electrons, so that the potential distribution curve 12 As shown, a peak value of 12^ for one potential occurs, and P
At another boundary position 3B where the internal electric field of region 3 is generated, there is an excess of holes due to the emitted holes, and that part produces a medium potential peak value 12B in the potential distribution curve 12.

In this way, the P-N junctions 2A, 2B or the boundary positions 3A, 3 where the carrier concentration changes with respect to the substrate.
Since the peak value of the potential distribution value appears at point B, by detecting the location where this peak value occurs, the P-N junction 2A
, 2B, or the boundary positions 3A and 3B where the carrier concentration has changed can be detected.

Furthermore, when the output signal of the potential distribution generated in this way is processed by an image processing circuit as a binary signal of white and black and displayed on a CRT screen, the P area and the N area are displayed with good contrast, and the inside of the semiconductor substrate is The formed PN junction is visualized on the CR'r' screen.

Then, a resist film is applied to the Si substrate in advance, and based on the positional information in the substrate of the detected P-N junctions 2A and 2B and the boundary positions 3A and 3B between the substrate and regions with different carrier concentrations. By operating an electron beam exposure device or the like at a certain temperature, a predetermined position of the substrate can be exposed.

Further, by combining the method of the present invention with a focused ion beam implantation device, it becomes possible to implant ions into a predetermined position on a substrate.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 4 is an explanatory diagram of an embodiment of the method of the present invention.

As shown in the figure, an electron beam 24 emitted from an electron gun 23 consisting of a cathode 21 and an anode 22 is condensed by a condensing lens 25, and a scanning signal from a scanning circuit 26 moves a scanning lens 27 to a predetermined position and a predetermined position. By scanning with a pinch, the electron beam is applied to, for example, a P-type Si substrate, Xl, X! +X3... scan along the direction. Electrodes 4 formed on both ends of the Si-based Fi,l detect the potential generated within the substrate by scanning the electron beam, and the detected output potential signal is amplified by the amplifier 28. And P-N in FIG.
The peak values of the potentials generated at the junctions 2A, 2B and the boundary positions 3A, 3B between the substrate and the carrier concentration fluctuation region 3 are detected, and the detected voltage signals are synchronized with the synchronization signal sent from the scanning circuit 26. The image processing circuit 29 converts the signal into an image signal and displays it on the display screen of the CRTa2.

When the signal is processed by the image processing circuit so that the child signal of the output potential signal becomes black, the - signal becomes white, or vice versa, the N-type area 32, the P-wall area 33, and the P- The position of the N junction is displayed on the display screen with good contrast.

As described above, the method of the present invention makes it possible to detect patterns in transparent conductor regions and high concentration regions formed on a semiconductor substrate without using alignment marks.
Based on this pattern data, an exposure device is operated to perform exposure with high precision.

Further, when ions are implanted using a focused ion beam irradiation device based on the above pattern data, ions can be implanted into a predetermined region of the semiconductor substrate with high precision.

In addition, although an electron beam was used as the electromagnetic wave in this example,
Instead of the electron beam, electromagnetic waves such as laser light, infrared light, visible light, and X-rays may be used in the form of a beam.

In addition to the P-N junction region and the P"P region formed in the Si substrate shown in this example as the generation region of the internal electric field of the semiconductor substrate, the boundary position of the P-P region, the N"NN region-Njff region However, a similar phenomenon occurs, and in addition to Si substrates, in the case of semiconductor devices with MIS structure, the energy band bends on the semiconductor substrate surface at the interface between the semiconductor substrate and the insulating film region, generating an internal electric field. Also, when the electromagnetic waves described above are irradiated at a hetero interface in a semiconductor device having a hetero structure, a phenomenon similar to that in the above-described embodiment occurs.

[Effects of the Invention] As is clear from the above description, according to the present invention, the position of a pattern to be exposed on a semiconductor substrate can be detected with high precision without using alignment marks, and the resist film can be coated on the substrate. Since the size and position of the pattern can be detected with high precision even when When used in the manufacturing process of semiconductor devices, it has the effect of enabling highly accurate exposure and ion implantation.

[Brief explanation of drawings]

Figure 1 is a diagram of the principle of the method of the present invention, Figure 2 is a cross-sectional view taken along line 1-1' in Figure 1, and Figure 3 is the voltage when scanning the electron beam in the method of the present invention. Output Diagram, FIG. 4 shows an explanatory diagram of an embodiment of the method of the present invention. In the figure, 1 is a semiconductor substrate (P-type Si substrate), 2 is an opposite conductivity type region (
2A, 2B are the P-N junctions, 3 is the carrier concentration fluctuation region (P" region), 3A, 3B are the boundary positions, 4 is the electrode, 11.12 is the potential distribution 1iII line, IIA
, 118.12A. 12B is the peak value, 21 is the cathode, 22 is the anode,
23 is an electron gun, 24 is an electron beam, 25 is a condensing lens,
26 is a scanning circuit, 27 is a scanning lens, 28 is an amplifier, 2
9 is an image processing circuit, 31 is a CRT, 32 is an N-type area, and 33 is a P-type head area. Oh history gl! / 1 direction 9 Kuribo 1st drawing 1 period ^ 14' Kayari Houshun's 2nd drawing I → Zahi IR (+ direction) Husband; γ all 1st d) Bee 4 Turtle 1
1 Otto - 4h Motga m Figure 3 Figure

Claims (1)

[Claims] A semiconductor substrate (1) is provided with a region (2) of the opposite conductivity type of the substrate or a carrier concentration variation region (3) having a carrier concentration different from that of the substrate, and an electrode (4) is provided on the side surface of the substrate. irradiating the substrate with scanning electromagnetic waves along the X and Y directions from the upper part of the substrate or the lower part of the substrate, and measuring the potential within the substrate due to the irradiation of the electromagnetic waves between the electrodes; P-N junctions (2A, 2B) at the boundary between the reverse conductivity type region (2) of the substrate or the boundary between the substrate and the carrier concentration fluctuation region (3) (3A, 3B)
) By measuring the potential fluctuation within the substrate (1) due to the internal electric field generated in the substrate, the position of the internal electric field within the substrate is detected, and the position of the P-N junction (2A, 2B) is determined. Alternatively, the boundary position (3A, 3B) between the substrate (1) and the carrier concentration fluctuation region (3) is detected, and the P-N junction (2A
, 2B), and the substrate and carrier concentration variation region (3
), based on the detection information of the boundary positions (3A, 3B), the resist film applied to the semiconductor substrate is exposed to light, or the implantation position for ion implantation into the semiconductor substrate is determined. A method for manufacturing a semiconductor device.