JPH0338035A - Manufacture of diffusion wafer - Google Patents

Manufacture of diffusion wafer

Info

Publication number
JPH0338035A
JPH0338035A JP17356989A JP17356989A JPH0338035A JP H0338035 A JPH0338035 A JP H0338035A JP 17356989 A JP17356989 A JP 17356989A JP 17356989 A JP17356989 A JP 17356989A JP H0338035 A JPH0338035 A JP H0338035A
Authority
JP
Japan
Prior art keywords
wafer
diffusion
lapped
wafers
silicon ingot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17356989A
Other languages
Japanese (ja)
Other versions
JP2851059B2 (en
Inventor
Takahiro Kiryu
桐生 隆弘
Hiroshi Sato
博史 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Coorstek KK
Original Assignee
Toshiba Ceramics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Ceramics Co Ltd filed Critical Toshiba Ceramics Co Ltd
Priority to JP17356989A priority Critical patent/JP2851059B2/en
Publication of JPH0338035A publication Critical patent/JPH0338035A/en
Application granted granted Critical
Publication of JP2851059B2 publication Critical patent/JP2851059B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Abstract

PURPOSE:To manufacture a diffusion wafer at a low cost by reducing the thickness of silicon ingot which is sued to obtain one diffusion wafer. CONSTITUTION:By cutting and polishing silicon ingot, a lapped wafer 1 is obtained, whose thickness is about twice the conventional lapped wafer, and finally, two diffusion wafers 3 are manufactured from the one lapped wafer 1. When the lapped wafer 1 is obtained from the silicon ingot, the same cutting margin and lapping margin are prepared for one lapped wafer 1. In this case, the total of the cutting margin and the lapping margin for obtaining total lapped wafers may be one half as compared with the conventional method. As a result, the total of the cutting margin and the lapping margin required for obtaining the final diffusion wafer 3 from the initial silicon ingot is reduced. Thereby the diffusion wafer 3 can be manufactured at a low cost.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は拡散ウェハの製造方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method of manufacturing a diffusion wafer.

〔従来の技術〕[Conventional technology]

シリコンウェハには、メーカーにより片面に不純物拡散
が施された状態でユーザーに出荷されるものがあり、こ
れらは一般に拡散ウェハと呼ばれている。この拡散ウェ
ハは、正確な拡散濃度及び拡散深さが確保されているた
め、主に三重拡散型トランジスタの基板として用いられ
ている。
Some silicon wafers are shipped to users with impurity diffusion applied to one side by the manufacturer, and these are generally called diffusion wafers. This diffusion wafer is mainly used as a substrate for triple diffusion type transistors because accurate diffusion concentration and diffusion depth are ensured.

従来、拡散ウェハは第2図(a)〜(d)に示すような
方法で製造されている。まず、例えばN型のシリコンイ
ンゴットをスライスしラッピングしてN型ラップトウェ
ハ1を得る(第2図(a)図示)。
Conventionally, diffusion wafers have been manufactured by the method shown in FIGS. 2(a) to 2(d). First, for example, an N-type silicon ingot is sliced and wrapped to obtain an N-type wrapped wafer 1 (as shown in FIG. 2(a)).

このラップトウェハlの両面に例えばN型不純物を拡散
してN0型拡散層2(拡散深さ70〜250t1M)を
形成する(同図(b)図示)。ここで、ラップトウェハ
及び拡散層の導電型は、用途に応じて、N型、P型のい
ずれでもよい。この両面拡散されたウェハ1の片面の拡
散層を研磨して除去する(同図(C)図示)。その後、
洗浄を行って、第2図(d)に示すような拡散ウェハ3
が得られる。
For example, an N-type impurity is diffused on both sides of this lap wafer 1 to form an N0-type diffusion layer 2 (diffusion depth 70 to 250t1M) (as shown in FIG. 3B). Here, the conductivity type of the lap wafer and the diffusion layer may be either N type or P type depending on the application. The diffusion layer on one side of the wafer 1, which has been subjected to double-sided diffusion, is polished and removed (as shown in FIG. 2C). after that,
After cleaning, a diffusion wafer 3 as shown in FIG. 2(d) is prepared.
is obtained.

なお、第2図(b)の工程でウェハの片面にのみ不純物
を拡散する方法もあるが、この場合も第2図(C)に対
応する工程でウェハの不純物が拡散されていない側の片
面の研磨が行われる。
Note that there is also a method of diffusing impurities only on one side of the wafer in the step shown in FIG. 2(b), but in this case also, in the step corresponding to FIG. Polishing is performed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、従来の方法では、シリコンインゴットからラッ
プトウェハを経て拡散ウェハを製造するまでに、1枚の
拡散ウニn3りの切り代(しろ)及びラップ代が大きい
ため、コストが上昇するという問題があった。
However, in the conventional method, there was a problem in that the cost increased because the cutting margin and wrapping margin of one diffusion sear n3 was large until manufacturing the diffusion wafer from the silicon ingot through the lapped wafer. .

本発明は前記問題点を解決するためになされたものであ
り、低コストで拡散ウェハを製造できる方法を提供する
ことを目的とする。
The present invention has been made in order to solve the above-mentioned problems, and an object of the present invention is to provide a method of manufacturing a diffusion wafer at low cost.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の拡散ウェハの製造方法は、複数のシリコンウェ
ハの両面に不純物を拡散する工程と、両面拡散された複
数のシリコンウェハを接着剤で接着してインゴットを作
製する工程と、インゴットを構成する両面拡散された各
シリコンウェハの中央部を切断する工程と、接着剤を除
去して片面拡散された拡散ウェハを得る工程とを具備し
たことを特徴とするものである。
The method for manufacturing a diffusion wafer of the present invention includes a step of diffusing impurities on both sides of a plurality of silicon wafers, a step of bonding a plurality of silicon wafers that have been diffused on both sides with an adhesive to prepare an ingot, and forming an ingot. This method is characterized by comprising a step of cutting the central portion of each silicon wafer that has been diffused on both sides, and a step of removing the adhesive to obtain a diffusion wafer that has been diffused on one side.

本発明においては、従来と同様に、ラップトウェハ及び
拡散層の導電型はN型、P型のいずれでもよく、用途に
応じて決定される。
In the present invention, as in the prior art, the conductivity type of the lap wafer and the diffusion layer may be either N type or P type, and is determined depending on the application.

本発明において、接着剤は特に限定されないが、ウェハ
に不純物が付着することがなく、Lかも容易に除去でき
るものが好ましい。このような接着剤としては例えばパ
ラフィンを挙げることができる。パラフィンは精製が容
易で、しかも有機溶剤を用いて容易に除去することがで
きる。接着剤の量はウェハの直径によっても異なるため
、−taに限定できないが、接着剤の量が少なすぎると
接着しに<<、多すぎるとムラになって均一に接着する
ことができない。
In the present invention, the adhesive is not particularly limited, but it is preferably one that does not allow impurities to adhere to the wafer and can be easily removed. Such adhesives include, for example, paraffin. Paraffin is easy to purify and can be easily removed using an organic solvent. Since the amount of adhesive varies depending on the diameter of the wafer, it cannot be limited to -ta, but if the amount of adhesive is too small, the bonding will be difficult. If it is too large, the bonding will be uneven, making it impossible to bond uniformly.

本発明において、両面拡散された複数のシリコンウェハ
を接着剤で接着して作製されたイン・ゴツトを構成する
各シリコンウェハの中央部を切断(スライス)するには
、C2法により引き上げられたインゴットをスライスす
る場合と同様な方法が用いられる。すなわち、インゴッ
トをカーボンベースに接着してカーボンベースごと切断
機にセットし、ブレードでインゴットとともにカーボン
ベースまでスライスする。
In the present invention, in order to cut (slice) the central part of each silicon wafer constituting an ingot made by bonding a plurality of double-sided diffused silicon wafers with an adhesive, an ingot pulled by the C2 method is used. A method similar to that used for slicing is used. That is, the ingot is adhered to a carbon base, the carbon base and the carbon base are set in a cutting machine, and the ingot and the carbon base are sliced with a blade.

〔作用〕[Effect]

本発明方法では、シリコンインゴットを切断・研磨して
、従来のラップトウェハの約2倍の厚さのラップトウェ
ハを得て、最終的には1枚のラップドウェへ当り2枚の
拡散ウェハを製造する。つまり、従来はシリコンインゴ
ットからA枚のラップトウェハを得ていたとすると、本
発明方法においてはシリコンインゴットからA/2枚の
ラップトウェハを得るだけでよい。このため、シリコン
インゴットからラップトウェハを得る際に、1枚のラッ
プドウェへ当り同一の切り代及びラップ代を見込むとす
れば、全ラップトウェハを得るための切り代及びラップ
代の合計は、本発明方法では従来の方法の1/2でよい
。また、ラップトウェハから拡散ウェハを得る際には、
従来の方法で片面の拡散層を研磨するためのラップ代と
、本発明方法において各シリコンウェハの中央部を切断
するための切り代とは同程度でよい。したがって、本発
明方法では、最初のシリコンインゴットから最終的な拡
散ウェハをjするまでの全体の切り代及びラップ代を従
来よりも大幅に減少することかできるので、低コストで
拡散ウェハを製造できる。
In the method of the present invention, a silicon ingot is cut and polished to obtain a lapped wafer approximately twice as thick as a conventional lapped wafer, and finally two diffusion wafers are produced per lapped wafer. That is, if conventionally A lapped wafers were obtained from a silicon ingot, in the method of the present invention, it is only necessary to obtain A/2 lapped wafers from a silicon ingot. Therefore, when obtaining lapped wafers from silicon ingots, if the same cutting allowance and wrapping allowance are expected for each lapped wafer, the total cutting allowance and wrapping allowance to obtain all lapped wafers is calculated using the method of the present invention. It only requires 1/2 of the conventional method. Also, when obtaining a diffusion wafer from a lap wafer,
The lapping allowance for polishing the diffusion layer on one side using the conventional method and the cutting allowance for cutting the central portion of each silicon wafer using the method of the present invention may be approximately the same. Therefore, in the method of the present invention, the overall cutting and lapping allowances from the initial silicon ingot to the final diffusion wafer can be significantly reduced compared to the conventional methods, so diffusion wafers can be manufactured at low cost. .

〔実施例〕〔Example〕

以下、本発明の実施例を第1図(a)〜(d)を参照し
て説明する。なお、以下の実施例では、全体の厚さが2
00us、拡散層の深さが150μsの拡散ウェハを製
造する場合について説明する。
Embodiments of the present invention will be described below with reference to FIGS. 1(a) to 1(d). In addition, in the following examples, the total thickness is 2
A case will be described in which a diffusion wafer with a diffusion layer depth of 150 μs and a diffusion layer depth of 150 μs is manufactured.

まず、N型のシリコンインゴットをスライスしラッピン
グして得られた厚さ900、.5インチ径のN型ラップ
トウェハ1の両面にN型不純物を拡散して拡散深さ15
0μのN+型型数散層2形成した(第1図(a)図示)
。次に、この両面拡散されたウェハ1を複数枚用意し、
50−150℃に加熱したパラフィン4を1〜5g滴下
し加圧して順次これらを接着することによりインゴット
を作製した(同図(b)図示)。このインゴットをカー
ボンベースに接着し、切断機にセットした後(図示せず
)、インゴットを構成する両面拡散された各ウェハ1の
中央部をカーボンベースが分離されるまで切断した。更
に、アルカリ洗浄してカーボンベースをはずし、溶剤を
用いて洗浄することによりパラフィン4を除去した。そ
の後、最終洗浄を行い、最後に鏡面加工を行った(同図
(c)図示)。
First, an N-type silicon ingot was sliced and wrapped to a thickness of 900 mm. N-type impurities are diffused on both sides of a 5-inch diameter N-type lapped wafer 1 to a diffusion depth of 15.
A 0μ N+ type dispersed layer 2 was formed (as shown in Figure 1(a)).
. Next, prepare a plurality of wafers 1 with this double-sided diffusion,
An ingot was prepared by dropping 1 to 5 g of paraffin 4 heated to 50 to 150° C. and bonding them one after another by applying pressure (as shown in FIG. 13(b)). After bonding this ingot to a carbon base and setting it in a cutting machine (not shown), the central part of each wafer 1 comprising the ingot, which had been diffused on both sides, was cut until the carbon base was separated. Furthermore, the carbon base was removed by alkali washing, and paraffin 4 was removed by washing with a solvent. Thereafter, a final cleaning was performed, and finally a mirror finish was performed (as shown in FIG. 4(c)).

こうして、厚さ20On、拡散深さ150.の拡散ウェ
ハ3を得た(同図(d)図示)。
Thus, the thickness is 20 On and the diffusion depth is 150. A diffusion wafer 3 was obtained (as shown in FIG. 3(d)).

ここで、従来の方法により厚さ200B、拡散深さ15
0 nの拡散ウェハを得る場合、ラップ代を250μ見
込んで厚さ450μのラップトウェハが必要とされてい
る。この厚さ450nのラップトウェハを得るためには
、切り代及びラップ代を410 tan見込んで1枚の
ラップドウェへ当り厚さ860nに相当するシリコンイ
ンゴットが使用される。すなわち、従来は厚さ200p
の拡散ウェハを得るために、厚さ860μのシリコンイ
ンゴットが使用されている。
Here, the thickness is 200B and the diffusion depth is 15B by the conventional method.
In order to obtain a 0 n diffusion wafer, a lapped wafer with a thickness of 450 μm is required, allowing for a lap allowance of 250 μm. In order to obtain a wrapped wafer having a thickness of 450 nm, a silicon ingot having a thickness of 860 nm per lapped wafer is used, with a cutting allowance and a wrapping allowance of 410 tan. That is, conventionally the thickness was 200p.
A silicon ingot with a thickness of 860μ is used to obtain a diffusion wafer of .

これに対して、前記実施例では厚さ20On、拡散深さ
150 Mの拡散ウェハを得るために、1枚当りの切り
代を25On、 2枚の合計で500n見込んで厚さ9
00μのラップトウェハから2枚の拡散ウェハを得てい
る。この厚さ900 tanのラップトウェハを得るた
めには、切り代及びラップ代を410゜見込んで1枚の
ラップドウェへ当り厚さ1310Bに相当するシリコン
インゴットが使用される。すなわち、前記実施例では厚
さ200μの拡散ウェノ\を2枚得るために、厚さ13
10μのシリコンインゴットが使用され、1枚の拡散ウ
ニへ当りのシリコンインゴットの厚さは855nである
On the other hand, in the above example, in order to obtain a diffusion wafer with a thickness of 20 On and a diffusion depth of 150 M, the cutting allowance for each wafer was 25 On, and the total thickness of the two wafers was 500 nm.
Two diffusion wafers are obtained from a 00μ lapped wafer. In order to obtain a lapped wafer having a thickness of 900 tan, a silicon ingot having a thickness of 1310B is used for one lapped wafer, with a cutting allowance and a wrapping allowance of 410°. That is, in the above example, in order to obtain two diffusion sheets with a thickness of 200μ, a thickness of 13
A 10μ silicon ingot is used, and the thickness of the silicon ingot per diffusion sea urchin is 855n.

このように本実施例では従来と比較して1枚の拡散ウェ
ハを得るために使用されるシリコンインゴットの厚さを
205 m (24%)減少できる。これに伴い、本実
施例では従来より材料コストを24%低減することがで
きる。
As described above, in this embodiment, the thickness of the silicon ingot used to obtain one diffusion wafer can be reduced by 205 m (24%) compared to the conventional method. Accordingly, in this embodiment, the material cost can be reduced by 24% compared to the conventional method.

〔発明の効果〕〔Effect of the invention〕

以上詳述したように本発明方法では低コストで拡散ウェ
ハを製造することができ、その工業的価値は極めて大き
い。
As described in detail above, the method of the present invention allows diffusion wafers to be manufactured at low cost, and its industrial value is extremely large.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)〜(d)は本発明の実施例における拡散ウ
ェハの製造方法を示す断面図、Ts2図(a)〜(d)
は従来の拡散ウェハの製造方法を示す断面図である。 1・・・シリコンウェハ、2・・・拡散層、3・・・拡
散ウェハ、 4・・・パラフィ ン (接着剤)
Figures 1 (a) to (d) are cross-sectional views showing the method for manufacturing a diffusion wafer in an embodiment of the present invention, and Figures 2 (a) to (d)
1 is a cross-sectional view showing a conventional method for manufacturing a diffusion wafer. 1... Silicon wafer, 2... Diffusion layer, 3... Diffusion wafer, 4... Paraffin (adhesive)

Claims (1)

【特許請求の範囲】[Claims] 複数のシリコンウェハの両面に不純物を拡散する工程と
、両面拡散された複数のシリコンウェハを接着剤で接着
してインゴットを作製する工程と、インゴットを構成す
る両面拡散された各シリコンウェハの中央部を切断する
工程と、接着剤を除去して片面拡散された拡散ウェハを
得る工程とを具備したことを特徴とする拡散ウェハの製
造方法。
A process of diffusing impurities onto both sides of multiple silicon wafers, a process of bonding multiple silicon wafers that have been diffused on both sides with an adhesive to create an ingot, and a central part of each silicon wafer that has been diffused on both sides that make up the ingot. 1. A method for manufacturing a diffusion wafer, comprising the steps of: cutting the wafer; and removing an adhesive to obtain a diffusion wafer with diffusion on one side.
JP17356989A 1989-07-05 1989-07-05 Diffusion wafer manufacturing method Expired - Lifetime JP2851059B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17356989A JP2851059B2 (en) 1989-07-05 1989-07-05 Diffusion wafer manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17356989A JP2851059B2 (en) 1989-07-05 1989-07-05 Diffusion wafer manufacturing method

Publications (2)

Publication Number Publication Date
JPH0338035A true JPH0338035A (en) 1991-02-19
JP2851059B2 JP2851059B2 (en) 1999-01-27

Family

ID=15962993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17356989A Expired - Lifetime JP2851059B2 (en) 1989-07-05 1989-07-05 Diffusion wafer manufacturing method

Country Status (1)

Country Link
JP (1) JP2851059B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107958929A (en) * 2016-10-17 2018-04-24 富士电机株式会社 Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107958929A (en) * 2016-10-17 2018-04-24 富士电机株式会社 Semiconductor device

Also Published As

Publication number Publication date
JP2851059B2 (en) 1999-01-27

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