JPH0338742B2 - - Google Patents

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device by improving isolation technology between devices such as bipolar or MOS type ICs and LSIs. Regarding the method.

(Prior Art) Conventionally, as methods for separating elements in the manufacturing process of semiconductor devices, especially bipolar ICs, pn junction isolation,
Selective oxidation is commonly used. This method will be explained below using a bipolar vertical npn transistor as an example.

First, as shown in FIG. 1a, a p-type silicon substrate 1
A highly concentrated n-type buried region 2 is selectively formed, and then an n-type semiconductor layer 3 is epitaxially grown to form a silicon oxide film 4 of about 1000 Å for selective oxidation. An oxidation-resistant silicon nitride film with a thickness of approximately 1000 Å is deposited on the substrate. Continuing,
The silicon oxide film 4 and the silicon nitride film 5 are patterned by photolithography to form silicon oxide film patterns 4a, 4b and silicon nitride film patterns 5a, 5.
form b. Subsequently, the silicon oxide film patterns 4a, 4b and the silicon nitride film pattern 5
Using a and 5b as masks, the n-type semiconductor layer 3 is
Silicon was etched to about 5000 Å, and p-type regions 6a and 6b were formed by boron ion implantation using the same patterns 4a, 4b, 5a, and 5b as masks (as shown in FIG. 1c). Next, thermal oxidation was performed in a steam or wet atmosphere to selectively grow silicon oxide films 7a to 7c with a thickness of about 1 .mu. (as shown in FIG. 1d). Next, silicon nitride film patterns 5a and 5b are formed.
For example, the base region 8 is formed by removing with hot phosphoric acid and performing boron ion implantation in the region directly under the silicon nitride film pattern 5a.
Furthermore, an n-type region 9 to serve as an emitter, an n-type region 10 for leading out the collector electrode, etc. are formed by arsenic ion implantation, and a contact window is formed in the silicon oxide film pattern 4a formed in advance. After opening, emitter electrode 1
1. A vertical npn transistor was manufactured by forming a base electrode 12 and a collector electrode 13. (Illustrated in Figure 1e). In this case, element isolation of the npn transistor is performed using field oxide films 7a and 7 with a thickness of about 1μ.
However, if the thickness of the n-type semiconductor layer 6 is about 1 to 2 μm, field oxidation by selective oxidation can be directly performed using p-type regions 6a, 6b, etc. The device can be brought into contact with the mold substrate 1 to separate the elements. In addition, even when devices are directly isolated using a field oxide film, ion implantation of p-type impurities for channel stop is performed between the p-type substrate 1 and the field oxide film to prevent leakage current between devices. It is preferable to carry out a pre-treatment.

However, the method of manufacturing bipolar ICs using the conventional selective oxidation method described above has various drawbacks as shown below.

FIG. 2 shows in detail the cross-sectional structure when field oxide films 7a and 7c are formed using Si ₃ N ₄ patterns 5a and 5b as masks. However, in FIG. 2, the silicon etching of the semiconductor layer 3 is
I haven't done it yet. It is generally known that in the selective oxidation method, the field oxide film 7b grows by digging into the region under the Si ₃ N ₄ pattern 5a (see
area F in the figure). This is because the oxidizing agent diffuses through the thin SiO ₂ film 4a under the Si ₃ N ₄ pattern 5a during field oxidation, resulting in the so-called bird's beak and the field oxide film 7.
The thick part b consists of a part E that wraps around in the lateral direction as well. For example, the length of F is Si ₃ N ₄ pattern 5a
The thickness of the SiO ₂ film 4a below it is 1000 Å.
Filter field oxide film 7b with a film thickness of 1 μm under the conditions of
When grown, it reaches approximately 1 μm. Therefore,
The width c of the field area is Si ₃ N ₄ pattern 5a, 5
If the distance A between b is 2 μm, since F is 1 μm, it cannot be made smaller than 4 μm, which is a big hindrance to LSI integration. For this reason, recently, a method has been developed to suppress the bird's beak (part D in the figure) by increasing the thickness of the Si ₃ N ₄ patterns 5a and 5b and thinning the SiO ₂ film underneath, and by increasing the thickness of the field oxide film 7b. Attempts have been made to reduce the thickness of the field oxide film to suppress the intrusion F of the field oxide film. However, in the former case, the stress at the end of the field increases and defects are more likely to occur, and in the latter case, there are problems such as a drop in field inversion voltage and an increase in wiring capacitance in the field part, which limits the ability to achieve high integration using selective oxidation. There is.

When the above-mentioned barb beak or the like occurs, the following problems occur. This will be explained using the manufacturing process of a bipolar transistor by the conventional selective oxidation method shown in FIGS. 3a and 3b.

As shown in FIG. 3a, the surface of the semiconductor layer 21, which will become the n-type collector region, is coated using the conventional selective oxidation method.
Silicon oxide films 22a and 22b were formed, and using the oxide films as masks, a p-type base region 23 was formed by boron ion implantation. Next, as shown in FIG. 3b, an n-type emitter region was formed by a diffusion method or an ion implantation method. Here, the silicon oxide film 24 is an insulating film for taking out the electrode.
The problem with the manufacturing method using the conventional selective oxidation method is mainly that the formed silicon oxide film 22a,
This is due to the so-called bird's beak shape such as 22b, stress in the semiconductor region near the bird's beak, and the resulting defects. First, regarding the shape of the base region 23, let C be the depth from the semiconductor main surface of the base junction formed by boron ion implantation, and D be the depth of the base junction directly under the bird's beak. , the value of D decreases by the thickness of the bird's beak oxide film.
Furthermore, since the surface of the silicon oxide film is etched during the etching process during the manufacturing process, the value of D becomes even smaller. For this reason, the bird
When an Al electrode for taking out the base is formed at the tip of the beak, the reaction between Al and silicon causes the Al to penetrate the base region, causing device failure.
Furthermore, if the base width of the transistor directly under the main surface of the semiconductor substrate is A, and the base width directly under the bird's beak is B, then as mentioned above, the depth of the base at the bird's beak is shallow and the etching during manufacturing. Due to the treatment, the tip of the bird's beak recedes, and the depth of the emitter from the tip of the bird's beak becomes deeper than other parts, and the stress and defects caused by the selective oxidation process cause the emitter to become smaller. Abnormal diffusion occurs, the depth of the emitter junction becomes deeper, and the base width B directly under the bird's beak becomes smaller than the normal base width A, causing a failure in the collector-emitter breakdown voltage of the NPN transistor. do not have. In this way, selective oxidation can be applied to bipolar
When applied to ICs, it is likely to cause various element defects.

For these reasons, the present applicant proposed a method of manufacturing a bipolar semiconductor device (for example, a vertical npn transistor) using a novel field region forming means described below.

First, as shown in FIG. 4a, a p-type semiconductor substrate 1
High concentration buried layer 1 of n-type impurity selectively on 01
02 was formed, and an n-type epitaxial semiconductor layer 103 was grown to a thickness of about 2.5 μm thereon, and then resist patterns 104a, 104b, and 104c were left on the surface of the semiconductor layer 103 by photolithography.
Next, this patterned resist 10
Using 4a, 104b, and 104c as masks, the semiconductor layer 103 is silicon-etched by anisotropic reactive ion etching until it reaches the p-type substrate 101, so that the width is approximately 1 μm.
Forming grooves 105a and 105b with a depth of about 3μ,
The n-type semiconductor layer 103 is separated into islands (fourth
Figure b shown). At this time, it is preferable to form p-type regions 106a and 106b by boron ion implantation for channel cutting between elements.

Next, as shown in FIG. 4c, a resist 104 is formed.
After removing a, 104b, 104c, CVD-
The SiO ₂ film 107 is connected to the device isolation trenches 105a and 1.
The film is deposited sufficiently thicker than half the width of 05b (approximately 5000 Å). At this time, CVD-SiO ₂ is gradually deposited on the inner surface of the groove, the grooves 105a and 105b are sufficiently filled, and the surface of the CVD-SiO ₂ film 107 is
It is almost flat. Note that during this deposition, there is no need for high-temperature, long-term thermal oxidation treatment as in the selective oxidation method, so the p-type regions 106a, 1
Rediffusion of 06b hardly occurs. Continuing,
CVD-SiO ₂ film 107 with ammonium fluoride in groove 10
The entire surface of the silicon semiconductor layer 103 was etched until portions of the silicon semiconductor layer 103 other than 5a and 105b were exposed. At this time, as shown in FIG. 4d, the top of the semiconductor layer 103 is
The thickness of the CVD-SiO ₂ film 107 is removed,
CVD-SiO ₂ remains only in the trenches 105a and 105b, thereby forming field regions 107a and 107b buried in the semiconductor layer 103.

Next, a p-type base region 108 is formed in the semiconductor region separated by the field regions 107a and 107b by boron ion implantation using a resist block method, and an insulating film 109 with a thickness of about 3000 Å is formed on the entire surface of the semiconductor layer. Then, by photolithography, diffusion windows for the emitter and collector are opened in this insulating film 109, and arsenic ion implantation is performed to form an n-type region 110 that will become the emitter and a collector extraction part. n-type region 111
form. Next, an opening for the p-type base region 108 is formed, an electrode material such as Al is deposited on the semiconductor surface, and this electrode material is patterned by photolithography to form the base electrode 112, emitter electrode 113, and collector electrode. Forming the electrode 114
An npn bibolar transistor is manufactured (as shown in FIG. 4e).

According to the method described above, a bipolar semiconductor device having various effects shown below can be obtained.

(1) Since the area of the field region is determined by the area of the groove formed in advance in the semiconductor layer, by reducing the area of the groove, it is possible to easily form the initially intended fine field region. type semiconductor device can be obtained.

(2) The depth of the field region is determined by the depth of the groove provided in the semiconductor layer, regardless of the area, so the depth can be selected arbitrarily, and
A high-performance bipolar semiconductor device that can reliably prevent current leakage between elements in the field region can be obtained.

(3) After forming the groove and selectively doping the channel stopper impurity into the groove, the impurity region is Since it does not re-diffuse in the lateral direction and reach the buried layer of the element forming region or the active region of the transistor, it is possible to prevent the effective reduction of the element forming area.
In this case, if the impurity is doped by ion implantation, the impurity ion-implanted layer can be formed at the bottom of the trench, and even if the ion-implanted layer is re-diffused, it will still remain in the surface layer of the element formation region (active part of the transistor). Because it does not extend to
It is possible to prevent the effective element formation region from being reduced, and also to prevent the impurity region from becoming a hindrance to the transistor active region.

(4) When a field region is formed by leaving an insulating material in all of the grooves, the substrate is flattened, so that it is possible to prevent breakage from occurring during the subsequent formation of electrode wiring.

As described above, the above method has many advantages. However, although it is possible to form an LSI using narrow field regions, there are some difficulties in forming a wide field region. In other words, the width of the field depends on the width S of the groove, and in order to leave the insulating film in the groove, the thickness of the insulating film (T) must be greater than 1/2S, and the width of the field is large. Sometimes the insulating film also needs to be deposited fairly thickly. For example, in order to form a field with a width of 20 .mu.m, the insulating film must be thicker than 10 .mu.m, and there are many difficult problems such as deposition time, film thickness accuracy, and crack-free conditions. Furthermore, it is very difficult to form a field with a width of 200 μm (for example, the lower part of an Al bonding pad) in the above direction. Therefore, if a wide field is required, first create narrow fields 107a, 107b, 1 according to the method described above, as shown in FIG.
After embedding 07c, for example, an insulating film (SiO ₂ )
A method was used in which a wide field region 107' was formed by depositing the insulating film and partially leaving this insulating film by photolithography.

Although this method allows the formation of a wide field oxide film and overcomes most of the deficiencies of the selective oxidation method, one major drawback occurs. That is, a step occurs at the end of the wide field film 107' shown in FIG. 5, and flatness is lost. In the case of the selective oxidation method, half of the field film is buried in the silicon semiconductor layer, but in this method, the field film thickness becomes a step, so the step is larger than that in the selective oxidation method, making it difficult to perform microlithography near the wide field film. This has become a major hindrance for those who need it.

(Problems to be Solved by the Invention) As a result of further intensive research based on the above-mentioned method, the present invention has developed a field region that is self-aligned to the groove of the semiconductor layer, whose surface is at the same level as the main surface of the semiconductor layer, and which has a wide width. The present invention aims to provide a method for manufacturing a semiconductor device in which a wiring made of a conductive material with excellent flatness is buried in a field region.

[Structure of the invention] (Means for solving problems) The present invention will be explained in detail below.

First, a mask material film is deposited on a semiconductor layer such as silicon, and then wide and narrow field region portions of the mask material film are removed by photolithography to form a mask pattern. Examples of the mask material film used here include oxidation-resistant materials such as a silicon nitride film or a two-layer film of a silicon oxide film and a silicon nitride film, a resist, SiO ₂ , and the like. Next, using this mask pattern, the semiconductor layer is selectively etched to a desired depth to form wide and narrow first trenches. In this case, if a directional etching method such as reactive ion etching or ion milling is used as the etching means, it is possible to provide a groove portion with vertical or nearly vertical side surfaces. However, a groove portion whose side surfaces are tapered may be formed, and by forming such a groove portion, it becomes possible to fill the first separating material film described later with a good shape. Next, after removing the mask pattern, a thin first separation material film is formed on the inner surface of the first groove. Examples of the first separation material film used here include a thermal oxide film formed by thermal oxidation or nitriding treatment, a Si ₃ N ₄ film, and the like.

Next, a conductive material film made of polycrystalline silicon doped with impurities such as phosphorus, arsenic, and boron is deposited over the entire surface of the semiconductor layer including the first trench. The conductive material film is deposited to a thickness such that it fills the first trench in which the first separation material film is formed, and the surface of the conductive material film is approximately the same as the surface of the semiconductor layer in the trench.

Next, a striped mask pattern is formed on the conductive material film within the wide first groove. Examples of the mask pattern material used here include resist, SiO ₂ , Si ₃ N ₄ and the like. Next, by patterning the conductive material film using the mask pattern by a directional etching method such as reactive ion etching, a striped conductive material film pattern is formed within the first groove. A narrow second groove is formed between them. At this time, even in a narrow groove formed in another part of the semiconductor layer, if the conductive material film formed in the groove is sufficiently thicker than half the width of the groove, A conductive material remains.

Next, an insulating material is deposited so as to fill the second trench between the conductive material film patterns, and then the insulating material film is etched until the surface of the semiconductor layer is exposed to insulate the second trench. A second separating material consisting of the material remains. Thereafter, if necessary, thermal oxidation is performed to form a thin oxide film on the surface of the conductive material pattern made of polycrystalline silicon.

By leaving the second separating material in the second groove between the conductive material film patterns using the above-described means,
A wide field region having a striped conductive material film pattern (wiring) surrounded by a thin first separation material film and a thin second separation material film and whose surface is approximately at the same level as the surface of the semiconductor layer is formed. . A disparate type element or a semiconductor layer is separated by such a wide field region or a narrow field region formed as necessary.
A semiconductor device is manufactured by forming MOS type elements and the like.

(Function) According to the present invention, it is possible to form a wide field region with no steps and with built-in wiring, and to obtain a semiconductor device that has high-density wiring and achieves high integration. Can be done.

(Example) Hereinafter, an example in which the present invention is applied to manufacturing a bipolar LSI will be described with reference to the drawings.

Example 1 First, a buried layer 302 with a high concentration of n-type impurities is selectively formed in a p-type semiconductor substrate 301, and an n-type epitaxial semiconductor layer 30 with a thickness of about 2 μm is formed on this.
3, a thin silicon nitride film is deposited on the surface of the semiconductor layer 303, and the silicon nitride film corresponding to the areas where narrow and wide trenches are to be formed is removed by photo-etching to form silicon nitride oxide patterns 304a to 304a. 304c was formed (as shown in FIG. 6a).

Next, silicon nitride film patterns 304a-3
04c as a mask, the semiconductor layer 303 is etched to a desired depth by reactive ion etching to form a narrow first groove 305a and a wide first groove 305b, and then the same pattern 304a is etched.
Using ~304c as a mask, boron ions are implanted, activated, and p ⁺
Mold regions 306a and 306b were formed. The groove portion 3 continues to be formed on the entire surface including the groove portions 305a and 405b.
The first layer is sufficiently thinner than the depth of 05a and 305b.
A CVD-SiO ₂ film 307 was deposited (as shown in FIG. 6b).

Next, a phosphorus-doped polycrystalline silicon film 3 is formed on the entire surface.
08 is deposited to have a thickness comparable to the depth of the wide groove 305b, and then a striped resist pattern 309a,
309b was formed (as shown in FIG. 6c). Subsequently, the polycrystalline silicon film 308 was subjected to anisotropic etching such as reactive ion etching. At this time, polycrystalline silicon 310 is placed in the narrow groove 305a covered with the thin first CVD-SiO ₂ film 307.
remained. At the same time, polycrystalline silicon patterns 311a and 311b are formed on the sides of the wide groove 305b.
However, the polycrystalline silicon pattern 311 also exists in the groove portion 305b under the resist patterns 309a and 309b.
c and 311b were formed (as shown in FIG. 6d).
In this case, if a wet etching method is used, only polycrystalline silicon patterns 311a and 311b corresponding to resist patterns 309a and 309b are formed.

Next, the second CVD-SiO ₂ 312 is applied to the second layer between the polycrystalline silicon patterns 311a to 311d.
The film was deposited to a thickness sufficiently thicker than half the width of the opening of the groove (as shown in FIG. 6e). Next, CVD−
The SiO ₂ film 312 is etched with ammonium fluoride until the surfaces of the silicon nitride film patterns 304a to 304c are exposed, and then etched between the polycrystalline silicon patterns 311a to 311d in the wide groove 305b.
CVD-SiO ₂ 312'a to 312'c were left (as shown in FIG. 6f). Subsequently, the silicon nitride film patterns 304a to 304c were removed and thermal oxidation treatment was performed. As a result, an oxide film 313 is grown on the surface of the remaining polycrystalline silicon 310 in the narrow groove 305a, and the polycrystalline silicon 310 is surrounded by the first CVD-SiO ₂ film 307 and the oxide film 313.
A narrow field region 314 having (wiring) was formed. At the same time, polycrystalline silicon pattern 31
An oxide film 313 is also grown on the surfaces of 1a to 311d, and the surrounding area is the first CVD-SiO ₂ film 307, CVD-
Polycrystalline silicon patterns 311a to 311d covered with SiO ₂ 312a' to 312c' and oxide film 313
A wide field region 315 having (wiring) was formed (as shown in FIG. 6g). Note that 313' is an oxide film grown on the surface of the semiconductor layer 303. After that, narrow and wide field areas 314 and 31
Although not shown, a pnp transistor was formed in the island-shaped semiconductor layer separated by 5 according to a conventional method to manufacture a bipolar LSI.

According to this embodiment, the phosphorus-doped polycrystalline silicon patterns 311a to 311d functioning as interconnects can be embedded in the wide field region 315, making it possible to form high-density interconnects with high performance and reliability. By doing so, it is possible to obtain a bipolar LSI that achieves high integration.

Note that in manufacturing the semiconductor device according to the present invention, a p-type semiconductor substrate provided as a semiconductor layer is used.
A type epitaxial layer, a p-type semiconductor substrate laminated twice with an n-type epitaxial layer, or a p-type epitaxial layer and an n-type epitaxial layer laminated on the same substrate may be used.

In manufacturing a semiconductor device according to the present invention, in addition to forming an npn bipolar transistor on an n-type semiconductor layer on a p-type semiconductor substrate as in the above embodiment, for example, a triple diffusion method is used on a p-type semiconductor substrate.
An npn bipolar transistor may also be formed.

The method for manufacturing a semiconductor device according to the present invention is not limited to manufacturing npn bipolar transistors as in the above embodiments, but can be similarly applied to manufacturing other bipolar type semiconductor devices such as I ² L and MOS semiconductor devices.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to self-align any fine or wide field region mainly with respect to a groove provided in a semiconductor layer without taking mask alignment margin. Along with being able to form,
It is possible to provide a method for manufacturing a semiconductor device such as a bipolar transistor having a structure in which a plurality of wirings made of a conductive material with excellent flatness are embedded in a wide field region.

[Brief explanation of the drawing]

Figures 1 a to e are cross-sectional views showing the manufacturing process of a vertical npn transistor using the conventional selective oxidation method, Figure 2 is a cross-sectional view illustrating the problems of the conventional selective oxidation method, and Figure 3 a , b are cross-sectional views for explaining problems when the conventional selective oxidation method is applied to bipolar transistors, and Figures 4 a to e are process cross-sectional views showing the manufacturing of an npn bipolar transistor already proposed by the applicant. , FIG. 5 is a sectional view showing a state in which a field region is formed by the deforming means shown in FIGS. . 301...p-type semiconductor substrate, 302...n ⁺ type buried layer, 303...n-type epitaxial semiconductor layer, 204a, 204b...silicon nitride film pattern, 305a, 305b...first trench, 3
06a, 306b... p ⁺ type region, 314, 31
4'...Narrow field area, 315, 31
5'...Wide field area, 307...1st
CVD-SiO ₂ films, 311a to 311d... polycrystalline silicon patterns, 312a' to 312d'... residual CVD-SiO ₂ .

Claims (1)

[Claims] 1. A step of forming a wide first groove in a portion of a semiconductor layer where a field is to be formed, a step of forming a thin first separation material film on the inner surface of the groove, and a step of forming a first separation material film on the inner surface of the trench. forming a conductive material film made of polycrystalline silicon doped with impurities in the groove so as to fill the trench, and patterning the conductive material film to form a striped conductive material film pattern within the groove. and forming a narrow second trench between them, and depositing an insulating material so as to fill the second trench between the conductive material film patterns, and then depositing the insulating material film in the second trench between the conductive material film patterns. By etching until the surface of the semiconductor layer is exposed and leaving a second isolation material made of an insulating material in the second trench, a wide conductive material film pattern and an insulating material embedded in the first trench are formed. 1. A method of manufacturing a semiconductor device, comprising the step of forming a field region. 2. When forming the wide first groove, simultaneously forming a narrow groove in another part of the semiconductor layer, and further leaving the second isolation material in the second groove between the patterns of the conductive material film. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the separating agent is left in the narrow groove at the same time.