JPH0831468B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] This occurs when a window for forming an internal base region and an emitter region is opened in a manufacturing method in which a base extraction electrode is provided and is divided into an external and internal base regions. Impurities are diffused from the impurity-containing film to the side surface of the stepped portion of the substrate to ensure the connection between the external and internal base regions.

 This will improve reliability and yield.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a base extraction electrode type bipolar transistor.

Recently, in order to improve the performance of semiconductor devices such as ICs and LSIs, technological development is being advanced toward higher integration and higher density.

Therefore, the semiconductor device adopts a self-alignment (Self Align) manufacturing method for miniaturization, and the above base extraction electrode type bipolar transistor is also a self-alignment method. As a matter of course, it is more difficult to manufacture the integrated transistor than in the past, and accordingly, a manufacturing method that pays more attention to reliability and yield is desired.

[Prior art] SST (Super Self align Technology) ) The structure is known.

FIG. 3 is a schematic cross-sectional view of a base extraction electrode type transistor produced in the SST structure, where 1 is a p-type silicon substrate, 2 is a field insulating film, 3 is a collector region, 4 is a base extraction electrode, and 5 is A p-type external base region, 6 is a p-type internal base region, 7 is an n-type emitter region, B is a base electrode, E is an emitter electrode, and C is a collector contact electrode.

FIGS. 4A to 4F show sectional views in order of steps of the conventional forming method, in which only the sectional view of the base / emitter forming region is shown. Referring to Fig. 4 (a), the n-type buried layer is thermally diffused on the p-type silicon substrate to grow the n-type epitaxial growth layer.
The n-type collector region 3 made of these layers is defined, and further selectively oxidized to form the field insulating film 2 made of a silicon oxide (SiO ₂ ) film.

See Fig. 4 (b); then, vapor phase growth (CV
D) method is used to deposit a polycrystalline silicon film, boron is injected into this to form a p-type polycrystalline silicon film 4 (base extraction electrode), and a SiO ₂ film 8 is further deposited on the upper surface, followed by heat treatment. To define the external base region 5. In the middle of this formation process, patterning is performed so that the polycrystalline silicon film serves as the base extraction electrode, but this is not shown in this figure.

See FIG. 4C; Next, the window W is opened by etching the SiO ₂ film 8 and the base extraction electrode 4 on the internal base formation region by a RIE (reactive on etch) method by a photo process.

Next, as shown in FIG. 4 (d), heat treatment is performed to form the SiO ₂ film 9 on the bottom and side surfaces of the window W, and then the SiO ₂ film 9 is transmitted from the upper surface to ion-implant boron and heat-treated to form a p-type An internal base region 6 is defined.

See FIG. 4 (e); then, S is formed by CVD on the upper surface including the window W.
The iO ₂ film 10 is deposited, then the polycrystalline silicon film 11 is deposited, and then the RIE method is used for etching to leave the polycrystalline silicon film 11 only on the side surfaces of the window W. Thus, the SiO ₂ films 10 and 9 on the emitter formation region are etched by the RIE method to open the emitter electrode window V.

FIG. 4 (f); Next, a polycrystalline silicon film 12 is deposited and patterned to form an electrode made of the polycrystalline silicon film in the emitter electrode window V, and then the polycrystalline silicon films 12 and 11 are formed. Phosphorus is ion-implanted in the silicon and heat treated to define the n-type emitter region 7.

The above is an example of the method of forming the base lead-out electrode type bipolar transistor of the SST structure which has been conventionally implemented.

[Problems to be Solved by the Invention] By the way, in the above-mentioned forming method, the step of forming the window W described in FIG. 4C is performed by the SiO ₂ film 8 and the p-type polycrystalline silicon film 4 ( Since the etching selection ratio between the base extraction electrode) and the silicon substrate (correctly, the p-type external base region 5) is small, the etching of the silicon substrate cannot be avoided, and the silicon substrate is etched to form a deep step portion. RIE using a chlorine-based gas as a reaction gas is used for this etching.

When such a step portion is formed, even if the inner base region 6 is ion-implanted through this window W and heat-treated to form, it is difficult to connect the outer base region 5 and the inner base region 6 due to the deep step. This is an important problem from the standpoint of reliability and yield of SST structure transistors.

The present invention proposes a forming method for solving such a problem.

[Means for Solving the Problems] The purpose is to open a window for forming an internal base region and an emitter region, and then deposit an impurity-containing film on a semiconductor substrate including a stepped portion opened by the window. A step of etching vertically from the upper surface to leave the impurity-containing film only on the side surface of the step portion, or a step of depositing the impurity-containing film on the semiconductor substrate including the step portion having a window opened and leaving it as it is. Then, a method of manufacturing a semiconductor device including a step of ion-implanting an impurity for forming an internal base region and performing heat treatment to form an internal base region, and at the same time, diffusing the impurity from the impurity-containing film to the side surface of the step portion. Is achieved by

[Operation] That is, according to the present invention, in the method of manufacturing an SST structure, impurities are diffused from the impurity-containing film to the side surface of the step portion generated when the window is opened to connect the external and internal base regions. Then, the reliability and yield of the transistor are improved.

[Examples] Hereinafter, examples will be described in detail with reference to the drawings.

1A to 1E are sectional views in order of steps of the forming method according to the present invention.

FIG. 1 (a); First, similar to the conventional method, the n-type buried layer is thermally diffused on the p-type silicon substrate by a known manufacturing method,
An n-type epitaxial growth layer is grown to define the n-type collector region 3, and further selective oxidation is performed to form a field insulating film 2 made of a SiO ₂ film.

See FIG. 1 (b); Next, a polycrystal silicon film having a film thickness of about 3000 Å is deposited on the upper surface by the CVD method, and boron is injected into the polycrystal silicon film 4 (base extraction). Electrode), and a SiO ₂ film 8 is further deposited on the upper surface and heat treatment is performed to define the external base region 5.

1 (c); Next, the window W is opened by etching the SiO ₂ film 8 on the internal base forming region and the base extraction electrode 4 by the RIE method using a chlorine-based gas as a reaction gas by a photo process. At that time, a step difference of about 2000 Å occurs in the silicon substrate (p-type external base region 5).

See FIG. 1 (d); next, a boron organic film (polyboron film film) 20 having a film thickness of 500 to 1000Å is deposited.

FIG. 1 (e); Next, the boron organic film 20 is vertically etched by the RIE method using a chlorine-based gas to leave the boron organic film 20 only on the step side surface of the window W, and further on it.
A SiO ₂ film 10 having a film thickness of 2000 to 3000 Å is deposited by the CVD method. Next, boron is ion-implanted through the SiO ₂ film 10 and heat-treated to define the p-type internal base region 6, and at the same time, the boron organic film 20 is thermally diffused to the side surface of the window W to form the p-type connection region 21.
To form.

See FIG. 1 (f); then, a polycrystalline silicon film 11 is deposited on the upper surface including the window W by the CVD method and further etched by the RIE method to leave the polycrystalline silicon film 11 only on the side surface of the window W. Let Next, the SiO ₂ film 10 on the emitter formation region is etched by the RIE method by a photo process, and the emitter electrode window V is formed.
Open.

FIG. 1 (g); Next, after depositing and patterning the polycrystalline silicon film 12, an emitter electrode made of the polycrystalline silicon film is formed in the emitter electrode window V, and then the polycrystalline silicon film 12, Ion implantation of phosphorus into 11 and heat treatment
A mold emitter region 7 is defined.

According to the forming method as described above, the external base region 5
The internal base region 6 and the internal base region 6 can be reliably connected to each other by the connection region 21, and the reliability and yield of the transistor can be improved and stabilized.

Next, FIGS. 2A and 2B show sectional views in order of steps of another forming method according to the present invention. This example is a method in which the forming steps shown in FIGS. 1 (d) and 1 (e) are replaced by the forming steps shown in FIG. 2 (a) in the forming method shown in FIG. This is a forming method in which the film 20 is left as it is without being etched by the RIE method.
That is, refer to FIG. 2 (a); the n-type collector region 3 is defined, the field insulating film 2 is formed, the base extraction electrode 4 and the SiO ₂ film 8 are formed thereon, and heat treatment is performed to form the external base region 5. And the window W is opened by etching by the RIE method. Then, the organic boron film 20 is deposited on the entire surface including the window.

See FIG. 2 (b); then, the SiO ₂ film 10 is deposited, and the SiO ₂ film is deposited.
Boron is ion-implanted through 10 and heat-treated to define the p-type internal base region 6 and, at the same time, the boron organic film 20.
To form a p-type connection region 21 by thermal diffusion to the side surface of the window W. Then, a polycrystalline silicon film 11 is deposited, and further RIE is performed.
Method is used to etch the polycrystalline silicon film only on the side surface of the window W.
11 is left, and then the SiO ₂ film 10 is etched by the RIE method to open the emitter electrode window V. Then, an emitter electrode made of a polycrystalline silicon film is formed in the emitter electrode window V in the same manner as described above, and then phosphorus ions are implanted into the polycrystalline silicon films 12 and 11 and heat-treated to form the n-type emitter region 7. To define These steps are almost the same as the steps described in FIG.

In this way, the connection region 21 is formed to reliably connect the external base region 5 and the internal base region 6. Since the boron organic film 20 has a relatively good insulating property, there is no adverse effect even if it is interposed as it is.

Moreover, although the boron organic film 20 is used as the impurity-containing film in the above-mentioned embodiment, a boron silicate glass (BSG) film may be used instead. In addition, the above formation method is
This is an example of a pn transistor, but it goes without saying that it can also be used for a pnp transistor. In that case, a phosphorus silicate glass (PSG) film, an arsenic glass film, or a boron arsenide glass film can be considered as the impurity-containing film.

[Effects of the Invention] As is clear from the above description, according to the present invention, the reliability and yield of the base-drawing-type bipolar transistor are improved, which contributes to the stability of IC quality and yield.

[Brief description of drawings]

1A to 1G are sectional views in order of steps of the forming method according to the present invention, and FIGS. 2A and 2B are sectional views in order of steps of another forming method according to the present invention. The figure is a schematic cross-sectional view of a base extraction type transistor to which the present invention is applied, and FIGS. 4A to 4F are cross-sectional views in order of forming steps of a conventional forming method. In the figure, 1 is a p-type silicon substrate, 2 is a field insulating film, 3 is an n-type collector region, 4 is a base extraction electrode (p-type polycrystalline silicon film), 5 is an external base region, 6 is an internal base region, 7 Is an emitter region, 8, 9 and 10 are SiO ₂ films, 11 and 12 are polycrystalline silicon films, 20 is a boron organic film, and 21 is a connection region.

Claims (2)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a base extraction electrode is provided, and a base region is formed separately from outside and inside, wherein a base extraction electrode and an external base region are formed, and the base extraction electrode is etched, A step of opening a window for forming an internal base region and an emitter region, and then depositing an impurity-containing film on the semiconductor substrate including the stepped portion having the window opened, and etching vertically from the upper surface to form a side surface of the stepped portion. A step of leaving the impurity-containing film only in the above step, and then ion-implanting impurities for forming the internal base region and heat-treating to form the internal base region, and at the same time diffusing the impurity from the impurity-containing film to the side surface of the step portion. A method of manufacturing a semiconductor device, comprising: 2. A method of manufacturing a semiconductor device, wherein a base extraction electrode is provided and a base region is formed separately from outside and inside, a base extraction electrode and an external base region are formed, and the base extraction electrode is etched, A step of opening a window for forming an internal base region and an emitter region, a step of depositing an impurity-containing film on a semiconductor substrate including a stepped portion having the window opened, and then ion implantation of impurities for forming an internal base region And a step of diffusing impurities from the impurity-containing film to the side surfaces of the step portion at the same time as forming the internal base region by heat treatment.