JPH0338842A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce a source inductance and a parasitic capacity between a source and a gate and to eliminate a defect to be caused when an electric-power supply part comes into contact with a wire by a method wherein a plurality of source electric-power supply parts are formed and the individual source electric-power supply parts are connected via a via hole. CONSTITUTION:A semiconductor device is provided with a single gate electric- power supply part 1b; source electric-power supply parts 3b are connected to a package by using via holes 3c. Consequently, the source electric-power supply parts 3b can be installed away from the gate electric-power supply part 1b; in addition, the source electric-power supply parts 3b can be arranged so as not to surround the gate electric-power supply part 1b. Thereby, a defect, in reliability, to be caused when the electric-power supply parts 1b, 3b come into contact with a wire is eliminated, a parasitic capacity between a source and a drain is reduced, and a source inductance is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and particularly to a highly reliable semiconductor device with small parasitic inductance and capacitance and excellent high frequency characteristics.

(Conventional technology) In recent years, with the development of advanced epitaxial growth technology and ultra-fine processing technology, MES (Met
Al Sem1conductor) type FET performance improvement and A ] Ga As / Ga AS
Heterozygous HEMT (High EIec
tron Mobility Transiste
r) has been put into practical use, and the operating frequency of these FETs has increased to 3.
It is being expanded to the EHF band above 0 GHz. This type of high frequency FET is generally arranged on a cross-shaped package for microwave semiconductor devices.

FIG. 4 shows a plan view of a conventional HEMT 30.

A gate electrode 1a having a multi-finger portion 1d and two gate power supply portions 1b connected to each of the multi-finger portions 1d are formed on a semiconductor substrate in a π-shaped planar pattern. A source electrode 3a and a drain electrode 2a are formed with the gate electrode 1a in between, and electrode supply parts 1b, 2b, and 3b connected to each electrode are provided.

The source power supply section 3b has an E-shaped planar pattern and surrounds the π-shaped gate power supply section 1b. H
EMT Chisop is usually installed in a small package of 70ml or 50ml.
b and the source power supply section 3b are close to each other, and the distance therebetween is 1 to several tens of micrometers.

As shown in FIG. 5, a gate power supply section 1b.

The source power supply section 3b and the drain power supply section 2b are respectively connected to the gate line, source line, and train line of the package by bonding wires.

(Problems to be Solved by the Invention) However, the above conventional technology has the following problems. Since the electrode supply parts 1b, 2b, and 3b of the gate, drain, and source electrodes are connected to the gate, drain, and source lines of the package by bonding wires, the following problem occurs.

■) Source power supply part 3b by wire bonding
Since the source line of the package is connected to the source line of the package, the source inductance is 0.1 to 0. The gain increased to 2 nH, and the gain at high frequencies (10 GHz or higher) decreased.

2) Each power supply part 3b of the source electrode and each electrode supply part 1b of the gate electrode are 1 pm -1&IO(tm
Since the electrodes are close to each other, the capacitance between the electrodes increases.
At high frequencies, the noise and gain characteristics of the FET deteriorated.

3) In a 70mil or 50ml package size, the E-shaped power supply section 3b was provided to surround the π-structured gate power supply section 1b;
When wire bonding is performed from the gate power supply section 1b to the gate line of the package, the wire (hereinafter abbreviated as gate wire) tends to come into contact with the source electrode supply section 1bl, making it extremely difficult to control the loop of the wire. For this reason, the manufacturing yield was low. Furthermore, the gate wire and the source power supply section 3b may come into contact with each other due to external stress such as vibration, reducing reliability. Furthermore, since the gate wire is located close to the source power supply section 3b, the parasitic capacitance between the gate and the source increases, deteriorating the noise characteristics and gain characteristics at high frequencies. Furthermore, in order to prevent contact between the gate wire and the source power supply section 3b, the source power supply section 3b was coated with a protective film such as a nitride film, but the thickness of the protective film could not be made sufficiently thick and the gate During wire bonding, the protective film 20 was often destroyed, resulting in contact between the source power supply section 3b and the gate wire.

The present invention has been made to solve the above problems, and its purpose is to reduce the source inductance and the parasitic capacitance between the source and gate, and to provide high reliability without defects caused by contact between the power supply section and the wire. The purpose of the present invention is to provide a high-performance semiconductor device with high performance.

(Means for Solving the Problems) The present invention is a semiconductor device, which includes: a semiconductor substrate having a via hole; a field effect transistor having a gate electrode formed on the semiconductor substrate and having a plurality of multi-finger portions; a source power supply unit connected to the source electrode of the effect transistor and a drain power supply unit connected to the drain electrode; and a single gate power supply unit connected to the plurality of multi-finger units via air bridge wiring. A plurality of the source power supply sections are formed, and each of the source power supply sections is connected via the via hole, thereby achieving the above object.

(Function) Since the power supply parts of the source electrodes are connected to each other on the back surface of the semiconductor substrate through via holes, the package and source can be connected without using wires, which reduces source inductance. . In addition, since the plurality of multi-finger parts are connected to a single gate power supply part by air bridge wiring, and the source power supply part is cast far from the single gate power supply part, the source gate The parasitic capacitance between the two is reduced. Furthermore, since the source power supply section is arranged so as not to surround the single gate power supply section, defects due to contact between the source power supply section and the wire do not occur.

This reduction in source inductance and source-to-gate parasitic capacitance improves noise and gain characteristics, and eliminates wire contact, improving reliability and manufacturing yield.

(Example) Examples of the present invention will be described below.

As shown in FIG. 1, one gate electrode 1a has three multi-finger parts 1d on a semiconductor substrate.

A HEMTIO having one drain electrode 2a and four source electrodes 3a is formed. The source electrode 3a is formed on the side of the gate electrode 1a where the multi-finger section 1d is located, and is connected to the two source power supply sections 3b. Further, each of the three multi-finger parts 1d of the gate electrode 1a is connected to a single gate power supply part 1b by two air bridge wiring lines 1c.

An SfN film 20 (not shown) is formed between the air bridge wiring 1c and the source electrode 3a located below it, and the air bridge wiring 1c and the source electrode 3a are insulated from each other. One end of the air bridge wiring 1c is in electrical contact with the surface of the multi-finger portion through a through hole 21 formed in the underlying SiN film 20. In this embodiment, the other end of the air bridge wiring 1c is continuous with a single gate power supply section 1b, and the air bridge wiring &'A1c and the gate power supply section 1b are integrally formed.

In this way, the plurality of multi-finger parts 1 of the gate electrode 1a
d is connected to the single gate power supply section 1b via the air bridge wiring 1c, the gate power supply section 1b is connected to each of the plurality of multi-finger sections 1d of the gate electrode 1a.
The area of the gate power supply section ib can be significantly reduced compared to the conventional HEMT in which the gate power supply section ib is connected. This word reduces the parasitic capacitance of the gate.

A total of two source power supply units 3b are formed, one each at intervals on the image side of the gate power supply unit 1b,
As shown in FIG. 2, each source power supply section 3b is connected to the back surface of the semiconductor substrate via a via hole wiring 3c formed in the semiconductor substrate.

A metal film 3d is formed on the back surface of the semiconductor substrate, and a source line (not shown) of the package and a source power supply section 3b are connected via this metal film 3d and a via hole wiring 3c. Therefore, a bonding wire connecting the pan cage and the source power supply section 3b is not required, the source inductance is reduced, and poor contact between the bonding wires becomes less likely to occur. Further, since the plurality of source power supply sections 3b are connected to each other on the back surface of the semiconductor via the via hole wiring 3C, there is no need to connect the plurality of source power supply sections 3b to each other on the front surface of the semiconductor substrate. Therefore, unlike the conventional example in which the source power supply section 3b is arranged to surround the gate power supply section 1b, the source power supply section 3b is arranged so as to surround the gate power supply section 1b.
It is possible to arrange the structure without enclosing it. Therefore, the possibility that the bonding wire connecting the gate power supply 1b to the gate line of the package comes into contact with the source power supply 3b is significantly reduced.

As described above, the source power supply section 3b can be arranged so as not to surround the gate power supply section 1b, and the gate power supply section 1b is single and has a reduced area. Therefore, the distance between the source power supply section 3b and the gate power supply section 1b can be increased within a limited area. Therefore, the gate-source capacitance is reduced.

Also, source inductance is reduced by using via holes.

By reducing the gate-source capacitance and source inductance, the HEMT's noise and gain characteristics are significantly improved compared to conventional HEMTs.

Next, Fig. 3 shows the method for manufacturing the device of this embodiment. Refer to and explain.

First, C: an undoped GaAs layer 12 is formed on an aAs substrate 11 by MBE (molecular beam epitaxy). Spacer layer 13 consisting of non-doped A 1 o, 2SG ao, 75A S. Si-doped n-type AI a, i
s G a 6. ? 5A S 14, a cap layer 15 made of Si-doped n-type Ga As is continuously grown. Subsequently, each of the above growth layers 12, 13, 14.15
After removing a predetermined region of the cap layer 15 by photoetching for insulation to form a mesa portion 16, a source electrode 3a and a drain electrode 2a are formed on the surface of the cap layer 15 by a lift-off method.
form. The picture electrodes 3a, 2a are made of Au-Ge (1
000 people), Ni (100 people), Au (1000 people)
After patterning by vapor deposition and lift-off, heat treatment is performed at 400'C for 30 seconds to form an ohmink contact.

Next, an electron beam resist 16 is applied to the wafer surface, and an opening 117 having a width of 0.2 μm is formed in the region between the source electrode 3a and the drain electrode 2a of the resist 1b. Next, using the resist 16 as a mask, the cap layer 15 is etched with a phosphoric acid mixed solution (phosphoric acid/hydrogen peroxide solution, water) to form a recessed structure in which the bottom @ width W is 10 to 30% smaller than the width of the opening 17. form 18. Furthermore, using the resist 16 as a mask, an Al film 19 having a thickness of 3,500 wafers is deposited, and lift-off is performed to form a gate electrode 1a at the bottom of the recess structure 18.

After lift-off, as shown in FIG. 2, a SiN film 20 mm thick is deposited on the wafer surface for insulation, and then the area other than each power supply section is masked with a photoresist pattern, and dry etched to a thickness of 5 jNl20 mm. by removing
A through hole 21 and windows for each power supply section of the gate, drain, and source are formed. Then Tj (1000
People), Pi.

After depositing Au (1000 Å) and Au (15000 Å) in this order, two gates were formed by lift-off.

Drain and source power supply sections 1b, 2b, 3b and air bridge wiring 1c are formed. After this, the wafer is thinned to about 30 to 80 μm, a hole of about 50 μm is made directly under the power supply part 3b of the source electrode, and the back side is metallized by metal plating to form via hole wiring 3c and back side wiring 3d. . next,
After cutting the wafer into individual elements, connect the back metal film 3d of the HEMTIO chip and the source line of the package.
Further, the power supply parts 1b and 2b of the gate and drain electrodes are respectively connected to the gate and drain lines of the package by bonding wires to complete the device of this embodiment.

Next, the characteristics of the HEMT of this example produced in this manner will be described. The HEMT of this example has an air bridge structure and a single gate power supply section, and since the source power supply section and the gate power supply section are far away (separated by 3 μm or more), the gate wire and source electrode power supply section There is no capacitance between 3b and the source-to-gate capacitance is reduced by 20 to 10% compared to conventional HEMTs. Further, the power supply section of the source electrode is connected to the package by the via hole wiring 3c.

3 Source inductance is 5.5% compared to conventional HEMT.
0% is extremely low.

The HEMT of this example has a gate electrode with a multi-finger portion, and as mentioned above, the source inductance and the parasitic capacitance between the source and gate are reduced, so the gate length is 0.20 μm and the total gate width is 280 μm (unit: The noise/gain characteristics of a HEMT with a gate width of 20 μm are 1
Noise figure 0.6dB and associated gain 13d at 2GHz
It became B.

This value is equivalent to the conventional gate length of 0.20 μm and total gate width of 2
Compared to the 80 μm HEMT, the noise figure is 0.3 dB lower and the associated gain is 1 dB higher.

Also, with the same gate length as above, the total gate width is 120 μm (
In this example HEMT with a unit gate width of 20 μm, 23
C: At Hz, the noise figure is 1.1 dB and the associated gain is 1.
1 dB, and the noise figure is 0.5 dB compared to the conventional HEMT with a gate length of 0.20 μm and a total gate width of 120 μm.
The associated gain is 3 dB higher.

4 Furthermore, since the source power supply section 3b of this embodiment is arranged in an island shape so as not to surround the gate power supply section 1b, it is difficult to wire-bond the gate power supply section 3b to the gate line of the package. , conventional F
Seen in ET. Gate wire and source power supply section 3b
There is no possibility of wire touching, and HEMTs can be formed with high reliability and high yield.

(Effects of the Invention) According to the present invention, the semiconductor device includes a single gate power supply section, and the source power supply section is connected to the package through the via hole. It becomes possible to cast the source power supply part far away from the supply part, and it becomes possible to arrange the source power supply part so as not to surround the gate power supply part. This eliminates reliability defects due to contact between the power supply unit and the wire, and also reduces parasitic capacitance between the source and gate and reduces source inductance.

Therefore, the field effect transistor 5 having the structure of the present invention has excellent noise characteristics and gain characteristics even at high frequencies of 10 GHz or higher, and has high reliability without defects due to wire contact.

4. Main points B- Fig. 1 is a plan view for explaining the present invention in detail, Fig. 2 is a cross-sectional view thereof, and Fig. 3 is a plan view for explaining the method for manufacturing the FE lower mold of the embodiment. The sectional view and FIG. 4 are plan views for explaining a conventional example.

1a...gate electrode, lb...gate power supply section 1
c...air bridge wiring, ld...multi-finger section, 2a...drain electrode, 2b...drain power supply section, 3a...source electrode, 3b...source power supply section, 3c via Hole, 3d... Back metal film, 1
0...HEMT, 11...GaAs substrate, 12...
・Undoped GaAs layer, 13...non-doped A I
o, zsGaO, 75AS spacer layer, 14-3
i-doped n-type Alo, zsGao, ysAs, 15
-3 i-doped n-type GaAS cap layer, 20...S
iN film, 21...Through hole, 30...Conventional HE
M.T.

that's all 6

Claims (1)

[Claims] 1. A semiconductor substrate having a via hole; a field effect transistor formed on the semiconductor substrate and having a gate electrode having a plurality of multi-finger parts; and a field effect transistor connected to a source electrode of the field effect transistor. A drain power supply section connected to the source power supply section and the drain electrode, and a single gate power supply section connected to the plurality of multi-finger sections via air bridge wiring, the source power supply section comprising: a drain power supply section connected to the source power supply section and the drain electrode; A semiconductor device comprising a plurality of semiconductor devices, each of which is connected to the source power supply section via the via hole.