JPH0338852A - Verification of integrated-circuit mask pattern - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a method for verifying an integrated circuit mask pattern, and in particular a method for verifying an integrated circuit mask pattern that can deal with cases where a mask pattern regarding a resistor element does not match a circuit diagram. Regarding verification method.

[Conventional technology]

When designing an integrated circuit, an integrated circuit mask pattern is designed from a circuit diagram. At this time, it is necessary to verify whether the designed mask pattern has equivalent circuit connections to the original circuit diagram. However, as the degree of integration of integrated circuits increases, integrated circuit mask patterns have become extremely complex, and recently, computer-based cross-sections have been used for such verification. That is, the designed mask pattern is digitized to obtain mask pattern data. Then, graphical operations are performed on this to extract connection information between the elements. on the one hand,
Based on the circuit diagram, mutual connection information between elements is imported, and the two are compared and verified to check for any discrepancies.

[Problem to be solved by the invention]

Generally, with respect to a resistor element, there are cases where a circuit diagram and a mask pattern do not correspond one-to-one. This is because even if there is one resistance element on the circuit diagram, it may be replaced with a plurality of resistance elements on the actual mask pattern due to geometrical requirements regarding layout. Such replacement is a common practice in terms of design technology, but in the conventional computer-based verification method described above, the circuit diagram and mask pattern do not have a complete one-to-one correspondence, resulting in a mismatch. will appear.

Conventionally, the circuit diagram had to be modified to match the actual mask pattern for such mismatched locations.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an integrated circuit mask pattern verification method that can deal with the case where there is a mismatch in resistance elements between the mask pattern and the circuit diagram due to design requirements. purpose.

[Means to solve the problem]

The first invention of the present application provides an integrated circuit mask pattern verification method for verifying whether an integrated circuit mask pattern designed based on a circuit diagram is equivalent to the circuit diagram, which comprises: extracting connection information of each element from the circuit diagram; a step of extracting the connection information of each element from the integrated circuit mask pattern as the first connection information; a step of extracting the connection information of each element from the integrated circuit mask pattern as the second connection information;
Extracts connection information about resistive elements, recognizes multiple resistive elements that perform the same function as a single resistive element in an electrical circuit, and replaces these multiple resistive elements with an equivalent single resistive element. The second connection information is modified, and the modified second connection information is compared with the first connection information.

The second invention of the present application is a method for verifying an integrated circuit mask pattern for verifying whether the integrated circuit mask pattern is designed based on a circuit diagram or whether it is equivalent to the circuit diagram. a step of extracting the connection information of each element from the integrated circuit mask pattern as the first connection information; a step of extracting the connection information of each element from the integrated circuit mask pattern as the second connection information;
extracting connection information regarding the resistive element, and giving, for each of both nodes of each resistive element, a first index if the node is connected only to the resistive element, and a second index otherwise; Resistance elements for which both nodes are given the first index or the like are in the first group, resistance elements for which one node is given the first index or the other node is given the second index are in the second group. a step of classifying the resistive elements whose nodes are both given the second index into a third group; and a step of assigning a predetermined priority to each of the nodes of the resistive elements belonging to the first group; Recognizing one of the two nodes as a priority node and the other as a prioritized node, and obtaining replacement information indicating that the prioritized node is to be replaced with the priority node; Of the step of erasing the element connection information and the second connection information,
replacing the connection information of the resistance elements belonging to the second group based on the replacement information; , search for two resistance elements that satisfy the condition that the shared node is not shared by any other resistance element, erase the connection information regarding these two resistance elements, and instead use the shared node of the two erased resistance elements. A step of adding connection information regarding a new resistance element having two nodes other than the nodes as both nodes, and a step of comparing and collating the second connection information corrected in each of the above steps with the first connection information. This is what I decided to do.

[For production]

According to the present invention, a plurality of resistive elements on an integrated circuit mask pattern are replaced with a single equivalent resistive element, and then compared with a circuit diagram. Therefore, even if a single resistor element is replaced with multiple resistor elements when designing a mask pattern, the multiple resistor elements are returned to the original single resistor element before comparison and verification. . Therefore, as a result of comparison and verification, it will no longer be determined that there is a mismatch.

〔Example〕

The present invention will be described in detail below based on illustrated embodiments. 1st
The figure is a diagram showing the procedure of a method for verifying an integrated circuit mask pattern according to an embodiment of the present invention.

First, a circuit diagram is created in step S1, and a mask pattern is designed in step S2 based on this circuit diagram. The purpose of the verification method described here is to check whether the circuit diagram created in step S1 and the mask pattern designed in step S2 are equivalent.

Before explaining the actual verification procedure, a specific example in which a mismatch occurs between a circuit diagram and a mask pattern regarding a resistor element due to design requirements will be described. For example, assume that the circuit diagram created in step S1 is as shown in FIG. This circuit includes transistors T1 to T6,
It is composed of resistive elements R and R'. Here, VDD and VSS in the figure indicate power supplies, and A-F indicate nodes.

Based on this circuit diagram, a mask pattern will be designed in step S2. Now, let us consider the case where a mask pattern for the resistive element R is designed.

There are many ways to design a mask pattern, but if the resistance value of the resistive element R is 6Ω, for example, as shown in Figure 3 (
Patterns such as a) to (C) are possible. Since resistance element R is a 6Ω resistance element provided between nodes B and C, if the design is performed according to the circuit diagram, the result will be as shown in Figure (a).
It is sufficient to provide only one 6Ω resistance element R as shown in FIG. However, due to the geometrical limitations of the layout, the same figure (b
), a pattern in which 3Ω resistive elements R1 and R2 are connected in series with a conductor N] is adopted, or
As shown in , 1Ω resistance elements R1-R6 are connected to conductors N1 to
In some cases, a pattern in which N5 is connected in series may be adopted. The circuit diagrams corresponding to FIGS. 3(a) to (C) are shown in FIG.
Shown in a) to (C). The connection information between nodes BC in the original circuit diagram shown in Fig. 2 matches the connection information in Fig. 4(a), but there is a mismatch with the connection information in Fig. 4(b) and (C). It turns out. In the verification method according to the present invention,
The plurality of resistance elements shown in FIG. 4(b) or (C) are
Recognizing that both perform the same function as the single resistive element shown in Figure (a) as an electric circuit, connection information as shown in Figure (B) or (C) was obtained from the mask pattern. In this case, the connection information is corrected to the one shown in FIG. 3A, and then compared and verified with the original circuit diagram.

In the example described below, the circuit diagram shown in FIG. 2 is created in step S2, and a mask pattern with connection relationships as shown in FIG. The explanation will be given assuming that ΣI has been applied.

That is, for the resistance element R in FIG. 2, the resistance element R in FIG.
), a pattern consisting of five resistance elements r1 to r5 was used, and for resistance element R' in Fig. 2, a pattern consisting of one resistance element r6 as shown in Fig. 5(b) was used. The design has been done.

First, in step S3, the mask pattern is digitized. This is a task of importing a mask pattern as shown in FIG. 3 into a computer as mask pattern data. Subsequently, in step S4, connection information is extracted based on this mask pattern data.

This is done by performing graphical operations on graphical information expressed as mask pattern data (or vector data or bitmap data) and recognizing each element and the connection relationship between each node. In order to recognize each element, it is necessary to set conditions such as, for example, a region consisting of a certain number of diffusion layers is a resistance element, and a region where a certain diffusion layer and a polysilicon layer overlap is a transistor. Since this type of graphical operation is well known, a detailed explanation will be omitted here. The finally obtained connection information is information indicating the connection relationship between each element and the node.

For example, in the circuit of FIG. 5(a), the information that resistance element rl is connected between node B and node X, resistance element r2 is connected between node X and node Y, etc. Connection information.

The connection information of the mask pattern extracted in this way is modified in steps 85 to $8. This modification procedure will be explained in order below. First, in step S5, resistance elements are extracted. This is step S4
From among the connection information of the mask pattern extracted in , only the connection information regarding the resistor element is extracted. As described above, since the connection information includes recognition information of elements such as resistive elements and transistors, it is easy to extract only the connection information regarding the resistive elements. For example, in the example shown in Figure 2, the extracted resistance element is shown in Figure 5 (
There are only resistance elements r1 to r6 shown in a) and (b).

Subsequently, in step S6, each resistance element 11 to "6"
into groups. In order to perform this classification, a first index of 1" or a second index of "0" is assigned to each of both nodes of each resistance element. Here, a certain node is connected only to a resistance element. If the node Both y and z are connected only to the resistance element, and nothing other than the resistance element is connected to this node. Therefore, the index "1" is given to both of these nodes. for,
Nodes B, C, D, and E are connected to a resistive element on one side and a transistor on the other side (see Figure 2).

Therefore, the index 0'' is given to each of these nodes.

FIG. 6(a) is a table 1, d showing the connection information regarding the resistor elements extracted in step S5. The first column of the table shows the name of the resistance element, the second and third columns show the names of the nodes at both ends of this resistance element, and the fourth column shows the index given to both nodes. For example, looking at the row for resistor element rl, both points B and X of this resistor element rl are shown in the second and third columns. Then, “01” in the fourth column means that node B has an index “0”.
However, the index "1" is given to each node X. In this way, indices are given to both nodes for all of the extracted resistance elements. Then, based on this index, each resistance element is classified into three groups. In other words, the resistance elements to which both nodes are given the first index "1" are grouped into the first group.
A second group includes resistive elements in which one node is given a first index "1" and the other node is given a second index "○".
Resistance elements for which both nodes are given the second index 0'' are classified into the third group. This classification is shown in the fifth column of the table.

Next, in step S7, replacement information is created. This replacement information is information indicating that a certain node is replaced with another node. First, the node of the resistance element that has been determined to belong to the first group by the classification in step S6 is extracted, and replacement information is created for this node. As shown in FIG. 6(a), in this embodiment, resistor element r2. r3. Since the three nodes r4 belong to the first group, nodes x, y, and z are extracted. Then, a predetermined priority is given to the extracted nodes. Here, priority is given to the nodes x, y, and z in the alphabetical order. Then, for both nodes of each resistance element belonging to this first group, one is recognized as a priority node and the other is recognized as a priority node, and replacement information is created to replace the priority node with the priority node. Specifically, it is as follows.

(a) Regarding the resistance element r2, a relationship is obtained in which X is a priority node and Y is a priority node, and information that Y→X is replaced is obtained.

(b) Regarding the resistance element r3, a relationship is obtained in which X is the priority node and 6Z is the priority node, and information that it is replaced with Z-X is obtained.

(C) Regarding the resistance element r4, a relationship is obtained in which Y is the priority node and Z is the priority node, and information is obtained that it will be replaced with Z-Y.

To summarize further here, the substitution Z → Y in (C) is
Furthermore, since there is the substitution Y-X in (a), it can be recognized that the final substitution is Z-4X (same as the substitution in (b)). After all, in this example, Y→
A substitution of X and a substitution of Z-+X are created as substitution information.

Once the replacement information is created in this way, the connection information is rewritten in step S8.

This work consists of (1) erasing the connection information of the resistance elements belonging to the first group, (2) replacing the connection information of the resistance elements belonging to the second group, and (3) replacing the connection information of the resistance elements belonging to the second group. It consists of three stages: elimination of shared nodes. This will be explained in order below.

(1) Deleting the connection information of the resistance elements belonging to the first group This operation is performed by deleting the connection information of the resistance elements belonging to the first group from the connection information extracted in step S4 (this is for all elements, not just the resistance elements). This is the task of erasing all connection information of the resistance elements belonging to the group. Looking only at the connection information of the resistance elements, from the information shown in FIG. 6(a), it is found that the resistance elements r2. The connection information of r3°r4 will be deleted.

(2) Replacement of connection information of resistance elements belonging to the second group Subsequently, connection information r of resistance elements belonging to the second group
Regarding l and r5, the replacement information created in step S7 is applied to perform node replacement. That is, the substitution Y→X and the substitution Z-4X are performed. As a result, the connection information for rl does not change, but the connection information for r5 is replaced by Z-+X, so that both nodes change from Z and C to X and C. 6th
Figure (b) is a table showing the state up to this point with respect to the connection information of the resistance elements.

(3) Deletion of shared nodes of resistance elements belonging to the second group Here, first, based on the connection information after replacement, the same nodes are shared among the resistance elements belonging to the second group,
In addition, two resistance elements satisfying the condition that the shared node is not shared by any other resistance element are searched for. Specifically, two resistance elements rl and r shown in FIG. 7(a)
2 satisfies this condition. That is, the resistance element rl
and r2 share the same node P2, and this node P2 is not shared by other resistance elements. Figure 7 (
The two resistance elements rl and r2 shown in b) do not satisfy this condition. This is because both resistance elements are located at the same node P4.
This is because the node P4 is also shared by another resistance element r3. When two resistance elements satisfying these conditions are found, the connection information regarding these two resistance elements is deleted, and a new one is created in which both nodes are two nodes other than the shared node of the two deleted resistance elements. Add connection information regarding the resistor element. Figure 7(a)
In the example, the connection 9 information regarding the resistive elements rl and r2 is erased, and the two nodes other than the shared node PI,
Information regarding a new resistance element having P3 as both nodes will be added.

Let us now return to the above-mentioned embodiment. Now, the connection information regarding the resistor element is as shown in the table of FIG. 6(b). Based on this table, when we search for two resistive elements that have a common node, we find that resistive elements rl and r5 are
It has a shared node X and satisfies the above conditions. Therefore, the connection information of resistive elements rl and r5 is deleted, and instead, information regarding a new resistive element r1' having two nodes B and C as both nodes is added, as shown in the table of FIG. 6(C). You can get connection information.

By going through the three steps (1) to (3) above,
The connection information regarding the resistance element will be modified from that shown in FIG. 6(a) to that shown in FIG. 6(e). In the end, the connection relationship between the nodes BC shown in FIG. 5(a) has been modified to consist only of a single resistance element rl', rather than one consisting of a plurality of resistance elements r1 to r5. . Note that since no changes have been made to the resistance element r6 belonging to the third 0 group, the connection relationship between the nodes DE shown in FIG. 5(b) remains unchanged.

On the other hand, in step S9, connection information is extracted from the circuit diagram. Then, in step S10, the connection information extracted from the circuit diagram and the corrected connection information extracted from the mask button are compared and verified. In the circuit diagram, the second
As shown in the figure, only a single resistance element R is connected between nodes BC, whereas in the mask pattern,
As shown in FIG. 5(a), five resistance elements r1 to r5 are connected between nodes BC. However, as described above, the connection information of this mask pattern is
Since the state is corrected such that only one resistance element r1/ is connected between them, the two match in the comparison in step S10, and no problem occurs.

The integrated circuit mask pattern verification method according to the present invention has been described above based on the circuit of one embodiment. In short, the point of the present invention is that the connection information in steps S5 to S8 surrounded by the dashed-dotted line in FIG. The point is that modifications can be made, and it can be implemented in various ways.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of resistive elements on an integrated circuit mask pattern are replaced with a single equivalent resistive element and compared with a circuit diagram. Even if one resistive element is replaced with a plurality of resistive elements, it will no longer be determined that they do not match as a result of comparison and verification.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the steps of a method for verifying an integrated circuit mask pattern according to an embodiment of the present invention, FIG. 2 is a circuit diagram targeted by the verification method shown in FIG. 1, and FIG. A pattern diagram showing an example in which a resistive element is replaced with multiple resistive elements on a mask pattern, Figure 4 is a circuit diagram corresponding to the pattern in Figure 3, and Figure 5 is designed based on the circuit diagram in Figure 2. Figure 6 is a table for explaining the rewriting of connection information in the verification method shown in Figure 1, and Figure 7 is shown in Figure 1. FIG. 7 is a diagram showing connection relationships of resistive elements for explaining connection information rewriting work in a verification method. A, B, C, D, E, F...nodes,
xyz/node, R, R', R1-R6, r 1-r6
-Resistance element, N1-N5...node, P1-P4...node, T1-T6...transistor.

Claims (2)

[Claims] (1) In an integrated circuit mask pattern verification method for verifying whether an integrated circuit mask pattern designed based on a circuit diagram is equivalent to the circuit diagram, connection information of each element from the circuit diagram is first extracting connection information as connection information; extracting connection information of each element from the integrated circuit mask pattern as second connection information; extracting connection information regarding the resistive element from the second connection information; The step includes the step of recognizing a plurality of resistance elements that perform an equivalent function to a single resistance element, and modifying the second connection information so as to replace the plurality of resistance elements with an equivalent single resistance element. A method for verifying an integrated circuit mask pattern, comprising: comparing the modified second connection information with the first connection information. (2) In an integrated circuit mask pattern verification method for verifying whether an integrated circuit mask pattern designed based on a circuit diagram is equivalent to the circuit diagram, connection information of each element from the circuit diagram is first extracting connection information as connection information; extracting connection information for each element from the integrated circuit mask pattern as second connection information; extracting connection information regarding the resistor element from the second connection information; For each of both nodes of the element, the first index is assigned if it is connected only to the resistive element, and the second index otherwise.
A step of providing an index of , and a first group of resistive elements having a first index assigned to both nodes, and a resistor having a first index assigned to one node and a second index assigned to the other node. a step of classifying the elements into a second group, and classifying the resistance elements whose nodes are both given the second index into a third group; giving a priority, recognizing one of both nodes of each resistance element as a priority node and the other as a prioritized node, and obtaining replacement information indicating that the prioritized node is to be replaced with the priority node; and the second connection information. deleting the connection information of the resistance elements belonging to the first group; and replacing the connection information of the resistance elements belonging to the second group in the second connection information based on the replacement information. and based on the replaced connection information, the resistance elements belonging to the second group share the same node, and
Find two resistance elements that satisfy the condition that the shared node is not shared by any other resistance element, erase the connection information regarding these two resistance elements, and replace the shared node of these two erased resistance elements with a step of adding connection information regarding a new resistance element having two nodes other than the node as both nodes;
A method for verifying an integrated circuit mask pattern, comprising the step of comparing and collating the second connection information modified in each of the steps with the first connection information.