JPH0339424B2 - - Google Patents

Description

[Detailed description of the invention]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data decoding device for decoding data of different numbers of bits from a ternary serial signal input with different numbers of bits within a predetermined time. Conventional configurations and their problems In recent years, digital technology has been introduced into many systems, and with this, means for transmitting digital information are becoming increasingly important. Information transfer means can be roughly divided into parallel transfer means and serial transfer means, but parallel transfer means require many signal lines for input/output during data transfer, and at the same time
Even if the number of input/output pins is increased accordingly, the number of input/output pins will be increased accordingly. Therefore, since there is a proportional relationship between the number of IC pins and cost, parallel transfer methods with a large number of pins are
This is disadvantageous for IC implementation. For this reason, serial transfer means that can reduce costs have been increasingly used in recent years. A data decoding device (Japanese Patent Application No. 57-210778), which is an example of a serial transfer system previously proposed by the present applicant, will be explained with reference to FIGS. 1 to 4. FIG. 1 is a diagram showing the configuration of the data decoding device, and FIG. 2 is a signal waveform diagram used to explain the operation. In FIG. 1, 11 is a three-value discrimination means, 12
13 is a delay means, 13 is a serial-to-parallel conversion means, 14 is a window signal generation means, 15 is a latch means, 16 is a discriminator,
17 is a gate section, and 30 is a determining means. The data decoding device configured as described above is a device for inputting a ternary serial signal sent through a single signal line and extracting parallel binary data from this signal.The operation will be explained below. explain. S3 in FIG. 2 shows a signal input to the data decoding device in FIG. 1. In the figure, i ₁ to i ₅ indicate index signals, and corresponding data d ₁ to d ₅ are allocated to the front part of each index signal as binary values of intermediate level and low level. Now, as an example, a case will be explained in which a ternary serial signal for transferring 5-bit data (00101) is used. When the ternary signal S3 is input to the ternary discrimination means 11, signals shown at S4 and S5 are output. This 3
Table 1 shows the output states of the value discrimination means 11 in response to the inputs.

[Table] A is a three-value serial signal input, two threshold levels are provided, and by converting this into a binary signal, two outputs A ₀ and A ₁ are output as shown in Table 1.
As a result, A ₀ is a signal containing binary data, A ₁
An index signal is output. The binary data signal S4 outputted from the three-value discrimination means 11 enters the delay means 12 and is delayed for a predetermined time to become the delayed binary data signal S6.
Enter 3. Further, the index signal S5, which is another output of the three-value discrimination means 11, is directly input to the serial/parallel conversion means 13. 2 input to the serial/parallel conversion means 13
By using the signal S5 of the two signals S5 and S6 as a clock, the binary data (00101) contained in the signal S6 is extracted in parallel from the outputs D ₀ to D ₄ of the serial/parallel conversion means 13. Additionally, we are taking the following measures to prevent malfunctions. Window signal creation means 14 that uses the first falling edge of the index signal S5 to create a window signal S7 having a predetermined time width that allows decoding processing.
During the window period of the window signal S7, the three-value discrimination means 11
a determining unit 16 that counts the output index signal S5 and determines whether the count value is a predetermined number;
A determination signal S16 is obtained by a determination means 30 comprising a gate section 17 that gates the window signal S7 based on the output S15 of the determination section 16, and this determination signal S1
6, the outputs _D0 to _D4 are latched by the latch means 15, and finally stable binary data output is obtained. Determination means 3 consisting of determination section 16 and gate section 17
The 0 part will be described in more detail below. FIG. 3 shows an example in which the determination means 30 is further specified.
The figure is a signal waveform diagram for explaining this. Here, 18 in FIG. 3 is a discrimination counter, 19 surrounded by a broken line is an R-S flip-flop, and 20 is a
It is an AND gate. During the window period of window signal S7,
The discrimination counter 18 that counts the index signal S5 counts a predetermined number (i ₁ to i ₅ ) of the index signal.
Once counted, the predetermined number detection signal S13 is set to "L", the R-S flip-flop 19 is set, and the discrimination signal S15, which is the output of the discrimination section 16, is set to "H". Further, the discrimination signal S15 is gated by the AND gate 20 together with the window signal S7 which has become "H"
16 determination signal becomes "H". Therefore, the outputs D ₁ to _{D 4} of the serial/parallel conversion means 13 are latched by the latch means 15 by the rising edge of the determination signal S16. If the number of index signals is greater than the predetermined number,
(Predetermined number + 1) A signal "L" indicated by a broken line of the detection signal S14 is output, whereby the R-S flip-flop 19 is reset and the discrimination signal S15 returns to "L". Therefore, the determination signal S16 remains at "L" and no latch is performed. It is also assumed that noise is mixed into the index signal S5 before the determination counter 18 counts the index signal S5 and when the determination signal S15 is in the "H" state. The R-S flip-flop 19 is reset by an index signal S5. Therefore, the R-S flip-flop 19 is reset by the noise, the determination signal S15 changes from "H" to "L", and the gate output signal S16 also changes from "H" to "L". Since the latching operation of the latch means 15 by the gate output signal S16 occurs when the signal S16 changes from "L" to "H", no erroneous latching occurs. That is, even if noise is mixed in, the reset operation is simply repeated, and there is no malfunction of the latch. As described above, in the above example, by providing a determination means consisting of a determination section and a gate section, malfunction of the device due to noise and input error signals is prevented, and it is determined whether or not the number of bits of input data is correct. 2
Value data is extracted as correct data. However, in such an example, even if a ternary serial signal with a predetermined number of bits can be decoded, multiple ternary serial signals with different numbers of bits can be decoded.
Unable to decipher value series signals. In other words, in order to decode ternary serial signals with different numbers of bits, the circuit shown in Figure 1 is required for each different number of bits.
Particularly when converting to IC, there is a problem that the circuit scale becomes large and the cost becomes high. Purpose of the Invention The present invention overcomes the drawbacks of the above examples, and provides a data decoding device that has a single input section for decoding ternary serial signals having different numbers of bits and has a simplified circuit configuration. The purpose is to Structure of the Invention The present invention provides a determination means comprising a three-value discrimination means, a window signal creation means, a delay means, a serial-to-parallel conversion means, a determination section and a gate section that obtain a plurality of outputs,
This is a data decoding device equipped with a plurality of latch means, and it is capable of handling three-value serial signals inputted with different numbers of bits by assigning one bit of binary data to the front or rear of the index signal into a single input section. The circuit configuration is simplified and stable decoding is possible. Furthermore, the present invention replaces the delay means with first and second delay means, and replaces the serial-to-parallel conversion means with first and second serial-to-parallel conversion means. A ternary serial signal input with different numbers of bits in which binary data is assigned bit by bit can be stably decoded by using only one input section and simplifying the circuit configuration. DESCRIPTION OF THE EMBODIMENTS FIG. 5 is a block diagram of a data decoding device according to an embodiment of the present invention, and FIG. 6 is a signal waveform diagram for explaining the operation. In FIG. 5, 11 is a three-value discrimination means, 12 is a delay means, 13 is a serial-to-parallel conversion means, 14 is a window signal generation means, 15a is a 5-bit latch means, and 15b
4-bit latch means, 26 a discrimination section, 27 a gate section, and 50 a judgment means. Note that the three-value discrimination means 11, the delay means 12, the serial-to-parallel conversion means 13, and the window signal generation means 14 are the same as those in the example shown in FIG. 1, so their explanations will be omitted. The data decoding device of the present invention configured as described above is capable of extracting parallel binary data corresponding to the number of bits from a plurality of ternary serial signals having different numbers of bits sent through one signal line. is a device,
The operation will be explained below. The ternary serial signal input to the data decoding device of FIG. 5 is shown in S23 of FIG. As an example, a case will be explained in which a ternary serial signal is used to transfer 5-bit data (00101) and 4-bit data (1011). First, when the 5-bit 3-value serial signal of the 3-value serial signal S23 is input, a binary data signal S24 and an index signal S25 are created as in the example of _FIG . ~D ₄ to 2
Value data (00101) is output. Furthermore, the first
Using the same method as in the example shown in the figure, the discriminator 26 generates a 5-bit discrimination signal S35, and the gate section 27 generates a 5-bit determination signal S36.
The above D ₀ ~ _{D 4} output is changed to 5 by the rising edge of 36.
Bit latch means 15a latches to obtain stable binary data output (00101) at X ₀ , X ₁ , X ₂ , X ₃ , and X ₄ . At this time, the 4-bit discrimination signal S45 is set by detecting the rising edge of the 4th bit of the index signal S25, and is further reset by detecting the falling edge of the 5th bit. For this reason 4
Bit determination signal S46 is only reset and no latch operation is performed. Next, when the 4-bit ternary serial signal of the ternary serial signal S23 is input, a binary data signal S24 and an index signal S25 are created in the same manner.
Binary data (1011) is output from the outputs D ₁ , D ₂ , D ₃ , and D ₄ of the serial/parallel conversion means 13. Thereafter, similarly, a 4-bit discrimination signal S45 is generated in the discrimination section 26, and a 4-bit judgment signal S46 is generated in the gate section 27, and the above-mentioned D ₁ , D ₂ , D ₃ , D ₄ outputs are generated by the rising edge of this 4-bit judgment signal S46. 4-bit latch means 1
Latch at 5b for stable binary data output (1011)
are obtained by Y ₁ , Y ₂ , Y ₃ , and Y ₄ . Incidentally, at this time, the 5-bit discrimination signal S35 is simply reset and held at "L". For this reason 5
The bit determination signal S36 is also only reset and no latch operation is performed. The distinguishing section 26 and the gate section 27, which are particularly different from the example shown in FIG. 1, will be explained in more detail below. FIG. 7 shows an example in which the determination means 50 comprising the determination section 26 and the gate section 27 is further embodied. Here, 28 in FIG. 7 is a discriminating counter for discriminating whether the ternary serial signal has 4 bits or 5 bits; 19 surrounded by a broken line;
29 is an R-S flip-flop, and 20 and 40 are AND gates forming a gate section. When determining whether the input of the index signal S25 and the window signal S7 is 5-bit data, first, the determination counter 2 is used as in the example of FIG.
Predetermined number of detection signals S1 for detecting 5 bits of 8 outputs
Using the detection signal S14 for detecting 3 and 6 bits (predetermined number + 1), the R-S flip-flop 19 is set or reset to generate the 5-bit discrimination signal S35.
This is determined by creating a And 5
The AND gate 20 uses the bit discrimination signal S35.
gates the window signal S7 at 5-bit latch means 1.
5a input 5-bit judgment signal S36 is created. Next, when determining whether the data is 4 bits or not, similarly, a predetermined number detection signal S33 for detecting 4 bits of the output of the discrimination counter 28 and a detection signal S34 for detecting 5 bits (predetermined number + 1) are used. ,R-
Discrimination is made by setting or resetting the S flip-flop 29 and creating a 4-bit discrimination signal S45. Then, using the discrimination signal S45, the AND gate 40 gates the window signal S7,
A 4-bit judgment signal S46 is generated to be input to the 4-bit latch means 15b. As described above, according to this embodiment, the ternary discrimination means, the delay means, the window signal creation means, the serial/parallel conversion means, and the determining means for determining whether or not a plurality of ternary serial signals have a predetermined number of bits are provided. By providing a gate means for creating a plurality of gate output signals and a plurality of latch means for latching each binary data of a ternary serial signal using a plurality of gate output signals, a ternary serial signal having a plurality of different numbers of bits can be generated. Signals can be extracted as stable binary data using only one input terminal. In this embodiment, we have explained the case of decoding two types of ternary serial signals, 4 bits and 5 bits, but it goes without saying that multiple types of data can be decoded as long as the ternary serial signals have different numbers of bits. stomach. Furthermore, in this embodiment, a ternary serial signal in which binary data is assigned to the front part of the index signal is used as an input signal, but it may be a ternary serial signal in which binary data is assigned to the rear part of the index signal. . In this case, the index signal S25 in FIG.
is input to the delay means 12 to be delayed, and the output of this delay means 12 and the binary data signal S24 are input to the serial/parallel conversion means 13 and extracted from the binary data D ₀ to D ₄ output, and the rest is similar. This can be achieved through configuration. Furthermore, a ternary serial signal in which binary data is assigned to the front and rear parts of an index signal can be considered as an input signal, but as a conventional example of handling this signal, Japanese Patent Application No. 58-4506 filed earlier by the present applicant There is. In order to obtain the same effect using this signal as an input signal, a three-value discrimination means similar to that in Japanese Patent Application No. 58-4506, a window signal creation means, a binary data signal output from the three-value discrimination means, and an index signal are required. first delay means and second delay means for respectively delaying the first delay means, first serial-to-parallel conversion means for extracting odd bits of the binary data in parallel from the output of the first delay means and the index signal, and second delay means. and a second serial/parallel conversion means for extracting even numbered bits of the binary data from the binary data signal in parallel, and counting the index signal used in the embodiment to convert the output of the ternary serial signal. determining means for determining the number of bits and obtaining a plurality of determination signals; gate means for gating the window signal using the output of the determining means to obtain a plurality of gate output signals; By adding a plurality of latch means for latching the output of the two-serial to parallel conversion means, it is possible to take out an output corresponding to the number of bits of the ternary serial signal from the plurality of latch means, as in the present embodiment. Effects of the Invention The data decoding device of the present invention includes three-value discrimination means,
By providing a delay means, a window signal generation means, a serial/parallel conversion means, a plurality of output determination means, a plurality of output gate means, and a plurality of output latching means, one It is possible to stably decode a ternary serial signal inputted with a different number of bits in which binary data is allocated bit by bit by using a single input section, simplifying the circuit configuration. Furthermore, the data decoding device of the present invention includes a ternary discrimination means, a first delay means, a second delay means, a window signal generation means, a first serial-to-parallel conversion means, a second serial-to-parallel conversion means, and a plurality of By providing an output determination means, a plurality of output gate means, and a plurality of latch means, it is possible to generate a three-value series input with different numbers of bits, in which one bit of binary data is assigned to the front and rear parts of the index signal. By using only one signal input section, the circuit configuration can be simplified and stably decoded.
Its practical effects are great.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the data decoding device proposed earlier, Fig. 2 is a signal waveform diagram for explaining the operation of the data decoding device, and Fig. 3 is details of the determination means and gate means in the data decoding device. FIG. 4 is a signal waveform diagram for explaining the operation of the determining means and gate means, FIG. 5 is a block diagram of a data decoding device according to an embodiment of the present invention, and FIG. 6 is a block diagram showing the same. FIG. 7 is a signal waveform diagram for explaining the operation of the data decoding device of the embodiment. FIG. 7 is a block diagram showing the detailed configuration of the determination means and gate means in the embodiment. 11... Three-value discrimination means, 12... Delay means, 13...
Serial-to-parallel conversion means, 14... Window signal creation means, 15...
Latch means, 15a...5 bit latch means, 15
b... 4-bit latch means, 16, 26... determination section,
17, 27... Gate section, 18, 28... Discrimination counter, 19, 29... R-S flip-flop, 2
0, 40...AND gate, 30, 50...determination means.

Claims (1)

[Scope of Claims] 1. The binary data signal is assigned one bit at a time to the front or rear part of an index signal corresponding to the number of bits of the binary data signal, and the data is transferred and input with a different number of bits at predetermined intervals. ternary discrimination means for discriminating a ternary serial signal to separate the index signal and the binary data signal; and a trigger triggered by the first rising or falling edge of the binary data signal output from the ternary discriminating means. and the time width from the timing of the trigger to the final timing of the ternary serial signal when the binary data signal has the maximum number of bits, and to the timing before the next ternary serial signal arrives. a window signal creating means for creating a window signal having the following characteristics; a delay means for delaying the binary data signal which is the output of the three-value discrimination means to obtain a delayed binary data signal; and an index which is the output of the three-value discrimination means. serial-to-parallel conversion means for latching the delayed binary data signal output from the delay means and extracting the delayed binary data signal in parallel according to the signal; A discriminating means obtains a plurality of discriminating signals corresponding to each number of bits based on an index signal output from the means, and detecting the plural discriminating signals based on the trailing edge timing of the window signal, and detecting the discriminating signals included in the incoming three-value serial signal. a determining means including a gate means for outputting only a specific determining signal corresponding to the number of bits of the binary data signal being outputted as a determining signal; and a plurality of latch means, each of which operates only in response to the determination signal and outputs only a binary data signal having a specific number of bits included in the three-value serial signal. data decoding device.