JPH033952B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit device, and more particularly to a method for manufacturing a semiconductor integrated circuit device including a high-speed bipolar transistor.

Semiconductor integrated circuit devices include PNP transistors,
NPN transistor etc. are integrated.
Generally, the switching speed of NPN transistors can be increased, but PNP transistors have a complicated structure or are formed laterally, which has the drawback that high switching speeds cannot be achieved. Therefore, a semiconductor integrated circuit device including a PNP transistor and an NPN transistor has many limitations in terms of the circuit when viewed as a whole due to the speed imbalance between the two transistors.

FIG. 1 shows a conventional semiconductor integrated circuit device in which a PNP transistor is integrally formed using a manufacturing process for an NPN transistor, which is a standard for integrated circuits.

In FIG. 1, 1 is a p-type substrate, 2 is a high concentration n
3 is an n-type epitaxial layer, and 4 is a preliminary isolation diffusion layer. 5 is a separation diffusion layer formed from the surface of the epitaxial layer 3, and is a preliminary separation diffusion layer 4.
It is connected in the middle to separate the active region.

6e, 6c, and 7b are p-type diffusion layers. Here, in the NPN transistor portion, 7b is a p-type region serving as a base, and in the lateral PNP transistor portion, 6e and 6c form an emitter and a collector, respectively. 8b is the contact for the base region of the PNP transistor, 9e is the contact for the base region of the PNP transistor, and 9e is the contact for the base region of the PNP transistor.
The emitter of the NPN transistor, 9c is a high concentration n for the collector contact of the NPN transistor.
It is a shaped diffusion layer. In Fig. 1, the integrally formed
In NPN and PNP transistors, the base width (distance between regions 6e and 6c) of the PNP lateral transistor is determined in a plane, that is, by the pattern accuracy of the mask. Generally, the mask accuracy is not very accurate, and the short one is usually about 3 μm. Therefore, a PNP transistor with a narrow base width cannot be formed. Furthermore, since the base region 7b of the NPN transistor has a concentration gradient due to diffusion, an electric field gradient is formed in the base region, so carriers are accelerated and high speed is achieved. However, the base region 3 of the PNP transistor
is an epitaxial layer itself, and there is no concentration gradient, making it impossible to achieve high speed. Furthermore, the concentration of the collector region 6c of the PNP transistor is higher than that of the base region 3, and when the base width is reduced, the breakdown voltage between the collector and emitter decreases rapidly.

As mentioned above, the PNP transistor in Figure 1 can be integrated without adding any additional manufacturing process, but the PNP transistor in Figure 1 has a wide base.
Horizontal PNP transistors usually have significantly inferior characteristics compared to vertical NPN transistors for three reasons: the diffusion profile does not create an electric field gradient, the collector concentration of the PNP transistor is higher than the base concentration, and the withstand voltage is lower. . Therefore, the semiconductor integrated circuit device shown in FIG. 1 has insufficient characteristics as a whole.

Next, FIG. 2 shows a conventional example of a semiconductor integrated circuit device that has improved this. In the case of Fig. 2, a manufacturing process is added and a vertical PNP transistor is integrally formed.

In FIG. 2, 11 is a p-type substrate, 12 is a high concentration n-type buried layer, 13 is an n-type epitaxial layer, 1
4 is a p-type preliminary separation diffusion layer, and 15 is a separation diffusion layer. The active regions are separated by the isolation diffusion layers 14 and 15. 16 is a p-type region manufactured by ion implantation method etc. on the n-type buried layer 12, and is a vertical type region.
This is the region that becomes the collector of the PNP transistor.
17 and 18 are formed simultaneously when forming the isolation diffusion layers 14 and 15, respectively, and serve as lead-out diffusion layers for the collector region 16. 19 is a drawer diffusion layer of the base 13. 20 is a p ⁺ diffusion layer formed at the same time as the separation diffusion layer 15, and is a vertical PNP.
This is the area that becomes the emitter of the transistor. 21
is the emitter layer of a normal NPN transistor, 22
23 is a base layer, and 23 is a collector contact portion formed at the same time as the emitter 21.

Now, in FIG. 2, a vertical PNP transistor is formed by the p ⁺ emitter diffusion layer 20, the n type epitaxial layer 13 serving as a base, and the p ⁺ type collector layer 16. This PNP transistor differs from the lateral ^PNP transistor shown in FIG ^. Since it depends on the depth of the emitter diffusion layer 20, there is an advantage that the base width can be narrowed by diffusion control. However, this structure also has many drawbacks. First of all, the base width is determined by the thickness of the epitaxial layer 13, the diffusion depth of the emitter 20, and the p-type collector region 16.
subtracting the upper diffusion width of the base width, the distribution of the base width is very large. In addition, the concentration of the p-type collector region 16 is higher than that of the buried layer 12.
Therefore, the upward diffusion is not uniquely determined by the doping amount of the p-type collector region 16, and therefore the base width distribution becomes wider and wider. Although it is not limited by pattern accuracy, it is difficult to determine and control the base width. Moreover, in this transistor as well, the epitaxial layer is the base and the first layer is the base layer.
The drawbacks of the PNP transistor shown in the figure, namely, that there is no concentration gradient in the base region and that the concentration of the collector 12 is higher than that of the base, have not been improved. That is, this transistor also has three problems: it is difficult to determine and control the base width, there is no concentration gradient, and the breakdown voltage is low.

The present invention has been made in view of the conventional drawbacks.
An object of the present invention is to form a high-speed PNP bipolar transistor and a crossover element, and to provide a semiconductor integrated circuit device including the same and a high-performance NPN bipolar transistor using a process advantageous method. That is, the present invention combines the low speed of the lateral PNP bipolar transistor shown in Figure 1 with the vertical type shown in Figure 2.
In addition to improving the base width of PNP bipolar transistors, which cannot be determined with good controllability and the withstand voltage,
The present invention aims to provide a method that enables integrated formation of a semiconductor integrated circuit device including an NPN bipolar transistor without significantly increasing the number of manufacturing steps. Furthermore, it is an object of the present invention to provide a method for manufacturing a semiconductor integrated circuit device which, in addition to the above-mentioned method, allows a crossover element to be integrally formed at the same time.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 3 shows a cross-sectional view of the structure of a semiconductor integrated circuit device formed by a method according to an embodiment of the present invention. In this example, a vertical PNP transistor, a vertical NPN transistor, and a crossover element are integrally formed.
The PNP transistor part has been improved and integrated.

In FIG. 3, 31 is a p-type semiconductor substrate, 32
33 is an n-type epitaxial layer of about 0.5 to 1.0 Ωcm grown to a thickness of 3 to 4 μm. Reference numeral 34 designates a p-type high concentration preliminary diffusion buried region, which pairs with the p-type high concentration diffusion region 35 formed from the surface of the epitaxial layer 33, separates the epitaxial layer 33, and serves as a PNP bipolar transistor forming region and a crossover region. It forms the element formation region and the collector region of the NPN transistor. Even if these isolation regions 34 and 35 are formed by oxide film isolation, the effects of the present invention will not change. 36 is a p-type high concentration buried region, which is buried region 3.
2 and formed at the same time as the separation area 34. The surface concentration of the high concentration buried region 36 is
The buried region 32 on the substrate 31 is quite low due to the high concentration, so there is less upward diffusion and it does not rise as high as the diffusion region 34. 37 is a p ⁺ diffusion region formed at the same time as diffusion region 35;
This was installed to reduce collector resistance. 38 is an n ⁺ diffusion region connected to the buried region 32 . 39 is one of the main regions formed in the present invention, and is formed by a low-dose ion implantation method, and has a sheet resistance value of 2KΩ/mm, which is more than an order of magnitude higher than the base resistance of a normal NPN transistor, which is 200Ω/mm. It is a p ^- region of ~4KΩ/approximately PNP
This becomes the collector region of the transistor. Reference numeral 40 denotes a p ^- region formed at the same time as the collector region 39, in which a wiring crossover element is formed. 41
is an n-type well, which is one of the main areas of the present invention,
It is formed in the p ^- region 39 by ion implantation and becomes the n-type base region of the PNP transistor. 42 is an n-type well formed at the same time as the base region 41 and forms a crossover element. 43 is a p-type region of about 200 Ω/hole formed in the n-type base region 41, which is the emitter region of the PNP transistor, and is simultaneously formed in the p-type base region 44 formed in the collector region of the vertical NPN transistor. It is formed.
45 is a contact diffusion region for the p ^- region 40 of the crossover element, which is formed at the same time as regions 43 and 44. 46 is an n-type contact diffusion region of the base region 41, which is formed at the same time as the emitter region 47 of the NPN transistor. 48 is an n-type contact region of the collector 33 of the NPN transistor. At the same time, a diffusion region 49 is formed, which together with the n-type well 42 constitutes a crossover element.

As is clear from the above explanation and Figure 3,
p-type emitter region 43, n-type base region 41, p
A vertical PNP transistor is formed by the shaped collector region 39, a vertical NPN transistor is formed by the n-type emitter region 47, the p-type base region 44, and the n-type collector region 33, and the n ^- type region 42 and the n ⁺ -type region 49 form a vertical NPN transistor. It can be seen that a crossover element is formed.

FIG. 4 shows the characteristics of the vertical PNP transistor formed by the above method. Vertical type in Figure 3
The explanation will be based on the impurity concentration distribution in the depth direction of each region of the PNP transistor. It will be explained that the problems of the conventional PNP transistors shown in FIGS. 1 and 2 can be solved. An n-type region 41, which is a base, is formed within the lightly doped p ^- collector region 39,
A narrow base width can be obtained, and the concentration and depth of the p-type impurity can be precisely determined by implanting impurity ions from above the p ^- region 39, and the p-type emitter region can be formed in the same way. . Therefore, the base width (the distance from the lower part of the emitter region 43 to the lower part of the base region 41) is determined only by controlling the impurities in the n-type base region 41 and the p-type emitter region 43, so that controllability is improved. is good. In other words, in the case of FIG. 2, there were three parameters, but in this example, there are two
Two parameters determine the base width. Also,
Since the n-type base region 41 is ultimately determined by impurity drive-in after ion implantation,
As is clear from Figure 4, there is a concentration gradient that decreases from top to bottom, and the structure is such that electric field acceleration is performed, so the traveling speed of the carrier increases and high-speed operation is possible. n ⁺
A base contact can be reliably formed in the base contact region 46. Furthermore, as is clear from FIG. 4, the concentration of the p-type collector region 39, which becomes the collector, is different from the conventional one, and is lower in concentration than the base region.
Since it is p ^- , the breakdown voltage is high, and the high concentration p-type region 3
6, the collector resistance can be lowered.

Furthermore, the features of the vertical PNP transistor shown in FIG. 3 will be described with reference to FIG. 4, which shows the impurity distribution in the depth direction. In FIG. 4, the buried region 32 is made of a material with a small diffusion coefficient, such as As (arsenic), and the p-type region 36 is made of boron, etc., thereby illustrating upward diffusion from the substrate 31. It becomes like this. Further, the p-type emitter region 43, the n-type base region 41, and the p-type collector region 39 having a lower concentration than the region 36 are formed with good controllability by implanting boron, phosphorus, etc., respectively, by ion implantation and subsequent heat treatment. As is clear from FIG. 4, the n-type base region 41, which has a higher concentration than the region 39, has a large concentration gradient, and an electric field gradient is obtained at the base. Furthermore, since the collector region 39 can be made with an extremely low concentration, the depth of the base region 41 is determined by the amount of impurity added to the base and the emitter region 4.
Since it is substantially determined by both the impurity amounts of No. 3 and does not depend on the impurity concentration of the collector region 39, there is no difficulty in controlling it.

A crossover element is formed simultaneously with the above PNP transistor. Electrode contacts of the crossover element are connected to both ends of the n ⁺ diffusion region 49, and wiring made of aluminum or the like crosses over the oxide film (not shown) between them.

The crossover element as in this embodiment has the following advantages.

(1) A low concentration n region 42 is placed at the junction interface between the p ^- island region 40 and the crossover region 49 in the crossover region.
Since the diffusion layer of the crossover region 49 is substantially deep, the influence of the edge effect is small and the junction breakdown voltage is high.

(2) As described above, since the semiconductor region 42 has a junction surface with a low concentration, the parasitic junction capacitance of the crossover element is small, and signal attenuation can be reduced.

(3) Since the p ^- island region 40 in the crossover section is a deep diffusion layer, the width below the crossover region 49 is wide, which reduces the effects of punch-through or defects, and improves the yield of crossover elements. do.

By the way, when the p ⁺ type buried region 36 is formed under the p ^- island region 40 of the crossover element, the effect described in (3) is further improved.

Further, in the structure according to this embodiment, the crossover island region 40 and the collector region 39 of the PNP transistor are formed in a common process, and the base region 44 of the NPN transistor is formed in the emitter region 43 of the PNP transistor and the island region 40 of the crossover element. Since it is formed in the same process as the contact 45, in order to form a vertical PNP transistor,
The new process is simply an addition of a process for forming the base n-type region 41 and the crossover region 42, resulting in a very simple structure.

As described above, the present invention significantly increases the number of manufacturing steps to produce a high-voltage, high-speed, high-density vertical PNP transistor, a high-speed vertical NPN transistor, and a low parasitic capacitance crossover element suitable for high density. It can be integrally formed without any problems, and has excellent industrial effects in manufacturing high-voltage, high-speed semiconductor integrated circuits.

[Brief explanation of the drawing]

Figures 1 and 2 are structural cross-sectional views of a conventional semiconductor integrated circuit device, and Figure 3 is a structure in which a vertical PNP transistor, a vertical NPN transistor, and a crossover element are integrated using the method of an embodiment of the present invention. A cross-sectional view of the structure of a semiconductor integrated circuit device, Figure 4 is a vertical version of Figure 3.
FIG. 3 is an impurity distribution diagram of a PNP transistor. 39,40...p ^- area, 41,42...n-area, 43,44,45...p-area, 46,47,
48, 49...n ⁺ area.

Claims (1)

[Claims] 1 PNP consisting of an n-type epitaxial layer and having n-type and p-type buried regions on a p-type semiconductor substrate
a transistor forming region, a collector region of a vertical NPN transistor having an n-type buried region made of the n-type epitaxial layer, and an island region of a crossover element; forming a p-type collector region of the PNP transistor and a p-type low concentration region of the crossover element each having a lower concentration than the p-type buried region by ion implantation;
The collector region of the PNP transistor and the p-type low concentration region of the crossover element are each provided with an n-type base region having a concentration gradient that is higher in concentration than the collector region of the PNP transistor and decreases downward from the surface, and the cross-over element. A first crossover region of the over element is formed by ion implantation, and the n-type base region and the collector region of the NPN transistor each have a higher concentration than the n-type base region.
type emitter region and p of the NPN transistor
forming a base region of the n-type base region, the base region of the NPN transistor and the first base region;
A method for manufacturing a semiconductor integrated circuit device, comprising forming an n-type base contact region, an n-type emitter region of the NPN transistor, and a second crossover region in each of the crossover regions.