JPH0339633B2 - - Google Patents
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- Publication number
- JPH0339633B2 JPH0339633B2 JP59177428A JP17742884A JPH0339633B2 JP H0339633 B2 JPH0339633 B2 JP H0339633B2 JP 59177428 A JP59177428 A JP 59177428A JP 17742884 A JP17742884 A JP 17742884A JP H0339633 B2 JPH0339633 B2 JP H0339633B2
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- Prior art keywords
- circuit
- voltage
- semiconductor elements
- semiconductor
- time
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Description
【発明の詳細な説明】
〔発明の技術的分野〕
本発明は半導体素子と非線形抵抗体を並列に接
続した回路を複数個直列に構成した電圧調整回路
の半導体素子あるいは非線形抵抗体の故障検出装
置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a failure detection device for a semiconductor element or a nonlinear resistor of a voltage regulating circuit configured in series with a plurality of circuits in which a semiconductor element and a nonlinear resistor are connected in parallel. Regarding.
半導体素子と非線形抵抗体を並列に接続した回
路を複数個直列に構成し、半導体素子のオン・オ
フ制御により回路の電圧降下を利用して電圧調整
を行なうことが出来る。第３図はその様な電圧調
整回路のブロツク図であり、第４図はタイミング
チヤートである。
A plurality of circuits in which a semiconductor element and a nonlinear resistor are connected in parallel are configured in series, and the voltage drop in the circuit can be used to adjust the voltage by controlling the semiconductor elements on and off. FIG. 3 is a block diagram of such a voltage regulating circuit, and FIG. 4 is a timing chart.
図において１は電圧調整回路、２１〜２４は半
導体素子、３１〜３４はスナバ抵抗、４１〜４４
はスナバコンデンサ、５１〜５４は非線形抵抗、
６１，６２は分圧用抵抗、７は電圧検出回路、８
は直流電源、９は負荷抵抗であり１０は半導体制
御回路、１１はタイムデイレイ回路、１２はイン
バータ、１３はアンド回路である。ａは運転信
号、ｂは故障検出信号であり、a′はタイムデイレ
イ回路１１の出力でである。 In the figure, 1 is a voltage adjustment circuit, 21-24 are semiconductor elements, 31-34 are snubber resistors, 41-44
is a snubber capacitor, 51 to 54 are nonlinear resistors,
61 and 62 are voltage dividing resistors, 7 is a voltage detection circuit, and 8
1 is a DC power supply, 9 is a load resistor, 10 is a semiconductor control circuit, 11 is a time delay circuit, 12 is an inverter, and 13 is an AND circuit. a is an operating signal, b is a failure detection signal, and a' is an output of the time delay circuit 11.
第３図で半導体素子２１〜２４はオフしている
とすると直流電源８の電流は、非線形抵抗３１〜
３４を介して負荷抵抗９に流入する。この時負荷
抵抗９に流入する電流ILは、直流電源８の電圧を
Ｅ、非線形抵抗５１〜５４の制限電圧を各々ｖ、
負荷抵抗９の抵抗値をRLとすれば、IL（Ｅ−
4v）／RLとなる。ここで半導体素子２１をオン
すると負荷電流ILはIL＝（Ｅ−3v）／RLとなる。
この様に負荷電流ILを増加する時は半導体素子を
順次オンし、また、負荷電流ILを減少する時には
オンしている半導体素子をオフすることにより負
荷電流ILの制御が可能となる。この制御を行なう
のが半導体制御回路１０である。 Assuming that the semiconductor elements 21 to 24 are off in FIG. 3, the current of the DC power supply 8 is
34 into the load resistor 9. At this time, the current I L flowing into the load resistor 9 represents the voltage of the DC power supply 8 as E, the limiting voltage of the nonlinear resistors 51 to 54 as V, respectively.
If the resistance value of the load resistor 9 is R L , then I L (E-
4v)/R L. Here, when the semiconductor element 21 is turned on, the load current I L becomes I L =(E-3v)/ RL .
In this way, when increasing the load current I L , the semiconductor elements are turned on one after another, and when decreasing the load current I L , the semiconductor elements that are on are turned off, making it possible to control the load current I L. . The semiconductor control circuit 10 performs this control.
また半導体素子２１〜２４、あるいは非線形抵
抗体５１〜５４の故障を検出するために、直列接
続された分圧用抵抗６１，６２を電圧調整回路に
並列に接続して、ブリツジを構成し、電圧調整回
路及び分圧回路の各々の中間点からブリツジ回路
の出力電圧を得て、この電圧を電圧検出回路７で
検出し、半導体素子２１〜２４の故障を検出して
いる。 In addition, in order to detect failures in the semiconductor elements 21 to 24 or the nonlinear resistors 51 to 54, voltage dividing resistors 61 and 62 connected in series are connected in parallel to the voltage adjustment circuit to form a bridge and adjust the voltage. The output voltage of the bridge circuit is obtained from the intermediate point of each of the circuit and the voltage dividing circuit, and this voltage is detected by the voltage detection circuit 7 to detect a failure of the semiconductor elements 21 to 24.
即ち、非線形抵抗５１〜５４はそれぞれほぼ同
一の値であり、又、分圧用抵抗６１と６２はほぼ
同一の値、スナバ抵抗３１〜３４も同一の値、ス
ナバコンデンサ４１〜４４も同一の値であるの
で、半導体素子と、非線形抵抗が正常であれば、
ブリツジ回路の出力電圧はほぼ零であるが、半導
体素子２１、あるいは非線形抵抗５１が故障し、
短絡状態となると、ブリツジ回路の平衡が失なわ
れ、電圧検出回路７で検出できる。なお、当然の
ことながら故障検出は半導体素子２１〜２４がオ
フ状態の時に行なわなければならない。 That is, the nonlinear resistors 51 to 54 have substantially the same value, the voltage dividing resistors 61 and 62 have substantially the same value, the snubber resistors 31 to 34 have the same value, and the snubber capacitors 41 to 44 have the same value. Therefore, if the semiconductor element and nonlinear resistance are normal,
The output voltage of the bridge circuit is almost zero, but if the semiconductor element 21 or the nonlinear resistor 51 breaks down,
When a short circuit occurs, the balance of the bridge circuit is lost, which can be detected by the voltage detection circuit 7. Note that, as a matter of course, failure detection must be performed when the semiconductor elements 21 to 24 are in the off state.
しかし、今、第４図に示す様に本電圧調整回路
をT0からT1までの期間運転し時刻T1ですべての
半導体素子をオフ状態とし運転を停止したとして
も、運転中である時刻T1の直前は電圧調整のた
めすべての半導体素子がオン状態、あるいはオフ
状態にあるとはかぎらず、各々の半導体素子の電
圧分坦が異なつている。従つてすべての半導体素
子２１〜２４あるいは非線形抵抗体５１〜５４が
正常であつても、運転停止時刻T1直後は、スナ
バコンデンサ４１〜４４にたくわえられている電
荷量の相異からブリツジ回路の平衡が失なわれ、
ブリツジ回路の出力電圧が零とならず、故障であ
ると判定する可能性がある。スナバコンデンサ４
１〜４４の電荷の放電はスナバ回路と並列に接続
されているエレメントのインピーダンスが大き
く、放電時定数が大きくなるので誤まりのない故
障検出を行なうためにはタイムデイレイ回路１１
の遅延時間を数分以上にしなければならないとい
う欠点があつた。 However, even if this voltage adjustment circuit is operated for a period from T 0 to T 1 as shown in Fig. 4, and all semiconductor elements are turned off at time T 1 and the operation is stopped, even if Immediately before T 1 , not all semiconductor elements are necessarily in an on state or an off state due to voltage adjustment, and the voltage distribution of each semiconductor element is different. Therefore, even if all the semiconductor elements 21 to 24 or the nonlinear resistors 51 to 54 are normal, immediately after the operation stop time T1 , the bridge circuit is equilibrium is lost,
There is a possibility that the output voltage of the bridge circuit will not become zero and it will be determined that there is a failure. Snubber capacitor 4
When discharging the charges 1 to 44, the impedance of the element connected in parallel with the snubber circuit is large and the discharge time constant becomes large.
The disadvantage is that the delay time must be several minutes or more.
従つて本発明の目的は、前述の点に鑑みなされ
たものであつて、運転中の半導体素子の状態がい
かなる状態であつても、運転停止後短時間のうち
に誤動作のない半導体素子あるいは非線形抵抗体
の故障を検出出来る故障検出装置を提供すること
にある。
Therefore, an object of the present invention has been made in view of the above-mentioned points, and the object of the present invention is to develop a semiconductor device that does not malfunction or is non-linear within a short period of time after the operation is stopped, regardless of the state of the semiconductor device during operation. It is an object of the present invention to provide a failure detection device capable of detecting a failure of a resistor.
本発明はこの目的を達成するために、電圧調整
回路の運転停止後、休止期間中にただちに電圧調
整回路の全半導体素子を所定の期間オンし、スナ
バコンデンサにたくわえられた電荷量を短時間の
うちに等しくし、運転停止後短時間で誤動作する
ことなく半導体素子あるいは非線形抵抗の故障を
判別できる様にしたことを特徴とするものであ
る。
In order to achieve this object, the present invention turns on all the semiconductor elements of the voltage regulation circuit for a predetermined period immediately after the operation of the voltage regulation circuit is stopped, and during the rest period, to discharge the amount of charge stored in the snubber capacitor for a short period of time. The present invention is characterized in that it is possible to determine a failure of a semiconductor element or a nonlinear resistor without malfunction within a short time after the operation is stopped.
本発明の一実施例を第１図に示す。第１図にお
いて第３図と同一機能を有するものは同一番号と
し説明は省略する。
An embodiment of the present invention is shown in FIG. Components in FIG. 1 having the same functions as those in FIG. 3 are designated by the same numbers, and their explanations will be omitted.
第１図において１５はダウンエツジでトリガさ
れるワンシヨツト回路であり、１４，１６はOR
回路である。 In Figure 1, 15 is a one-shot circuit triggered by a down edge, and 14 and 16 are OR circuits.
It is a circuit.
第２図は本発明の動作を表すタイミングチヤー
トである。 FIG. 2 is a timing chart showing the operation of the present invention.
以下、第１図、第２図により本発明の作用を説
明する。 The operation of the present invention will be explained below with reference to FIGS. 1 and 2.
今、第１図の電圧調整回路１を運転信号ａによ
り第２図に示される様にT0からT1までの時刻・
動作させたとする。T0〜T1までの期間は電圧調
整を行なつているので、半導体素子２１〜２４は
どの素子がONでどの素子がOFFであるか、はわ
からず、運転停止時刻T1の直後は各々の半導体
素子の分坦電圧は異なつていると考えられる。そ
こで時刻T1の直後時刻T2からT3までの所定の期
間ダウンエツジでトリガされるワンシヨツト回路
１５によりパルスを出し、電圧調整回路１のすべ
ての半導体素子２１〜２４をオン状態とする。時
刻T2で半導体素子２１〜２４がオン状態となる
と、スナバ抵抗３１〜３４を介してスナバコンデ
ンサ４１〜４４の電荷が放電され百μS程度でス
ナバコンデンサ４１〜４４の分担電圧は等しく零
となる。そこで時刻T3で、半導体素子２１〜２
４を一斉にオフすれば、半導体素子２１〜２４と
非線形抵抗５１〜５４がすべて健全であればブリ
ツジ回路は平衡を保ち、電圧検出回路７は出力零
であり、もし、半導体素子２１〜２４あるいは非
線形抵抗５１〜５４に異常が存在するならば、ブ
リツジ回路の平衡がくずれ、電圧検出回路７は、
故障を検出することができる。従つて、電圧検出
回路７の出力を時刻T3以降とりこむことにすれ
ば誤まりのない故障検出信号ｂを得ることができ
る。T2〜T5までの期間はスナバ抵抗とスナバコ
ンデンサによる時定数から、スナバコンデンサが
十分に放電できる時間をとる様にすればよい。 Now, the voltage adjustment circuit 1 in FIG .
Let's say it works. Since the voltage is adjusted during the period from T0 to T1 , it is not known which of the semiconductor elements 21 to 24 is ON and which element is OFF, and immediately after the operation stop time T1 , each of the semiconductor elements 21 to 24 is It is thought that the polarization voltages of the semiconductor devices are different. Therefore, the one-shot circuit 15 which is triggered by the down edge outputs a pulse for a predetermined period from time T2 to time T3 immediately after time T1 to turn on all the semiconductor elements 21 to 24 of the voltage adjustment circuit 1. When the semiconductor elements 21 to 24 are turned on at time T2 , the charges in the snubber capacitors 41 to 44 are discharged through the snubber resistors 31 to 34, and the voltages shared by the snubber capacitors 41 to 44 become equal to zero in about 100 μS. . Therefore, at time T3 , semiconductor elements 21 to 2
If semiconductor elements 21 to 24 and nonlinear resistors 51 to 54 are all healthy, the bridge circuit will maintain balance and the voltage detection circuit 7 will have zero output. If there is an abnormality in the nonlinear resistors 51 to 54, the bridge circuit will be unbalanced, and the voltage detection circuit 7 will
Failures can be detected. Therefore, by taking in the output of the voltage detection circuit 7 after time T3 , it is possible to obtain a failure detection signal b without error. During the period from T 2 to T 5 , the time constant for the snubber resistor and the snubber capacitor may be used to allow sufficient time for the snubber capacitor to discharge.
第１図においてタイムデイレイ回路１１をはぶ
き、T1とT2の期間は零とおいてもよい。また、
電圧調整回路と、負荷抵抗の間にスイツチを設け
半導体素子２１〜２４をすべてオンするT2〜T3
の期間のみ、回路電流をバイパスするか、あるい
は高抵抗を電圧調整回路と負荷の間に設けること
により、停止期間中に負荷に大電流を流すことを
さけることができる。 In FIG. 1, the time delay circuit 11 may be omitted and the periods T1 and T2 may be set to zero. Also,
T 2 to T 3 where a switch is provided between the voltage adjustment circuit and the load resistor and all semiconductor elements 21 to 24 are turned on.
By bypassing the circuit current only during this period, or by providing a high resistance between the voltage regulating circuit and the load, it is possible to avoid flowing a large current through the load during the stop period.
以上の説明の様に本発明によれば、電圧調整回
路を運転停止後、ただちに所定の期間全半導体素
子をオンした後にブリツジ回路の電圧を検出する
ことにより、運転停止後短時間のうちに誤動作の
ない半導体素子、あるいは非線形抵抗の故障検出
を行なうことができる。
As described above, according to the present invention, by detecting the voltage of the bridge circuit after immediately turning on all the semiconductor elements for a predetermined period after the voltage regulating circuit is stopped, malfunction occurs within a short time after the operation is stopped. It is possible to detect failures in semiconductor devices with no faults or nonlinear resistances.
第１図は本発明による電圧調整回路の故障検出
回路の一実施例を示すブロツク図、第２図はその
タイミングチヤート、第３図は半導体素子と非線
形抵抗体を並列に接続した従来の電圧調整回路の
故障検出回路の一実施例を示すブロツク図、第４
図は第３図の動作を説明するためのタイムチヤー
トである。
１……電圧調整回路、２１〜２４……半導体素
子、３１〜３４……スナバ抵抗、４１〜４４……
スナバコンデンサ、５１〜５４……非線形抵抗
体、６１〜６２……分圧用抵抗、７……電圧検出
回路、８……直流電源、９……負荷抵抗、１０…
…半導体制御回路、１１……タイムデイレイ回
路、１２……インバータ、１４……OR回路、１
５……ワンシヨツト回路、１６……OR回路。
Fig. 1 is a block diagram showing an embodiment of a failure detection circuit for a voltage regulator circuit according to the present invention, Fig. 2 is a timing chart thereof, and Fig. 3 is a conventional voltage regulator in which a semiconductor element and a nonlinear resistor are connected in parallel. Block diagram illustrating an embodiment of a circuit failure detection circuit, No. 4
The figure is a time chart for explaining the operation of FIG. 3. 1... Voltage adjustment circuit, 21-24... Semiconductor element, 31-34... Snubber resistor, 41-44...
Snubber capacitor, 51-54...Nonlinear resistor, 61-62...Voltage dividing resistor, 7...Voltage detection circuit, 8...DC power supply, 9...Load resistor, 10...
...Semiconductor control circuit, 11...Time delay circuit, 12...Inverter, 14...OR circuit, 1
5...One-shot circuit, 16...OR circuit.
Claims (1)
子を並列に接続した回路を複数個直列に構成した
電圧調整回路と該電圧調整回路に並列に接続され
る一対の分圧用抵抗から成る直列回路とでブリツ
ジ回路を構成し、前記電圧調整回路と直列回路の
中間点からブリツジ回路の出力電圧を得て、前記
半導体素子あるいは非線形抵抗体の故障を検出す
るようにした故障検出装置において、前記電圧調
整回路の運転停止後又は運転期間の最後に所定期
間前記電圧調整回路の全半導体素子を導通状態に
する手段を具備した故障検出装置。1. A bridge circuit is constructed by a voltage adjustment circuit consisting of a plurality of circuits connected in series with a semiconductor element, a snubber circuit, and a nonlinear resistance element connected in parallel, and a series circuit consisting of a pair of voltage dividing resistors connected in parallel to the voltage adjustment circuit. In the failure detection device, the output voltage of the bridge circuit is obtained from an intermediate point between the voltage adjustment circuit and the series circuit, and a failure of the semiconductor element or the nonlinear resistor is detected. A failure detection device comprising means for bringing all semiconductor elements of the voltage regulating circuit into conduction for a predetermined period after stopping or at the end of an operating period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59177428A JPS6156977A (en) | 1984-08-28 | 1984-08-28 | Failure detection device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59177428A JPS6156977A (en) | 1984-08-28 | 1984-08-28 | Failure detection device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6156977A JPS6156977A (en) | 1986-03-22 |
| JPH0339633B2 true JPH0339633B2 (en) | 1991-06-14 |
Family
ID=16030760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59177428A Granted JPS6156977A (en) | 1984-08-28 | 1984-08-28 | Failure detection device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6156977A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6467171A (en) * | 1987-09-05 | 1989-03-13 | Ekushimu Shokai Kk | Apparatus for applying twist pleat to bun or such |
| JP3635028B2 (en) * | 2000-11-24 | 2005-03-30 | レオン自動機株式会社 | Molding equipment for food materials |
-
1984
- 1984-08-28 JP JP59177428A patent/JPS6156977A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6156977A (en) | 1986-03-22 |
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