JPH0339842U - - Google Patents
Info
- Publication number
- JPH0339842U JPH0339842U JP1989099888U JP9988889U JPH0339842U JP H0339842 U JPH0339842 U JP H0339842U JP 1989099888 U JP1989099888 U JP 1989099888U JP 9988889 U JP9988889 U JP 9988889U JP H0339842 U JPH0339842 U JP H0339842U
- Authority
- JP
- Japan
- Prior art keywords
- insulating substrate
- wiring board
- printed wiring
- push
- bonding pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
Landscapes
- Die Bonding (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図イないしハは本考案における一実施例概
略構成図、第２図は第１図Ｂ−Ｂ′断面図、第３
図イおよびロは従来例説明図である。
１……印刷配線板、２……ダイランド、３……
ベアチツプ、４……ボンデイング・パツド、５…
…ワイヤー、６……プツシユ・バツク可能な絶縁
基板、７……開口、８……貫通孔、９……スリツ
ト、１０……封止樹脂。
Figures 1A to 3C are schematic configuration diagrams of an embodiment of the present invention, Figure 2 is a sectional view taken along line B-B' in Figure 1, and Figure 3 is a cross-sectional view taken along line B-B' in Figure 1.
Figures A and B are explanatory diagrams of a conventional example. 1...Printed wiring board, 2...Dieland, 3...
Bear tip, 4... Bonding pad, 5...
... wire, 6 ... push-back insulating substrate, 7 ... opening, 8 ... through hole, 9 ... slit, 10 ... sealing resin.
Claims (1)
デイング・パツド４が形成されている印刷配線板
１において、 当該印刷配線板１の一部を打ち抜いてプツシユ
・バツク可能な状態に嵌め込まれている絶縁基板
６と、 当該プツシユ・バツク可能な絶縁基板６と前記
印刷配線板１とで形成されるスリツト９に開けら
れた貫通孔８と、 前記プツシユ・バツク可能な絶縁基板６上に設
けられたダイランド２と、 当該ダイランド２上に載置されている半導体ベ
アチツプ３と、 当該半導体ベアチツプ３と上記印刷配線板１の
ボンデイング・パツト４とを接続するワイヤー５
と、 半導体ベアチツプ３、ボンデイング・パツド４
およびワイヤー５を覆う部分と前記貫通孔８の内
部とを一体にモールドする樹脂１０と、 を備えたことを特徴とする印刷配線板。[Claim for Utility Model Registration] A printed wiring board 1 in which a circuit, a die land 2, and a bonding pad 4 are formed on an insulating substrate, in a state where a part of the printed wiring board 1 can be punched out and pushed back. an insulating substrate 6 fitted into the push-back insulating substrate 6; a through-hole 8 formed in a slit 9 formed by the push-back insulating substrate 6 and the printed wiring board 1; and the push-back insulating substrate 6. A die land 2 provided above, a semiconductor bare chip 3 placed on the die land 2, and a wire 5 connecting the semiconductor bare chip 3 and the bonding pad 4 of the printed wiring board 1.
, semiconductor bare chip 3, bonding pad 4
and a resin 10 that integrally molds a portion covering the wire 5 and the inside of the through hole 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989099888U JPH0339842U (en) | 1989-08-29 | 1989-08-29 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989099888U JPH0339842U (en) | 1989-08-29 | 1989-08-29 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0339842U true JPH0339842U (en) | 1991-04-17 |
Family
ID=31648920
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989099888U Pending JPH0339842U (en) | 1989-08-29 | 1989-08-29 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0339842U (en) |
-
1989
- 1989-08-29 JP JP1989099888U patent/JPH0339842U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0339842U (en) | ||
| JPH0270447U (en) | ||
| JPS61192479U (en) | ||
| JPH032635U (en) | ||
| JPS6430878U (en) | ||
| JPH0327068U (en) | ||
| JPH0336478U (en) | ||
| JPH0213728U (en) | ||
| JPS63164239U (en) | ||
| JPS62168685U (en) | ||
| JPH033770U (en) | ||
| JPS62103277U (en) | ||
| JPS61102074U (en) | ||
| JPS633154U (en) | ||
| JPS6234445U (en) | ||
| JPH0447571U (en) | ||
| JPH0351861U (en) | ||
| JPH038449U (en) | ||
| JPS62142874U (en) | ||
| JPH03124643U (en) | ||
| JPH0328756U (en) | ||
| JPS62196374U (en) | ||
| JPH028080U (en) | ||
| JPH036843U (en) | ||
| JPS58193663U (en) | Element mounting structure of printed circuit board |