JPH0339944U - - Google Patents

Info

Publication number
JPH0339944U
JPH0339944U JP10014889U JP10014889U JPH0339944U JP H0339944 U JPH0339944 U JP H0339944U JP 10014889 U JP10014889 U JP 10014889U JP 10014889 U JP10014889 U JP 10014889U JP H0339944 U JPH0339944 U JP H0339944U
Authority
JP
Japan
Prior art keywords
data processing
synchronous clock
processing block
optical fiber
generation circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10014889U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10014889U priority Critical patent/JPH0339944U/ja
Publication of JPH0339944U publication Critical patent/JPH0339944U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Synchronisation In Digital Transmission Systems (AREA)
  • Optical Communication System (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの考案の一実施例のデータ処理装置
の外観図、第2図は第1図に示す実施例装置のブ
ロツク図、第3図は従来のデータ処理装置の一例
の外観図、第4図は第3図に示す従来装置のブロ
ツク図である。 符号の説明、1…データ処理装置、2…マザー
ボード、3…基板ソケツト、4…プリント配線パ
ターン、5…回路基板、7…光分配器、8…光コ
ネクタ、9…光フアイバ、11…データ処理ブロ
ツク、21…クロツク発生回路。
FIG. 1 is an external view of a data processing device according to an embodiment of this invention, FIG. 2 is a block diagram of the embodiment shown in FIG. 1, and FIG. 3 is an external view of an example of a conventional data processing device. FIG. 4 is a block diagram of the conventional device shown in FIG. Explanation of symbols, 1... Data processing device, 2... Motherboard, 3... Board socket, 4... Printed wiring pattern, 5... Circuit board, 7... Optical distributor, 8... Optical connector, 9... Optical fiber, 11... Data processing Block 21...Clock generation circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 複数のデータ処理ブロツク間を導体線で接続し
これを介して各データ処理ブロツクがデータを送
受信すると共に、同期クロツク発生回路から各デ
ータ処理ブロツクに光フアイバを介して同期クロ
ツクを伝送することを特徴とするデータ処理装置
It is characterized by connecting a plurality of data processing blocks with conductor wires, through which each data processing block transmits and receives data, and at the same time transmitting a synchronous clock from a synchronous clock generation circuit to each data processing block through an optical fiber. data processing equipment.
JP10014889U 1989-08-28 1989-08-28 Pending JPH0339944U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10014889U JPH0339944U (en) 1989-08-28 1989-08-28

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10014889U JPH0339944U (en) 1989-08-28 1989-08-28

Publications (1)

Publication Number Publication Date
JPH0339944U true JPH0339944U (en) 1991-04-17

Family

ID=31649168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10014889U Pending JPH0339944U (en) 1989-08-28 1989-08-28

Country Status (1)

Country Link
JP (1) JPH0339944U (en)

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