JPH0423331U

JPH0423331U -

Info

Publication number: JPH0423331U
Application number: JP1990065306U
Authority: JP
Priority date: 1990-06-20
Filing date: 1990-06-20
Publication date: 1992-02-26

Description

[Brief explanation of drawings]

第１図は本考案のデイレイ回路が設けられたマ
ザーボードシステムの回路図、第２図は本考案の
他の実施例の回路図、第３図は従来のデイレイ回
路が設けられたマザーボードシステムの構成説明
図、第４図はクロツク信号のタイムチヤート、第
５図は他の従来例のデイレイ回路である。１０……マザーボード、１１……クロツクライ
ン、２０２，２１２……デイレイライン、２０５
，２１５……遅延回路パターン、３０，３１……
出力ボード。 Figure 1 is a circuit diagram of a motherboard system equipped with the delay circuit of the present invention, Figure 2 is a circuit diagram of another embodiment of the present invention, and Figure 3 is the configuration of a motherboard system equipped with a conventional delay circuit. The explanatory diagrams, FIG. 4 is a time chart of a clock signal, and FIG. 5 is another conventional delay circuit. 10...Motherboard, 11...Clock line, 202, 212...Delay line, 205
, 215... Delay circuit pattern, 30, 31...
output board.

Claims

[Scope of Claim for Utility Model Registration] (1) A device comprising a motherboard and a plurality of output boards installed at intervals on the motherboard via connectors, and supplying clock signals to each output board at the same timing. In the delay circuit, the connector installed on the motherboard has at least first, second, and third output terminals, and the first output terminal is connected to a clock line to which a clock signal from a clock generator is supplied. Connect the 2nd and 3rd
A delay means having a delay time depending on the installation position of the connector is connected between the terminals of the connector, and the connector installed on the output board is connected to the first, second, and third output terminals of the connector on the motherboard side. has first, second, and third signal input terminals to be coupled;
, a second signal input terminal is electrically connected, and a clock signal obtained from the third output terminal is applied to an output board. (2) The delay circuit according to claim 1, wherein the delay means is constituted by a delay line. (3) The delay circuit according to claim 1, wherein the delay means is constituted by a wiring circuit pattern provided on a motherboard.