JPH0339949Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to an improvement of a phase control circuit using a PLL.

A phase control circuit using a PLL (Phase Look Loop) is well known. When trying to obtain a signal with a phase that has a certain relationship with a certain signal using such a PLL method, if you try to synchronize with a signal with a low frequency such as the commercial frequency, the low-pass filter in the PLL circuit will respond. If time becomes slow and you try to make this low-pass filter have a high-speed response, the output ripple will increase and the frequency of the synchronous waveform will change.

This invention was devised to solve the above-mentioned problems of conventional PLLs, and its purpose is to create a phase control circuit that responds extremely quickly and stably even when obtaining signals synchronized with low-frequency signals. It provides: Hereinafter, the present invention will be explained in detail using the drawings.

The figure is a circuit diagram of an embodiment of the present invention. In the figure, IN is an input terminal to which a low frequency (Fi) signal is applied, and OUT is an output terminal from which a signal of frequency Fo having a predetermined phase difference with respect to the input frequency Fi is extracted. 10 is a phase comparator, one input terminal 11 of which is connected to an input terminal IN. 2
0 is a charge pump, 30 is a summing point, 40 is an integrator, 50 is a voltage control oscillator, and 60 is a frequency divider.

In the charge pump 20, ±Es is a positive/negative reference voltage source, 21 and 22 are switches, and 23 is an interval averaging circuit. Switches 21 and 22 are driven by the output of phase comparator 10, and positive and negative reference voltage sources ±Es are applied to section averaging circuit 23 via these switches. The interval averaging circuit 23 includes an integrator 24 that integrates the reference voltage ±Es, a switch 25 driven by a signal synchronized with the input signal Fi, and holds the output of the integrator 24 obtained through this switch. 2, and a feedback resistor 27 that negatively feeds the output of the hold circuit to the integrator 24. Note that 28 is a differentiation circuit that differentiates the input signal Fi.

The output signal of the charge pump 20 having such a configuration is added to the phase control signal α at the addition point 30, and the added output is applied to the voltage controlled oscillator 50 via the integrator 40. The output terminal of the voltage controlled oscillator 50 is connected to the output terminal Out via the frequency divider 60 and is also connected to the other input terminal 12 of the phase comparator 10. The operation of the phase control circuit according to the present invention having such a configuration will be explained as follows.

The input terminals 11 and 12 of the phase comparator 10 receive an input signal of low frequency Fi applied to the input terminal IN and a signal of Fo/N obtained by dividing the output frequency Fo by a frequency division ratio N in a frequency divider 60. Added. A phase comparator 10 compares the phases of Fi and Fo/N and generates a signal according to the phase difference between the two signals. That is, the output Fo/of the frequency divider 40 is
When the phase is leading N, the phase comparator 10
The switch 22 is driven by outputting a DOWN signal.
This causes the -Es reference voltage to change to the charge pump 2
Integrator 2 constituting the interval averaging circuit 23 at 0
4 and integrated. Conversely, for Fi
If the phase of Fo/N is delayed, the phase comparator 10
outputs the UP signal, and the reference voltage of +Es is applied to integrator 2.
Added to 4. The output of the integrator 24 is given to a hold circuit 26 via a switch 25 driven by a signal synchronized with the input frequency Fi. Therefore, the hold circuit 26 holds the output voltage of the integrator 24 which is proportional to the phase difference between one cycle of the input signal Fi. This hold voltage is negatively fed back to the integrator 24 via the resistor 27. Therefore, the integrator 24 now integrates the difference voltage between the square of the instantaneous value of the input signal Fi and the output of the hold circuit 26 for one cycle of the input signal Fi, and the integrated output is held in the hold circuit 26. Similarly, the hold circuit 26 holds the integral value of the difference between the square of the instantaneous value of the input signal Fi and the output of the hold circuit 26 for each period of the input signal Fi. In this way, the section averaging circuit 23 constituting the charge pump 20 outputs the average value of the difference between the square of the instantaneous value of the input signal Fi and the output of the hold circuit 26 for each predetermined section. In such an interval averaging circuit 23, only the difference between the output of the hold circuit 26 and the output of the phase comparator 10 is integrated by the integrator 24 at the period of the input signal, in a period with the input frequency. Even if the input frequency Fi is low, it responds quickly and eliminates ripples. The output of the charge pump 20 is subtracted from the phase control signal α at the summing point 30, and the subtracted signal is sent to the integrator 4.
After being added to 0 and integrated, it is added to the next stage voltage controlled oscillator 50. The output of the voltage controlled oscillator 50 is applied to the other input terminal 12 of the phase comparator 10 via the frequency divider 60, but this voltage controlled oscillator has a constant phase angle of the output frequency Fo defined by the phase control signal α. In other words, the integrator 4
The phase of the oscillator output is controlled so that the 0 input becomes zero. When the input to the integrator 40 becomes zero, the voltage controlled oscillator 50 outputs a frequency Fo with a constant phase angle determined by the phase control signal α. As a result, the Fo signal whose phase angle is defined by the value of the phase control signal α is continuously extracted from the output terminal OUT. Note that it is not always necessary to add the phase control signal α. In that case, if the output is taken out from the voltage controlled oscillator 50, the phase angle is defined by the input signal Fi as the output, and a signal obtained by multiplying this input signal Fi by N times is taken out.

In the phase control circuit of the present invention having such a configuration, the interval averaging circuit 23 is used as a low-pass filter constituting the PLL. In the interval averaging circuit 23, the output of the hold circuit 26 and the phase comparator 1
Integrator 2 calculates only the difference from the output of 0 using the period of the input signal.
Since the integration is performed by 4, the response is very fast. Therefore, in the present invention configured using such an interval averaging circuit 23, a signal synchronized with a low frequency input can be obtained at extremely high speed with a simple configuration.

[Brief explanation of the drawing]

The figure is a connection diagram showing one embodiment of the phase control circuit according to the present invention. 10... Phase comparator, 20... Charge pump, 23... Area averaging circuit, 40... Integrator,
50... Voltage controlled oscillator, 60... Frequency divider.

Claims (1)

[Scope of utility model registration request] A low frequency input signal, a frequency divider, a phase comparator for comparing the phases of the low frequency input signal and the output signal of the frequency divider, an integrator, a switch driven by a signal synchronized with the input signal, and this switch. The section averaging circuit includes a hold circuit that holds the output signal of the integrator that has passed through the integrator, and a feedback resistor that feeds back the output of this hold circuit to the integrator. a charge pump configured such that a reference voltage source is connected to the integrator; a voltage controlled oscillator to which the output of the hold circuit in the charge pump is applied;
A phase control circuit comprising the frequency divider for frequency dividing the output of the voltage controlled oscillator, and configured to obtain an output signal from the frequency divider or the voltage controlled oscillator.