JPH0339979U - - Google Patents

Info

Publication number
JPH0339979U
JPH0339979U JP10097189U JP10097189U JPH0339979U JP H0339979 U JPH0339979 U JP H0339979U JP 10097189 U JP10097189 U JP 10097189U JP 10097189 U JP10097189 U JP 10097189U JP H0339979 U JPH0339979 U JP H0339979U
Authority
JP
Japan
Prior art keywords
circuit
keying
outputs
pulse
hold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10097189U
Other languages
Japanese (ja)
Other versions
JPH071892Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10097189U priority Critical patent/JPH071892Y2/en
Publication of JPH0339979U publication Critical patent/JPH0339979U/ja
Application granted granted Critical
Publication of JPH071892Y2 publication Critical patent/JPH071892Y2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Television Receiver Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は本考案の一実施例に係り
、第1図はキードAGC回路をその周辺回路とと
もに示したブロツク回路図、第2図は動作説明に
供する波形図である。第3図および第4図は従来
例に係り、第3図はキードAGC回路とその周辺
回路を示すブロツク回路図、第4図は動作説明に
供する波形図である。 1…チユーナ、2…映像中間周波増幅回路、3
…映像検波回路、4…映像増幅回路、5…同期分
離回路、6…発振回路、7…ダウンカウント回路
、8…AFG回路、9…キーイング回路、11…
ピークホールド回路、AO…タイミング制御回路
、HD…水平同期信号、BP…バツクポーチ、S
O…検波映像信号、SOK…キーイング映像信号
、PR…ホールドリセツトパルス、PK…キーイ
ングパルス、VA,VA…AGC電圧。
1 and 2 relate to an embodiment of the present invention, in which FIG. 1 is a block circuit diagram showing a keyed AGC circuit together with its peripheral circuits, and FIG. 2 is a waveform diagram for explaining the operation. 3 and 4 relate to a conventional example, with FIG. 3 being a block circuit diagram showing a keyed AGC circuit and its peripheral circuits, and FIG. 4 being a waveform diagram for explaining the operation. 1... Tuner, 2... Video intermediate frequency amplification circuit, 3
...Video detection circuit, 4...Video amplification circuit, 5...Synchronization separation circuit, 6...Oscillation circuit, 7...Down count circuit, 8...AFG circuit, 9...Keying circuit, 11...
Peak hold circuit, AO...timing control circuit, HD...horizontal synchronization signal, BP...back porch, S
O...detected video signal, SOK...keying video signal, PR...hold reset pulse, PK...keying pulse, VA1 , VA2 ...AGC voltage.

Claims (1)

【実用新案登録請求の範囲】 水平同期信号終了後のバツクポーチの部分でホ
ールドリセツトパルスを出力するとともに、前記
バツクポーチの部分で前記ホールドリセツトパル
スの直後にキーイングパルスを出力するタイミン
グ制御回路と、 前記キーイングパルスの入力によつて検波映像
信号を抜き取り、キーイング映像信号として出力
するキーイング回路と、 前記ホールドリセツトパルスの前側エツジによ
つてリセツトされ、ホールドリセツトパルスの後
側エツジによつて前記キーイング映像信号をピー
クホールドし、AGC電圧として出力するピーク
ホールド回路 とを備えたキードAGC回路。
[Claims for Utility Model Registration] A timing control circuit that outputs a hold reset pulse at a back porch portion after the horizontal synchronization signal ends, and outputs a keying pulse immediately after the hold reset pulse at the back porch portion; a keying circuit that extracts a detected video signal by inputting a pulse and outputs it as a keying video signal; and a keying circuit that is reset by the front edge of the hold reset pulse and outputs the keying video signal by the rear edge of the hold reset pulse. A keyed AGC circuit that includes a peak hold circuit that holds the peak and outputs it as an AGC voltage.
JP10097189U 1989-08-29 1989-08-29 Keyed AGC circuit Expired - Fee Related JPH071892Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10097189U JPH071892Y2 (en) 1989-08-29 1989-08-29 Keyed AGC circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10097189U JPH071892Y2 (en) 1989-08-29 1989-08-29 Keyed AGC circuit

Publications (2)

Publication Number Publication Date
JPH0339979U true JPH0339979U (en) 1991-04-17
JPH071892Y2 JPH071892Y2 (en) 1995-01-18

Family

ID=31649948

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10097189U Expired - Fee Related JPH071892Y2 (en) 1989-08-29 1989-08-29 Keyed AGC circuit

Country Status (1)

Country Link
JP (1) JPH071892Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100816685B1 (en) * 2007-02-05 2008-03-25 장창진 Oxygen water making machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100816685B1 (en) * 2007-02-05 2008-03-25 장창진 Oxygen water making machine

Also Published As

Publication number Publication date
JPH071892Y2 (en) 1995-01-18

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees