JPH0340036A - Memory protecting circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a memory protection circuit that prevents erroneous data from being written to memory even when a temporary error occurs in the operation of a CPU. be.

[Conventional technology]

FIG. 3 is a diagram showing a conventional memory protection circuit,
(1a) is the CPU of the main system, and (1b) is the CPU of the slave system.

(2) is a synchronous control circuit that operates CPU (1a) and CPU (1b) in clock synchronization; (3a) (3
b) is the address output from CPU (1a) (1b), (4a) (4b) is the address output from CPU (1a) (1b)
), (5) is a write signal to the memory output from cpu (1a), (6) is a writable memory, (7) is the address (3a) and (3b) and data (4a). ) and (4b) at the timing of the write signal (5), (8) is the comparison circuit (7).
), (9) is the error signal (8)
A failure detection circuit that detects , aI is a CPU stop signal, aD
is an address decoder, and α2 is a chip select signal for selecting one of the memories (6).

FIG. 4 is a diagram showing the operation timing of the main signals in FIG. 3.

Next, the operation will be explained.

The CPU (Ia) and the CPU (1b) perform parallel processing in synchronization with control signals such as clocks output from the synchronous control circuit (2).

When data writing processing to memory (6) occurs.

The CPUs (1a) and (1b) respectively access addresses (3a) and (3b) and data (
4g) (4b) Outputs the write signal (5) and chip select signal αa.

Addresses (3a) and (3b), data (4a) and (4b)
)teeth.

A comparator circuit (7) compares the values to see if they are the same in a time width of T1, and the result is output as an error signal (8) at timings to and tl. When the error signal (8) in Fig. 4 is 10, no error occurs.

This shows a situation where an error occurred when tl.

When the error signal (8) indicates no error, that is, to, the data (4a) is written to the memory (6) by the write signal (5) and processing continues. Error signal (8)
When there is an error, that is, when tl, the data (4a) is written to the memory (6) by the write signal (5), and at the same time the failure detection circuit (9) outputs the CPU stop signal 01.
occurs. Synchronous control circuit (2) is CPU (1a)
(1b) immediately stops.

[Problem to be solved by the invention]

Since the conventional memory protection circuit was configured as described above, the error signal (
8), when an error occurs, the CPU (ia) (1b) processing is stopped by the CPU stop signal αIK, but the incorrect data (4a) has already been written to the memory (6). There was the issue of

This invention was made in order to solve the above-mentioned problem, and even if an error occurs in the main CPU (1a), it can be done without writing incorrect data (4a) to the memory (6). The purpose is to be able to stop the processing of CPU (Ia) (1b).

[Means to solve the problem]

The memory protection circuit according to the present invention has a main system cpU (1
a) and the slave CPU (1b) are processed in parallel, and when writing data to the memory (6), the address (3) from both systems is processed in parallel.
A comparison circuit (7) that compares each part of a) and (3b) and data (4a) and (4b), and address data and memory that determines which memory (6) to access based on the address (3&). A gate circuit is configured to control the generation of the write signal (5) to the CPU (1a) in the comparison circuit.
) and CPU (1b), the gate circuit sends a write signal (5) to the memory.
) is prohibited from being output.

[Effect]

The memory protection circuit in this invention is CPU (1a)
Even if an error occurs by configuring a gate circuit that opens and closes the output of the write signal (5) to the memory, it is possible to prevent erroneous data (4a) from being written to the memory (6).

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, (13) a gate circuit that stops supplying the write signal (5) to the memory (6) when the error signal (8) is output from the Ifi comparison circuit (7), (141
is the write signal after the control of gate circuit 3. Write signal +141 is finally supplied to memory (6), at which point data (4a) is written to memory (6) accessed by chip select signal 0z.

FIG. 2 shows a timing chart of the main signals.

Next, the operation will be explained.

Addresses (50 and (sb), data (4&) output from CPU (1a) and CPU (1b)
The operations of (4b) and write signal (5) are the same as in the conventional example.

In this invention, the comparison circuit (7) is connected to the synchronous control circuit (2).
The address (60 and (sb)) and the data (4a
) and (4b).

In FIG. 2, the time "to" is an example in which no error occurs due to comparison, and the error signal (8) is not generated and the write signal (
5) is supplied to the memory (6) as a write signal α through its IT gate circuit a31. tl time is
This is an example where an error occurs due to comparison, and the error signal (8)
occurs, gate circuit α3 is closed, and write signal α4
is prohibited.

By using the above method, even if the CPU (1a) executes an incorrect process, incorrect data (4a) is stored in the memory (6).
can be prevented from being written.

Note that the failure detection circuit (
9) operates, and the CP
The processing of U (1a) and (1b) is stopped.

Note that in the above embodiment, the CPU (1a) is connected to the memory (
6) shows an example of writing data (42L) t-, but the same effect can be achieved even when applied to an external output circuit, etc., instead of writing to the memory (6).

〔Effect of the invention〕

As described above, according to the present invention, the CPU (1a) and C
The output information from the PU (1b) is compared, and if an error occurs, the gate circuit that disables the write signal 0 to the memory (6) is configured.
Even if an error occurs in (1a), the memory (
Writing of incorrect data (4a) to 6) can be prevented.

[Brief explanation of drawings]

1 and 2 are diagrams showing an embodiment of the present invention, and FIGS. 3 and 4 are diagrams showing a conventional example. (1a) (ib) is the CPU, +21 is the synchronous control circuit,
(3a) (3b) is address X, (4a) (4b)
is data, (51 (141 is a write signal, (6) is a memory, (7) is a comparison circuit, (8) is an error signal, (9)
is a failure detection circuit, α1)Vi is a CPU stop signal. The wholesaler is the address decoder, and the a3 is the chip select signal. a3 is a gate circuit. Note that the same reference numerals in Figure 1 indicate the same or equivalent parts.

Claims (1)

[Claims] Main system CPU, slave system CPU, above-mentioned main system and slave system CP
A synchronous control circuit that synchronizes U operations, the above-mentioned main system and slave system C
A comparison circuit that compares addresses and data values respectively output from the PU, an address decoder that generates a chip select signal for the memory to be accessed based on the address of the main CPU, and a memory It consists of a gate circuit that prohibits write signals to the memory, and a failure detection circuit that detects error signals from the comparison circuit.If the main and slave CPUs output the same address and data value, this value is write to memory,
A memory protection circuit characterized in that if the values are not the same, a write signal to the memory is inhibited by an error signal of the comparison circuit, thereby preventing writing of erroneous data to the memory.