JPH0340133A - Information processor - Google Patents

Abstract

PURPOSE:To process the information at a high speed and at a low cost by providing a switch circuit which changes the speed of a processor clock between the use of a low speed storage part storing a normal process program and a high speed storage part storing a high speed process program. CONSTITUTION:At execution of a normal instruction, a program instruction is stored in a low speed storage part 2 and carried out when a selector 5 is controlled by a storage part pointing circuit 4 and selects the output of the part 2. At execution of a high speed instruction, the program instruction is stored in a high speed storage part 3. Then the circuit 4 receives an address pointing the part 3 from a processor 1 via a storage part address line 6 and controls the selector 5 for selection of the output of the part 3. At the same time, the circuit 4 controls a clock switch circuit 10 to shorten the clock cycle. As a result, the information can be processed at a high speed and at the same time the hardware quantity and the increase of the cost of the storage part can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to the configuration of a storage unit that stores a program.

[Prior Art] Conventionally, a storage unit for storing programs of this type of information processing apparatus has been configured with storage elements having the same performance regardless of the type of program.

[Problems to be Solved by the Invention] In the conventional information processing device described above, memory elements with the same performance are used as the program storage section, so in order to improve the performance of the processor, the entire program storage section must be equipped with a high-speed This will use expensive memory. This means that the information processing device becomes expensive.

[Means for Solving the Problems] An information processing apparatus of the present invention includes a low-speed storage section for storing one normal processing program as a storage section.

The present invention is characterized by having a high-speed storage section for storing a high-speed processing program, and further comprising a clock switching circuit for changing the speed of the processor clock when using the low-speed storage section and when using the high-speed storage section. .

[Example] Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention.

1 is the processor, 2 is the normal processing program (normal instructions)
3 is a high-speed storage section for storing high-speed processing programs; 4 is a storage section instruction circuit; 5 is a low-speed storage section for storing a high-speed processing program;
is a selector for switching the output signals of the low-speed storage section and the high-speed storage section, 6 is the address line of the storage section, 7 is the output signal line of the low-speed storage section, 8 is the output signal line of the high-speed storage section, and 9 is the output of the selector. A signal line 10 is a clock switching circuit for the processor 1.

Generally speaking, as shown in Figure 2, when a processor executes one program instruction at the rising edge of the clock,
According to that instruction, the address for fetching the next instruction is output to the address line. The next program instruction is read from the storage section according to the output address, starts execution at the rising edge of the primary clock, and repeats this process. A processor takes different times to generate the next program address depending on the instruction being executed. Conventionally, the execution cycle was determined by the slowest of these instructions. On the other hand, in the present invention, a program group that must be processed at high speed is stored in the high-speed storage unit 3, and the cycle of the clock supplied to the processor 1 when an instruction is executed on the high-speed storage unit 3 is shortened. This enables high-speed processing.

When executing a normal instruction, the program instruction is stored in the low-speed storage section 2, and is executed by controlling the selector 5 by the storage section instruction circuit 4 to select the output of the low-speed storage section 2. On the other hand, when a high-speed instruction is executed, the program instruction is stored in the high-speed storage section 3, and when the storage section instruction circuit 4 receives an address that instructs the high-speed storage section 3 from the processor 1 through the storage section address line 6, the program instruction is stored in the high-speed storage section 3. The selector 5 is controlled to select the output of , and the clock switching circuit 10 is also controlled to shorten the clock cycle. As a result, programs that require high-speed processing are executed in short clock cycles, making high-speed processing possible.Furthermore, since only the necessary programs are stored in the high-speed storage unit 3, the amount of hardware and cost required for the storage unit can be reduced. The increase will be small.

[Effects of the Invention] As explained above, the present invention includes a low-speed storage section for storing a normal processing program, a high-speed storage section for storing a high-speed processing program, and a difference between when the low-speed storage section is used and when the high-speed storage section is used. By including a clock switching circuit that changes the speed of the processor clock over time, an information processing device capable of high-speed processing can be provided at low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a diagram showing an execution time chart of a general processor. 1: Processor, 2: Low speed storage section, 3: High speed storage section, 4
: storage section instruction circuit, 5: selector, 6: storage section address line, 7: low speed storage section output signal line. 8: High-speed storage unit output signal line, 9: Selector output signal line,
10: Crochet switching circuit.

Claims (1)

[Claims] 1) An information processing device that has a processor and a storage unit that stores a program that instructs the operation of the processor, and the processor reads a program from the storage unit and operates according to the instructions. Information processing comprising: a storage unit, a high-speed storage unit for storing a high-speed processing program, and a clock switching circuit for changing the speed of a processor clock between when the low-speed storage unit is used and when the high-speed storage unit is used. Device.