JPH034032Y2 - - Google Patents

Info

Publication number
JPH034032Y2
JPH034032Y2 JP14406485U JP14406485U JPH034032Y2 JP H034032 Y2 JPH034032 Y2 JP H034032Y2 JP 14406485 U JP14406485 U JP 14406485U JP 14406485 U JP14406485 U JP 14406485U JP H034032 Y2 JPH034032 Y2 JP H034032Y2
Authority
JP
Japan
Prior art keywords
carrier tape
electrical components
burn
wiring pattern
electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP14406485U
Other languages
Japanese (ja)
Other versions
JPS6251745U (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP14406485U priority Critical patent/JPH034032Y2/ja
Publication of JPS6251745U publication Critical patent/JPS6251745U/ja
Application granted granted Critical
Publication of JPH034032Y2 publication Critical patent/JPH034032Y2/ja
Expired legal-status Critical Current

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  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Description

【考案の詳細な説明】 [概要] 本考案は、電気部品を配列して移送するキヤリ
アテ−プ面に複数部品の端子を連結した共通配線
パタ−ンを形成して、キヤリアテ−プ面上の配線
パタ−ンに接続、固定された電気部品をキヤリア
テ−プ上で電圧が印加できるようにし、バ−ンイ
ン等の製造工程の効率化を計つたものである。
[Detailed description of the invention] [Summary] This invention forms a common wiring pattern that connects the terminals of multiple components on the surface of a carrier tape on which electrical components are arranged and transferred. This allows voltage to be applied on the carrier tape to electrical components connected and fixed to the wiring pattern, thereby increasing the efficiency of manufacturing processes such as burn-in.

[産業上の利用分野] 本考案は電気部品のキヤリアテ−プ(または搭
載フイルム)に関するものである。
[Industrial Application Field] The present invention relates to a carrier tape (or mounting film) for electrical components.

近時、量産される電気部品の信頼性を向上させ
るために、電気部品の製造工程でバ−ンイン工程
は極めて重要に成つている。
In recent years, burn-in processes have become extremely important in the manufacturing process of electrical components in order to improve the reliability of mass-produced electrical components.

一方これらの電気部品を収納する方法として、
従来電気部品をキヤリアテ−プに自動化装置等で
巻き取り収納する方法があり、対象になる電気部
品は多種類にわたり、抵抗、コンデンサ、半導体
装置、その他の量産部品に採用されている。
On the other hand, as a way to store these electrical components,
Conventionally, there is a method of winding and storing electrical components on carrier tape using automated equipment, etc., and this method covers a wide variety of electrical components and is used in resistors, capacitors, semiconductor devices, and other mass-produced components.

このようにキヤリアテ−プに電気部品を収納す
る方法は自動化装置で作業が行われ、また電気部
品をプリント板等に順次実装する際も自動機によ
つてなされるために省力効果果が大きい。
This method of storing electrical components in a carrier tape is carried out by automated equipment, and the sequential mounting of electrical components onto a printed circuit board or the like is also carried out by an automated machine, resulting in a large labor-saving effect.

本考案ではキヤリアテ−プ面に複数部品の端子
を連結した共通配線パタ−ンを行い、複数電気部
品に同時に電圧を印加して、キヤリアテ−プ面上
で電気部品のバ−ンインを行うようにしたもので
ある。
In this invention, a common wiring pattern is formed on the surface of the carrier tape that connects the terminals of multiple components, and voltage is applied to multiple electrical components simultaneously to perform burn-in of the electrical components on the surface of the carrier tape. This is what I did.

[従来の技術] 従来、電気部品として、例えば半導体装置のバ
−ンインを行う場合には、バ−ンインを行う半導
体装置の数量に相当する専用ソケツトを準備し、
そのソケツトに半導体装置を挿入して、所定の環
境条件と電気条件のもとでバ−ンインを行つてい
る。
[Prior Art] Conventionally, when performing burn-in of electrical components such as semiconductor devices, dedicated sockets corresponding to the number of semiconductor devices to be burn-in are prepared, and
A semiconductor device is inserted into the socket and burn-in is performed under predetermined environmental and electrical conditions.

また従来から電気部品をキヤリアテ−プによつ
て、自動的に巻き取り収納する方法があり、これ
はキヤリアテ−プ面に電気部品を貼着して渦巻状
に巻き取るのが一般的であるが、従来のキヤリア
テ−プのパタ−ンは個々の電気部品毎に分かれて
おり、複数部品を連結した共通パタ−ンを有する
ものはなかつた。
Additionally, there is a conventional method for automatically winding up and storing electrical components using carrier tape, which generally involves attaching the electrical components to the surface of the carrier tape and winding it up in a spiral. Conventional carrier tape patterns are separated for each individual electrical component, and there is no carrier tape that has a common pattern that connects multiple components.

[考案が解決しようとする問題点] 従来の個々の電気部品の端子毎に、接触子を設
けることは効率が悪く、また電気信号(電圧等)
を印加するためのフイクスチヤ−もより複雑にな
るということが問題である。
[Problems to be solved by the invention] Conventionally, it is inefficient to provide a contact for each terminal of each electrical component, and electrical signals (voltage, etc.)
The problem is that the fixture for applying is also more complex.

[問題点を解決するための手段] 本考案は上記問題点を解消した部品のキヤリア
テ−プを提供するもので、その手段は、複数の電
気部品を所定間隔で連続的に配列したキヤリアテ
−プ面に、所定の共通配線パタ−ンを形成し、そ
の配線パタ−ンは電気部品の所定リ−ド端子間の
接続パタ−ン、外部信号印加パツド等が設けら
れ、動作時にはキヤリアテ−プ面の共通配線パタ
−ンに電圧を印加して、複数の電気部品のバ−ン
インを行うようにしたものてある。
[Means for Solving the Problems] The present invention provides a carrier tape for parts that solves the above problems. A predetermined common wiring pattern is formed on the surface, and the wiring pattern is provided with connection patterns between predetermined lead terminals of electrical components, external signal application pads, etc., and during operation, the carrier tape surface The burn-in of a plurality of electrical components is performed by applying a voltage to a common wiring pattern.

[作用] 本考案は、電気部品のキヤリアテ−プに共通配
線パタ−ンを形成することにより、キヤリアテ−
プ上に端子を連結した形で電気部品を収納してか
ら、バ−ンインを行うもので、その結果複数の電
気部品をより少ない信号印加接触子をもつてバ−
ンインすることができ、製造工程の効率化を計か
つたものである。
[Function] The present invention improves the carrier tape by forming a common wiring pattern on the carrier tape of electrical components.
Burn-in is performed after electrical components are housed with connected terminals on the board, and as a result, multiple electrical components can be burn-in with fewer signal application contacts.
It is designed to improve the efficiency of the manufacturing process.

[実施例] 第1図は、本考案の電気部品のキヤリアテ−プ
の模式斜視図である。
[Example] FIG. 1 is a schematic perspective view of a carrier tape for an electrical component of the present invention.

実施例は、キヤリアテ−プ面上に数個乃至数十
個程度の半導体装置が端子を連結配列さた場合を
示している。
The embodiment shows a case in which several to several dozen semiconductor devices are connected and arranged with terminals on the surface of a carrier tape.

半導体装置1を搭載するキヤリアテ−プ11は
フイルム状であり、その材料は紙または合成樹脂
系が一般的であつて、厚みが約0.1mm〜0.2mm、幅
が35mm〜70mm程度であり、バ−ンイン条件により
耐熱性を考慮すると、耐熱温度として、最低でも
150℃の耐熱性が必要であり、そのような材料と
してポリイミド等が最適材料として使用すること
ができる。キヤリアテ−プ面の長さ方向には、半
導体装置の種類による大きさ7mmx7mm〜12mmx12
mm程度の付法に対応する収納テ−プ12が設けら
れ、また両側面にはテ−プ送り孔13がある。
The carrier tape 11 on which the semiconductor device 1 is mounted is in the form of a film, and its material is generally paper or synthetic resin, and the thickness is about 0.1 mm to 0.2 mm, the width is about 35 mm to 70 mm, and the material is about 0.1 mm to 0.2 mm, and the width is about 35 mm to 70 mm. - Considering heat resistance depending on the in-line conditions, the minimum heat-resistant temperature is
Heat resistance of 150°C is required, and polyimide or the like can be used as an optimal material for such a material. In the length direction of the carrier tape surface, the size is 7 mm x 7 mm to 12 mm x 12 depending on the type of semiconductor device.
A storage tape 12 corresponding to an approximation of about mm is provided, and tape feeding holes 13 are provided on both sides.

本考案による、キヤリアテ−プ面には、配線パ
タ−ンとして、銅を蒸着またはスパツタにより、
幅が1mmの共通配線パタ−ン14が形成されてい
るが、その配線パタ−ンには、半導体装置のリ−
ド端子との接続パタ−ン15、信号印加パツド1
6,17が設けられている。
According to the present invention, copper is deposited or sputtered on the surface of the carrier tape as a wiring pattern.
A common wiring pattern 14 with a width of 1 mm is formed, and the wiring pattern includes a lead of a semiconductor device.
Connection pattern 15 with pad terminal, signal application pad 1
6 and 17 are provided.

第2図は、本考案の一実施例であるキヤリアテ
−プ面上で半導体装置をバ−ンインしている状態
を示す斜視図である キヤリアテ−プ11は半導体装置1を搭載し
て、バ−ンインが行われ、信号印加パツド16に
は電源接続端子18から電源電圧が印加され、ま
た信号印加パツド17は接地端子19によつて接
続される。
FIG. 2 is a perspective view showing a state in which a semiconductor device is burn-in on the surface of a carrier tape according to an embodiment of the present invention. The power supply voltage is applied to the signal application pad 16 from the power supply connection terminal 18, and the signal application pad 17 is connected to the ground terminal 19.

半導体装置のリ−ド端子とキヤリアテ−プ上のパ
タ−ンの接続は、銀ペ−ストや半田付け等でも良
いし、また接合部を押圧して接合してもよい。
The lead terminals of the semiconductor device and the patterns on the carrier tape may be connected by silver paste, soldering, or the like, or by pressing the joints.

このように、半導体装置をキヤリアテ−プ上で
バ−ンインした後、そのまま収納することにより
製造工程が著しく合理化される。
In this manner, the manufacturing process is significantly streamlined by storing the semiconductor device as it is after being burned in on the carrier tape.

なおキヤリアテ−プの長さに、特に制限はなく
半導体装置の数量やバ−ンインの条件により、適
宜長さを決定することがきる。
There is no particular limit to the length of the carrier tape, and the length can be determined as appropriate depending on the number of semiconductor devices and burn-in conditions.

[考案の効果] 以上詳細に説明したように本考案の電気部品の
キヤリアテ−プは、電気部品に専用のバ−ンイン
用の共通配線パタ−ンがなされているために、少
ない外部接触子で同時に複数個の半導体装置をバ
−ンインし得るという効果大なるものがある。
[Effects of the invention] As explained in detail above, the carrier tape for electrical components of the present invention requires fewer external contacts because the electrical components have a common wiring pattern for dedicated burn-in. A great advantage is that a plurality of semiconductor devices can be burned in at the same time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のキヤリアテ−プの要部斜視
図、第2図は、本考案のキヤリアテ−プお用いて
半導体装置をバ−ンインしている状態を示す要部
斜視図、 図において、1は半導体装置、2はリ−ド線、
11はキヤリアテ−プ、12は収納テ−プ、13
はテ−プ送り孔、14は共通配線パタ−ン、15
は接続パタ−ン、16,17は信号印加パツド、
18は電源接続端子、19は接地端子、をそれぞ
れ示している。
FIG. 1 is a perspective view of the main part of the carrier tape of the present invention, and FIG. 2 is a perspective view of the main part showing a state in which a semiconductor device is burn-in using the carrier tape of the present invention. 1 is a semiconductor device, 2 is a lead wire,
11 is carrier tape, 12 is storage tape, 13
is the tape feed hole, 14 is the common wiring pattern, 15
is a connection pattern, 16 and 17 are signal application pads,
Reference numeral 18 indicates a power supply connection terminal, and reference numeral 19 indicates a ground terminal.

Claims (1)

【実用新案登録請求の範囲】 複数の電気部品1が所定間隔で連続的に貼着さ
れて配置されたキヤリアテ−プ11面上に、複数
部品の端子を連結した共通所定の配線パタ−ン群
14,16,17が形成され、 該キヤリアテ−プ面の配線パタ−ンに該電気部
品の所定のリ−ド端子2を接合して該複数部品に
同時に電圧が印加できるようにしたことを特徴と
する電気部品のキヤリアテ−プ。
[Claims for Utility Model Registration] A group of common predetermined wiring patterns connecting the terminals of the plurality of parts on the surface of the carrier tape 11 on which the plurality of electrical parts 1 are successively pasted at predetermined intervals. 14, 16, and 17 are formed, and a predetermined lead terminal 2 of the electrical component is bonded to the wiring pattern on the surface of the carrier tape so that voltage can be applied to the plurality of components simultaneously. Carrier tape for electrical parts.
JP14406485U 1985-09-19 1985-09-19 Expired JPH034032Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14406485U JPH034032Y2 (en) 1985-09-19 1985-09-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14406485U JPH034032Y2 (en) 1985-09-19 1985-09-19

Publications (2)

Publication Number Publication Date
JPS6251745U JPS6251745U (en) 1987-03-31
JPH034032Y2 true JPH034032Y2 (en) 1991-02-01

Family

ID=31054328

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14406485U Expired JPH034032Y2 (en) 1985-09-19 1985-09-19

Country Status (1)

Country Link
JP (1) JPH034032Y2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4855672A (en) * 1987-05-18 1989-08-08 Shreeve Robert W Method and process for testing the reliability of integrated circuit (IC) chips and novel IC circuitry for accomplishing same

Also Published As

Publication number Publication date
JPS6251745U (en) 1987-03-31

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