JPH0340467A - Photoelectric conversion device - Google Patents

Abstract

PURPOSE:To obtain a photoelectric conversion device which is simple in constitution and high in resolution by a method wherein a primary electrode region and a control electrode region of a transistor(TR) which forms a photoelectric conversion element are independently controlled in potential, and the junction between the regions is biased in a required direction. CONSTITUTION:In a transistor having an amplification function which forms a photoelectric conversion element, the emitter and the collector of a primary electrode region and the base of a control electrode region which stores carriers correspondent to the irradiation of light rays are separately controlled in potential through separate power sources respectively. In a storage operation, the emitter is made floating, the collector is positively biased, the base is reversely biased to the emitter, a saturation voltage is determined through the control of the base potential, and the transistor has a switching action. In a readout operation, the emitter and the collector are put in the same state, the base is normally biased to the emitter, and the transistor carries out readout at a high speed as keeping linearity, and in a refresh operation, the transistor functions well the same as above, so that a photoelectric conversion element of this design is simple in structure and improved in resolution, where amplification and switching are properly controlled and no after image occurs.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a photoelectric conversion device, and more particularly to a photoelectric conversion device that accumulates carriers generated by incident light and reads out a signal based on the accumulated carriers.

[Prior Art] In recent years, research on photoelectric conversion devices, particularly solid-state imaging devices, has been actively conducted along with the progress of semiconductor technology, and some of them have begun to be put into practical use.

These solid-state imaging devices can be roughly divided into CCD type and M
It is classified into two types of OS. The CCD type imaging device is MO
A potential well is formed under the S capacitor electrode, and charges generated by incident light are accumulated in this well. During readout, these potential wells are sequentially moved by pulses applied to the electrode to remove the accumulated charges. It uses the principle of transferring the data to the output amplifier section and reading it out.

Furthermore, some CCD type imaging devices use a pn junction diode structure for the light receiving section and a COD structure for the transfer section. On the other hand, in a MOS type imaging device, charges generated by incident light are accumulated in each of the photodiodes made of pn junctions that constitute the light receiving section, and when reading out, the MOS switching transistors connected to each photodiode are sequentially activated. It uses the principle that by turning on, the accumulated charge is read out to the output amplifier section.

The CCD type imaging device has a relatively simple structure, and
Considering the noise that can be generated, only the capacitance value of the charge detector consisting of the floating diffusion in the final stage contributes to random noise, so it is a relatively low-noise imaging device and can perform low-light imaging. . However, CC
Due to process constraints for manufacturing a D-type imaging device, a MOS type amplifier is used as an on-chip output amplifier, and therefore 1/f noise, which is easily noticeable on images, is generated from the interface between silicon and the 5iOi film. Therefore, although it is said to have low noise, there are limits to its performance. Furthermore, if the number of cells is increased to achieve higher density in order to achieve higher resolution, the maximum amount of charge that can be stored in one potential well will decrease, making it impossible to maintain a dynamic range. This will be a big problem as it becomes more and more popular. Furthermore, since a CCD-type imaging device transfers accumulated charges by sequentially moving potential wells, even if there is a defect in one of the cells, charge transfer may stop there, or in an extreme case. It also has the disadvantage that the manufacturing yield cannot be improved.

On the other hand, MOS type imaging devices are structurally a little more complex than CCD type imaging devices, especially frame transfer type devices, but they can be configured to increase storage capacity.
It has the advantage of having a wide dynamic range.

Furthermore, even if one of the cells has a defect, because of the X-Y addressing method, the defect does not affect other cells, which is advantageous in terms of manufacturing yield. However, in this MOS type imaging device, wiring capacitance is connected to each photodiode during signal readout, so an extremely large signal voltage drop occurs, resulting in a drop in the output voltage, and the wiring capacitance is large, resulting in random noise. CCD
Compared to conventional imaging devices, these devices have drawbacks such as difficulty in low-light photography.

Furthermore, in the future, as the resolution of imaging devices increases, the size of each cell will be reduced and the amount of accumulated charge will decrease. On the other hand, the wiring capacitance, which is determined by the chip size, does not decrease much even if the line width is made thinner. For this reason, the MOS type imaging device becomes increasingly disadvantageous in terms of S/N.

Although CCD type and MOS type imaging devices have the above-mentioned advantages and disadvantages, they are gradually approaching the level of practical use. However, it can be said that there are essentially major problems in promoting the higher resolution that will be required in the future.

On the other hand, regarding solid-state imaging devices, Japanese Patent Laid-Open No. 56-15
Publication No. 0878 "Semiconductor Imaging Device" JP-A-56-157
Publication No. 073 “Semiconductor Imaging Device °°, JP-A-56-16
A new method is proposed in Publication No. 5473 "Semiconductor Imaging Device". While CCD type and MOS type imaging devices accumulate charges generated by incident light on the main electrode (for example, the source of a MOS transistor), the method proposed here accumulates charges generated by incident light. , control electrode (
For example, it is based on a new concept of controlling the flowing current by the charges accumulated in the base of a bipolar transistor, the gate of a 5IT (static induction transistor), or a MOS transistor, and generated by light.

In other words, whereas the CCD type and MOS type read out the accumulated charge itself to the outside, the method proposed here amplifies the charge using the amplification function of each cell and then reads out the accumulated charge. If you look at it from another perspective, it is read out as a low impedance output through impedance conversion. Therefore, the method proposed here has high output, wide dynamic range, and low noise, and because the carriers (charges) excited by the optical signal are accumulated in the control electrode, non-destructive readout is possible. It has several advantages such as Furthermore, it can be said that this method has the potential for higher resolution in the future.

[Technical Problem to be Solved by the Invention J] However, this method is basically an X-Y address method, and the element structure described in the above publication is a bipolar transistor in each cell of a conventional MOS type imaging device. The basic configuration is a combination of amplifying elements such as , SIT transistors, etc. Therefore, it has a relatively complicated structure, and although it has the potential for high resolution and high resolution, there is a limit to high resolution as it is.

There are also limitations in the points described below. The above-mentioned Japanese Patent Application Publication No. 56-150878, Japanese Patent Application Publication No. 56-15
No. 7073, JP-A-56-165473, and r SIT (Static Injection T
Transistor) Application to Image Sensors, Technical Report of the Television Society (hereinafter referred to as the Journal of the TV Society)”
This is a representative example of the prior art in which one of the inventors of the present invention was involved.

JP-A-56-150878, JP-A-56-157
Publication No. 073 includes N”P”I (or P-,
A configuration is described in which charge is accumulated in the P1 region of a hook structure consisting of N-) and N◆ regions, and the potential of the N0 region, which forms a capacitor with the ground potential, is read out using a switching transistor. .

However, in the reset operation after reading, P1
Since the area is only grounded, many visible afterimages occur and fixed pattern noise is also large.
Due to the manufacturing process, variations occur in the parasitic capacitance of switches connected to the P' region, so even though it is reset, the P0 region is swayed due to the influence of that pulse after the reset pulse is removed, resulting in variations in the positive potential. It is. Another reason is that since the output line is not reset, residual potential appears as an afterimage in that part.

On the other hand, Japanese Patent Application Publication No. 56-165473
The P0 area in the floating state, the high resistance area, and the N+ area connected to the transparent electrode to which the )<)res voltage is applied. The hook structure is shown.

The N0 region in a floating state also serves as one of the main electrode regions of the readout transistor, and during a readout operation, the transistor is turned on and electrons flow into the positively charged N3 region, and the voltage change is used as a signal to read out the transistor. conduct. However, in the reset operation after reading, only the N+ region O on the transparent electrode side opposite to the output circuit is set to a slightly negative potential, so that many noticeable afterimages occur. Also, fast refresh is not possible. This is because the parasitic capacitance of the hook structure varies due to the manufacturing process, so even though it is reset,
This is because after the reset pulse is removed, a positive potential is applied to the N+ region, and the P region is swung, causing variations in the positive potential. Another reason is that since the output line is not reset, residual potential appears as an afterimage in that part.

The TV Society Journal describes gate storage type photocells and base storage type photocells. Among these, the gate storage type photocell has a configuration in which the gate is placed in a floating state, the gate region is reverse biased to a predetermined voltage in advance via a refresh line via an insulating film, and data is read out to an output circuit with a grounded source resistance load. However, in this configuration, many afterimages occur because there is no reset operation on the reading side during the reset operation. Furthermore, since the gate potential is not fixed, the gate potential that is finally reset will vary due to variations in the gate potential immediately before reset (initial gate potential), which has variations in the process.

On the other hand, the base storage type photocell is N”P”N-1N
It has a phototransistor structure, and has a floating base (P"), a collector (N") to which a pulsed voltage is applied, and an emitter-follower output circuit including a capacitor and a switching MOSFET are connected. Emitter (N
o). However, with this configuration, even in refresh, the emitter is simply grounded, so good refresh cannot be achieved. Furthermore, since the gate potential is not fixed, the base potential that is finally reached varies depending on the variation in the base potential (initial base potential) immediately before reset, which has variations in process.

In addition to the above-mentioned prior art, U.S. Patent No. 3.624
, 428 and Japanese Patent Publication No. 50-38531, an output circuit with a grounded emitter resistor load is connected to a transistor whose base is provided with an electrode through an insulating layer, and the base is reverse biased to perform an accumulation operation. A configuration is shown in which current is read out by the output circuit of the emitter-grounded resistive load.

However, please note that since this is a current readout from a destructive sensor, linearity and afterimage characteristics are poor.

[Object of the Invention] An object of the present invention is to provide a new photoelectric conversion device that has an amplification function in each cell but has an extremely simple structure and can sufficiently cope with future increases in resolution.

Another object of the present invention is to provide an excellent photoelectric conversion device in which afterimages and fixed pattern noise are hardly a problem even when performing high-speed readout with good linearity.

Still another object of the present invention is to provide a photoelectric conversion device in which afterimages and fixed pattern noise are hardly a problem even when performing high-speed readout with good linearity, and which can be refreshed at high speed.

Still another object of the present invention is to provide a photoelectric conversion device that has almost no problems with afterimages, noise, or variation in output from cell to cell even when irradiated with any amount of light, and can refresh even faster. It's about doing.

This object has a control electrode region made of a semiconductor of a first conductivity type, and first and second main electrode regions made of a semiconductor of a second conductivity type different from the first conductivity type, and has a control electrode region made of a semiconductor of a first conductivity type. the first main electrode region is electrically connected to a first reference voltage source, and the first main electrode region is electrically connected to a first reference voltage source so that the carriers generated by the carriers are accumulated in the control electrode region; A photoelectric conversion device comprising: a first switch means for removing carrier; and a second switch means for electrically connecting the control electrode region to a second reference voltage source. achieved.

[Function] According to the present invention, the potential of the control electrode region and the potential of the main electrode region can be independently controlled during the refresh operation.

During readout, the junction between the control electrode region and the main electrode region connected to the output circuit is forward biased. In this way, an integrated output voltage can be obtained in a very short time in a non-destructive mode, and an output signal with good linearity with respect to the irradiated light can be obtained.

Furthermore, at the time of refreshing, the main electrode area connected to the output circuit can be refreshed, so that the output line can be reset at the same time.

In addition, since the reset for setting the potential of the control electrode region, which injects carriers into the control electrode region or directly fixes its potential, is combined with the reset of the main electrode region, the resetting of the main electrode region Since the potential of the control electrode region immediately after resetting does not depend on the initial potential of the control electrode region, which tends to have variations, the refresh operation can be improved.

[Example] An outline of a preferred embodiment according to the present invention will be described below.

First, referring to FIGS. 3 and 4, reference numeral 3 in FIG.
An output circuit is connected to a first main electrode region (emitter) of a photoelectric conversion cell including a transistor indicated by 0. This output circuit is connected to vertical lines 38, 38', 3
8″, horizontal shift register 39, MOS transistor 4
0.40'40'', output line 41% MOS transistor 42, output transistor 44, load resistor 45, etc., and vertical lines 38, 38' and 38'' are each designated by the reference numeral 21 in FIG. 4 as a capacitive load. It has wiring capacitance like Cs.

In addition, a vertical shift register 32 is used as a readout means for reading out a photoelectrically converted signal based on the accumulated charge.
Buffer MOS transistors 33.33', 33'',
A circuit configuration is adopted in which a terminal 34 and horizontal lines 31, 31', 31'' are provided.

During storage operation, the emitter is floating or grounded, and the second main electrode region (collector) is biased to a positive potential. Further, the control electrode region (base) is placed in a reverse bias state with respect to the emitter, and the saturation voltage can be determined by controlling the base potential at this time. In this way, by appropriately setting the bias voltage, the cell itself can have a switching action.

During a read operation, the emitter is kept in a floating state and the collector is biased to a positive potential.The potential of the control electrode region is controlled by the read means independently of the main electrode region. If the base is forward biased with respect to the emitter, high-speed readout can be achieved while ensuring good linearity. The operation at this time will be explained with reference to FIG. At the time of reading, by independently applying a positive voltage 5 from the wiring 10 to the emitter in a floating state and the collector held at a positive potential, the base potential is biased in the forward direction with respect to the emitter potential. This causes the emitter-base junction to be deeply biased in the forward direction. In this way, a current flows until the emitter potential becomes equal to the base potential, that is, the accumulated voltage generated by light irradiation, but the time required at this time is further shortened by the action of the voltage Vll, resulting in high-speed readout. Even in this case, excellent linearity can be ensured.

The refresh operation is as follows.

The emitter is connected to a first reference voltage source, indicated by the earth symbol, and grounded by means of MOS transistors 48, 48', 48'' as first switching means.The collector is then connected to a third reference voltage source, i.e. Placed at positive potential or ground potential.

FIG. 5 shows a case where the collector is grounded. In such a state, by applying a positive potential V□ as a voltage from the second reference voltage source to control the potential of the base as a control electrode region, at least the base-emitter region is forward biased and the base region The holes accumulated in the base region flow out, and electrons flow into the base region, causing the accumulated charge to disappear. Forward bias means for applying such a forward bias is constructed by providing MOS transistors 48, 48', 48'', buffer MOS transistors 35, 35', 35'', terminals 36, 37, etc.

Further, it is more preferable that the base potential is controlled by a transistor as a second switch means as shown in FIGS. 1 and 2. In such a configuration, carriers are injected into the base from the wiring 222 serving as the second reference voltage source to set the base potential to O or a slightly positive potential, and then the emitter is grounded to perform forward bias refreshing. In this way, problems caused by afterimages and noise can be further improved regardless of the amount of irradiation light.

Embodiments of the present invention will be described in detail below with reference to the drawings.

First, prior to explaining the photoelectric conversion device of the present invention, the basic structure and operation of the optical sensor cell that constitutes the photoelectric conversion device of the present invention will be explained.

FIG. 6 is a diagram illustrating the basic structure and operation of a photosensor cell that constitutes a photoelectric conversion device according to the present invention.

FIG. 6(a) shows a plan view of the optical sensor cell, and FIG. 6(b) shows a plan view of the optical sensor cell.
) is a cross-sectional view of a portion AA' in the plan view of FIG. 6(a), and FIG. 6(C) is an equivalent circuit thereof. In addition,
In each part, parts common to FIGS. 6(a), (b), and (c) are given the same number.

Although FIG. 6 shows a plan view of the aligned arrangement method, it goes without saying that the pixel shifting method (interpolation arrangement method) can also be used to increase the horizontal resolution.

This optical sensor cell is made of silicon doped with impurities such as phosphorus (P), antimony (sb), and arsenic (As) to make it n-type or n'' type, as shown in FIGS. 6(a) and (b). On the substrate 1, a passivation film 2 usually made of a PSG film or the like; an insulating oxide film 1 made of a silicon oxide film (Sing) 3
; Element isolation region 4 made of an insulating film of 5ins or 5isN+, or a polysilicon film, etc., for electrically insulating between neighboring photosensor cells; A low impurity concentration region formed by epitaxial technology, etc.; n
- region 5; p region 6, which is the base of the bipolar transistor doped with an impurity such as boron (B) using an impurity diffusion technique or an ion implantation technique; formed by an impurity diffusion technique, an ion implantation technique, etc. n0 region 7 which becomes the emitter of the bipolar transistor; for example, aluminum (Al
2), a wiring 8 formed of a conductive material such as An-Si, Al2-Cu-5i, etc.; an electrode 9 for applying a pulse to the p-region 6 in a floating state through the insulating film 3; a wiring 10 therefor; ; n0 region 1 with high impurity concentration formed by impurity diffusion technology to make ohmic contact with the back surface of the substrate 1;
1; an electrode 12 made of a conductive material such as aluminum for applying a substrate potential, that is, a collector potential of a bipolar transistor;

Note that 19 in FIG. 6(a) is a contact portion for connecting the n0 region 7 and the wiring 8. Further, the alternating portions of the wirings 8 and 10 are so-called two-layer wirings, and are insulated from each other by insulating regions formed of an insulating material such as SiO'a. That is, metal 2
It has a layered wiring structure.

In the equivalent circuit of FIG. 6(C), capacitor Cox13 is connected to electrode 9. Insulating film 3. Consisting of a MOS structure of p region 6,
Also, the bipolar transistor 14 has n0 as an emitter.
It consists of a region 7, a p region 6 as a base, an n- region 5 with a low impurity concentration, and an n or n' region 1 as a collector. As is clear from these drawings, p region 6 is made into a floating region.

The second equivalent circuit in FIG. 6(c) shows that the bipolar transistor 14 has a base-emitter junction capacitance Cbe l 5
, base-emitter pn junction diode Dbe 16
, base-collector junction capacitance Cbc 17, base-collector junction capacitance Cbc
This is expressed using a collector pn junction diode Dbc18.

Here, symbols indicating two current sources in different directions, which should originally be drawn in parallel with the pn junction diode Dbe 16 and the pn junction diode Dbc 18, are omitted in the equivalent circuit diagram.

The basic operation of the optical sensor cell will be explained below using FIG. 6.

The basic operation of this photosensor cell consists of a charge accumulation operation by light incidence, a read operation, and a refresh operation.

First, charge accumulation operation will be explained.

In the charge storage operation, for example, the emitter is grounded through the wiring 8, and the collector is biased to a positive potential through the wiring 12. Further, the base is set to a negative potential by applying a positive pulse voltage to the capacitor Cox l 3 through the wiring 10 in advance, that is, the emitter 7
It is assumed that the reverse bias state is applied to . The operation of biasing the base 6 to a negative potential by applying a pulse to the Cox 13 will be explained in detail later when the refresh operation is explained.

In this state, when light 20 enters from the front side of the photosensor cell as shown in FIG. 6, electron-hole pairs are generated within the semiconductor.

Of these, electrons flow toward the n-region 1 side because the n-region 1 is biased to a positive potential, but holes are rapidly accumulated in the p-region 6. Due to the accumulation of holes in the p region, the potential of the p region 6 gradually changes toward a positive potential.

In FIGS. 6(a) and 6(b), the lower surface of the light-receiving surface of each sensor cell is mostly occupied by the p region, which is the n0 region 7. Naturally, the concentration of electron-hole pairs excited by light increases as it approaches the surface. Therefore, many electron-hole pairs are excited in the p-region 6 by the light. Electrons photoexcited in the p region immediately flow out of the p region 6 without recombining,
If the structure is such that it is absorbed in the n region, the p region 6
The excited holes are accumulated as they are, changing the potential of p region 6 to a positive potential direction. When the impurity concentration of p region 6 is made uniform, electrons excited by light diffuse to the pn-junction between p region 6 and n-region 5, and then join the n-region. It is absorbed by the n collector region 1 due to the drift caused by the strong electric field. of course,
Electrons within the p-region 6 may travel only by diffusion, but if the structure is such that the impurity concentration of the p-pace decreases from the surface to the inside, this impurity concentration difference will cause the base An electric field Ed, directed from the inside to the surface is generated within the surface. Here, Wa is the depth from the light incident surface of the p region 6, k is the Boltzmann constant, T is the absolute temperature, q is the unit charge, Nas is the surface impurity concentration of the p space region 6, and N
1 is the impurity concentration at the interface of p region 6 with n- high resistance region 5.

Here, if N□/NAl>3, the movement of electrons in the p region 6 is performed by drift rather than diffusion. That is, in order to effectively operate the carriers excited by light in the p-region 6 as a signal, the impurity concentration of the p-region 6 must decrease from the light-incidence side surface toward the inside. is desirable. When p region 6 is formed by diffusion, its impurity concentration decreases toward the inside compared to the light incident side surface.

A portion below the light-receiving surface of the sensor cell is occupied by the n0 region 7. The depth of n0 region 7 is usually 0.2 to 0.3μ
Since the amount of light absorbed by the n3 region 7 is designed to be about m or less, the amount of light absorbed by the n3 region 7 is not so large to begin with, so there is no problem. However, the presence of the n3 region 7 causes a decrease in sensitivity to light on the short wavelength side, particularly blue light.

n"The impurity concentration of region 7 is usually I x 10"cm-"
Designed to a degree or more. The diffusion distance of holes in the n0 region 7 doped with impurities at such a high concentration is about 0.15 to 0.2 μm. therefore,
In order to effectively flow the holes optically excited in the no region 7 into the p region 6, it is desirable that the n0 region 7 also have a structure in which the impurity concentration decreases from the light incident surface toward the inside. If the impurity concentration distribution in the n0 region 7 is as shown above, a strong drift electric field will be generated from the light incident surface toward the inside, and the holes optically excited in the n0 region 7 will immediately flow into the p region 6 due to the drift. .

If the impurity concentration of both the n0 region 7 and the p region 6 is configured to decrease from the light incident side surface toward the inside, the n0 region 7, which exists on the light incident side surface side of the sensor cell,
All the carriers optically excited in the p region 6 function effectively as optical signals. If this n" region 7 is formed by impurity diffusion from a silicon oxide film or a polysilicon film doped with As or P at a high concentration, it is possible to obtain an n0 region with the desired impurity gradient as described above. It is.

Eventually, the accumulation of holes will cause the base potential to change to the emitter potential, in this case to ground potential, where it will be clipped.

More precisely, the base and emitter are biased deeply in the forward direction, and the holes accumulated in the base are clipped at a voltage that starts flowing out to the emitter. That is, the saturation potential of the photosensor cell in this case is approximately given by the potential difference between the bias potential when p region 6 is initially biased to a negative potential and the ground potential. When n'' region 7 is not grounded and accumulates charges generated by optical input in a floating state, p region 6 can accumulate charges to approximately the same potential as n region 1.

The above is a qualitative and general explanation of the charge accumulation operation, but a more specific and quantitative explanation will be given below.

The spectral sensitivity distribution of this optical sensor cell is given by the following equation.

λ S (n)=□・exp(-αX) 1.24 x(1-exp(-αy)) ・T [A/WE However, the first is the wavelength of light [μml, α is the light in the silicon crystal Attenuation coefficient [μm-'], )
1ayer (insensitive region) thickness [μml y is the thickness of the epitaxial layer [μml], T is the transmittance, that is, the ratio of the amount of light that effectively enters the semiconductor considering reflection, etc. to the amount of incident light are shown respectively. Spectral sensitivity S (λ) and irradiance Ee of this optical sensor cell
(λ), the photocurrent Ip is calculated by the following formula.

Ip-(S (L) ・Ee (尤)-dλ[μ
A/cm") However, the irradiance Ee (λ) (gW-cm-"-nm-'
] is given by the following equation.

[μW @cm-"-nm-'] However, Ev is the illuminance of the sensor's light receiving surface (Luxl, P(λ)
is the spectral distribution of the light incident on the light receiving surface of the sensor, ■(λ
) is the relative luminous efficiency of the human eye.

Using these formulas, an optical sensor cell with a 4 μm thick layer is irradiated with A light source (2854°K) and the sensor light receiving surface illuminance is approximately 280 nA/L when 1 [Luxl].
When a photocurrent of cm-2 flows, the number of incident photons or the number of electron-hole pairs generated is 1.8X.
It is about IO "ke/cm"・sec.

Further, at this time, the potential Vp generated by the accumulation of holes excited by light in the base is given by Vp=Q/C. Q is the amount of accumulated hole charge, and C is C
It is the junction capacitance that is the sum of be l 5 and Cbc17.

Now, the impurity concentration of n' region 7 is set to 10"""p region 6.
The impurity concentration of n-region 5 is 10"cm-" and the area of n9-region 7 is 16μm.
l When the area of p region 6 is 64 μm2 and the thickness of n- region 5 is 3 μm, the junction capacitance is about 0.014 pF, while the number of holes accumulated in p region 6 is:
Assuming that the accumulation time is 1/60 sec and the effective light-receiving area, that is, the area obtained by subtracting the area of electrodes 8 and 9 from the area of p-region 6, is approximately 56 μm2, the result is 1.7×10′. Therefore, the potential Vp generated by light incidence is 190m
It will be in V position.

What should be noted here is that as the resolution increases and the cell size decreases, the amount of light incident on each photosensor cell decreases, and the amount of accumulated charge Q decreases as well. As the cell size is reduced, the junction capacitance also decreases in proportion to the cell size, so the potential Vp generated by light incidence is kept almost constant. This is because the optical sensor cell according to the present invention has an extremely simple structure, as shown in FIG. 6, and has the possibility of having an extremely large effective light-receiving surface.

This is one of the reasons why the photoelectric conversion device of the present invention is advantageous compared to interline type CCDs.
In a D-type imaging device, in order to secure the amount of charge to be transferred, the area of the transfer section becomes relatively large, which reduces the effective light-receiving surface, resulting in a decrease in sensitivity, that is, the voltage generated by incident light. become. Furthermore, in the interline type CCD type imaging device, the saturation voltage is limited by the size of the transfer section and gradually decreases, whereas in the optical sensor cell of the present invention, as mentioned earlier, the saturation voltage is limited by the size of the transfer section and gradually decreases. The saturation voltage is determined by the bias voltage when p-region 6 is initially biased to a negative potential, and a large saturation voltage can be ensured.

The operation of reading out the voltage generated by the charges accumulated in p region 6 as described above to the outside will be described next.

In the read operation state, the emitter and wiring 8 are in a floating state,
The collector is held at a positive potential Vcc.

Figure 4 shows an equivalent circuit.

Here again, originally as an equivalent circuit, the pn junction diode D
The symbols indicating two different oriented current sources to be drawn in parallel with be 16 and pn junction diode Dbc 18 are omitted.

Now, if the potential when the base 6 is biased to a negative potential before irradiation with light is -vII, and the accumulated voltage generated by light irradiation is ■, then the base potential is -Va+Vp. . In this state, the wiring 10 is passed through the electrode 9.
When positive voltage VII for reading is applied to
, c7, and a voltage is added to the base. Therefore, the base potential becomes.

Here, if the following conditions are satisfied, the base potential becomes the accumulated voltage vP itself generated by light irradiation. When the base potential is biased in the positive direction with respect to the emitter potential in this way, electrons are injected from the emitter to the base, and since the collector potential is positive, they are accelerated by the drift electric field and flow into the collector. reach. The current flowing at this time is given by the following equation.

X (exp (Vp −Va ) −1
)T where A is the junction area between the base and emitter, q is the unit charge (1,6XIO-'' coulombs), Dn is the electron diffusion constant in the base, and n2. is the minority carrier at the emitter end of the p base. Wa is the base width, NAo is the acceptor concentration at the emitter of the base, NAC is the acceptor concentration at the collector end of the base, k is Boltzmann's constant, T is the absolute temperature, and ■ is the emitter potential.

It is clear from the above equation that this current flows until the emitter potential (1) becomes equal to the base potential, that is, the accumulated voltage Vp generated by light irradiation here. At this time, the temporal change in the emitter potential V is calculated using the following equation.

However, the wiring capacitance Cs here is the capacitance 21 of the wiring 8 connected to the emitter.

FIG. 7 shows an example of a temporal change in emitter potential calculated using the above equation.

According to FIG. 7, it takes about 1 second for the emitter potential to become equal to the base potential. This is due to the fact that when the emitter potential (2) approaches vP, less current flows. Therefore, the means to solve this problem is to set a condition such that when applying the positive voltage VII to the electrode 9, but to set a condition in place of this condition, the base potential is set to V□1. One possible method is to apply an extra forward bias.

The current flowing at this time is given by the following equation.

× (eX p (Vp + Va+am-V*
)-1)T In Fig. 8(a), when V m+-=0, 6 V, after a certain period of time, V and l applied to the electrode 9 are returned to zero volts, and the flowing current is stopped. Figure 8(a) shows the relationship between the readout voltage, that is, the emitter potential, and the accumulated voltage vP when is plotting the value after subtracting the gain. Positive voltage VII applied to electrode 9
When the voltage is returned to zero volts, a voltage opposite to that when applied is added to the base potential, so the base potential is
The state before applying positive voltage VII, i.e. -V m
, and the emitter is reverse biased, so current flow stops. According to Figure 8(a), 1oo
If a readout time of approximately ns or more (that is, the time during which V is applied to the electrode 9) is taken, the linearity of the storage voltage Vp and the readout voltage is ensured over a range of approximately 4 lines, and high-speed readout is possible. It is shown that. In FIG. 8(a), the 45° line is the result when sufficient time is taken for reading, and in the above calculation example, the capacitance Cs of the wiring 8 is 4pF.
However, this is the junction capacitance of Cbe+Cbc, O,
Although it is about 300 times larger than 0.014 pF, the accumulated voltage Vp generated in p region 6 is not attenuated in any way and is read out at an extremely high speed due to the effect of the bias voltage. Figure 8(a) shows. This is because the amplification function, that is, the charge amplification function, of the photosensor cell according to the above configuration is working effectively.

On the other hand, in the conventional MOS type imaging device, the accumulated voltage v
In this readout process, due to the influence of the wiring capacitance Cs, P becomes Cj・■P/(Cj+C3) (where Cj is the pn junction capacitance of the light receiving part of the MOS image pickup device), and the readout voltage value decreases by two orders of magnitude. It had the disadvantage of being stored away. For this reason, in MOS type imaging devices, fixed pattern noise due to variations in parasitic capacitance of switching MOS transistors for external readout, or random noise generated due to large wiring capacitance, that is, output capacitance, is large.
Although there was a problem that the S/N ratio could not be obtained, Fig. 6 (a
), (b), and (c), p
The accumulated voltage itself generated in region 6 is read out to the outside, and since this voltage is quite large, fixed pattern noise and random noise caused by the output capacitance are relatively small, resulting in a signal with an extremely good S/N ratio. It is possible to obtain

First, when the bias voltage V□□ was set to 0.6V,
Although it has been shown that linearity of about 4 lines can be obtained with a high-speed readout time of about xoonsec, the results of calculating the relationship between this linearity, readout time, and bias voltage V II l m g are shown in more detail in Figure 8 ( Shown in b).

In FIG. 8(b), the horizontal axis represents the bias voltage V, □, and the vertical axis represents the read time. Also, the parameters are that when the storage voltage is 1mV, the readout voltage is 1mV.
80%, 90% of V.

It shows the time dependence until it reaches 95% and 98%.

As shown in Figure 8(a), when the storage voltage is 1 mV, the values are 80%, 90%, 95%, and 98%, respectively, and the values are even better at higher storage voltages. That is clear.

According to FIG. 8(b), the bias voltage Vll is 0.
．． At 6V, the readout voltage becomes 80% of the storage voltage when the readout time becomes 0.12μ5190% takes 0.27
It can be seen that it takes 0.54 μs to reach 95% and 1.4 μs to reach 98%. Also, the bias voltage V
It is shown that if □□ is made larger than 0.6V, even faster reading is possible. In this way, once the readout time and required linearity are determined from the overall design of the imaging device, the required bias voltage
) can be determined by using the graph.

Another advantage of the optical sensor cell having the above configuration is that the holes accumulated in the p region 6 can be read out non-destructively since the probability of recombination of electrons and holes in the p region 6 is extremely small. That is, when the voltage VII applied to the electrode 9 during readout is returned to zero volts, the potential of the p region 6 becomes the reverse bias state before applying the voltage v5, and the accumulated voltage Vp generated by light irradiation is newly As long as it is not irradiated, it will be preserved as is. This means that when the optical sensor cell according to the above configuration is configured as a photoelectric conversion device, system operation
This means that new functionality can be provided.

The time during which the accumulated voltage Vp can be held in the p region 6 is extremely long, and the maximum holding time is rather limited by the dark current thermally generated in the depletion layer of the junction.

In other words, this thermally generated dark current saturates the optical sensor cell. However, in the optical sensor cell according to the above configuration, the region where the depletion layer is spread is the n- region 5 which is a low impurity concentration region, and this n- region 5 is a low impurity concentration region.
-Region 5 has an extremely low impurity concentration of about 10 cm to 10 cm, so its crystallinity is good, and thermally generated electrons are less・There are few hole pairs. Therefore, the dark current is small compared to other conventional devices. That is, the optical sensor cell according to the above configuration essentially has a structure with low dark current noise.

Next, the operation of refreshing the charges accumulated in p region 6 will be explained.

In the optical sensor cell having the above configuration, as already mentioned, the charges accumulated in the p region 6 are not eliminated by the read operation. Therefore, in order to input new optical information, a refresh operation is required to eliminate the previously accumulated charges. At the same time, it is necessary to charge the potential of p region 6, which is in a floating state, to a predetermined negative voltage.

In the optical sensor cell having the above configuration, the refresh operation and the read operation are performed by applying a positive voltage to the electrode 9 through the wiring 10. At this time, the emitter is grounded through the wiring 8. The collector is grounded or at a positive potential through the electrode 12. FIG. 5 shows an equivalent circuit for refresh operation. However, an example is shown in which the collector side is grounded.

When a positive voltage V is applied to the electrode 9 in this state, the base 22 has a capacitance divided by the oxide film capacitance Cox13, the base-emitter junction capacitance Cbel5, and the base-collector junction capacitance ficbc17. voltage is applied instantaneously as in the previous read operation. With this voltage, the base-emitter junction diode Dbe 16 and the base-collector junction diode Dbc 18 are forward biased and become conductive, current begins to flow, and the base potential gradually decreases.

At this time, the change in the potential V of the base in a floating state is approximately expressed by the following equation.

However, X (exp C±V)-1) T x (exp C±V)-1) T i is the current flowing through the diode Dbc, and i2 is the current flowing through the diode Dbe. Ab is the base area, Ae
is the emitter area, Dp is the diffusion constant of holes in the collector, pn is the hole concentration in the collector at thermal equilibrium, t, p are the mean free path of holes in the collector, np is the electron at thermal equilibrium in the base It is concentration. In i3, the current due to hole injection from the base side to the emitter can be ignored because the impurity concentration of the emitter is sufficiently higher than that of the base.

The above equation is an approximation of a stepwise junction, and the actual device deviates from a stepwise junction, and the base is thin and has a complicated concentration distribution, so it is not exact. , the refresh operation can be explained with a fair approximation.

Of the current il flowing between the base and collector in the above equation, q
-Dp-p, /Lp indicate a current due to holes, that is, a component in which holes flow from the base to the collector side. In order to facilitate the flow of current due to these holes, in the optical sensor cell having the above configuration, the impurity concentration of the collector is designed to be a little lower than that of a normal bipolar transistor.

FIG. 9 shows an example of the time dependence of the base potential calculated using this formula. The horizontal axis is the refresh voltage V, I1
4 is applied to the electrode 9, that is, the refresh time, and the vertical axis represents the base potential. In addition, the initial potential of the base is used as a parameter. The initial potential of the base is the potential exhibited by the base in a floating state at the moment the refresh voltage VRH is applied.
VII)l.

It depends on Cox, Cbe, Cbc and the charges stored in the base.

Looking at FIG. 9, the base potential always falls along a straight line on the semi-logarithmic graph after a certain period of time, regardless of the initial potential.

FIG. 9(b) shows experimental values of base potential change with respect to refresh time. Compared to the calculation example shown in Figure 9(a), the test device used in this experiment has a much larger dimension, so although the absolute value does not match the calculation example, the base potential change with respect to the refresh time is It has been demonstrated that it changes linearly on a semi-logarithmic graph. This experimental example shows values when both the collector and emitter are grounded.

Now, the maximum value of the accumulated voltage Vp due to light irradiation is 0.4 [V
], If the voltage ■ applied to the base by the refresh voltage V□ is 0.4 EVE, the maximum value of the initial base potential is 0.8 [V] as shown in FIG. 9, and 10-'' after the refresh voltage is applied. [5ecl
Afterwards, the base potential begins to fall in a straight line and decreases to 10-'
(After secl, the potential change coincides with that when no light was applied, that is, when the initial base potential was 0.4 (V).

There are two ways in which the p region 6 can be charged to a negative potential by applying a positive voltage for a certain period of time through the MOS capacitor Cox and removing the positive voltage. One is p region 6
The holes with positive charge from n are mainly in the grounded state.
This is an operation in which negative charges are accumulated by flowing out into region 1.

In order to prevent holes from flowing unilaterally from p region 6 to n region 1 and to prevent electrons from n region 1 from flowing into p region 6 too much, the impurity density of p region 6 must be set to the impurity density of nvA region 1. It should be higher. On the other hand, n0 region 7 and n
Electrons from region 1 flow into p region 6 and recombine with holes, thereby allowing negative charges to accumulate in p region 6. In this case, the impurity density of n region 1 is p
It is set higher than area 6. The operation in which negative charges are accumulated due to the outflow of holes from the p region 6 is more
This is much faster than the operation in which negative charges are accumulated by electrons flowing into the base of region 6 and recombining with holes. However, according to experiments conducted so far, it has been confirmed that even a refresh operation in which electrons are poured into the p-region 6 shows a sufficiently fast time response for the operation of the photoelectric conversion device.

When a photoelectric conversion device is constructed by arranging a large number of optical sensor cells according to the above configuration in the X and Y directions, the accumulated voltage vP in each sensor cell is determined by the image from O to 0.4 [V] in the above example.
After applying the refresh voltage V, , a constant voltage of about 0.3 [■] remains at the base of all sensor cells at 10-' [5ecl], but the accumulated voltage vP due to the image It can be seen that all changes in . That is, in the photoelectric conversion device using optical sensor cells having the above configuration, there is a complete refresh mode in which the base potential of all sensor cells is brought to zero volts by a refresh operation (in this case, in the example of FIG. 9(a), 10 (secl) is There are two modes: 1) and a transient refresh mode in which a certain constant voltage remains at the base potential but the fluctuation component due to the accumulated voltage Vp disappears (in this case, in the example of FIG. 9(a), 10 [μ5
ecl~10 (refresh pulse of secl). In the above example, the voltage VA applied to the base by the refresh voltage VllH was set to 0.4 [V], but if this voltage VA is set to 0.6 [V], the above-mentioned transient refresh mode According to Figure 9, 1 [ns e
cl and can be refreshed extremely quickly. The choice of whether to operate in complete refresh mode or transient refresh mode is determined by the purpose of use of the photoelectric conversion device.

If the voltage remaining at the base in this transient refresh mode is VK, then after applying the refresh voltage VRH,
In the transient state at the moment when v and lH are returned to zero volts, a negative voltage of is added to the base, so that the base potential after the refresh operation by the refresh pulse becomes, and the base becomes reverse biased with respect to the emitter.

It was explained earlier that during the accumulation operation to accumulate carriers excited by light, the base is in a reverse bias state in the accumulation state, but this refresh operation brings refresh and the base to a reverse bias state. These two operations are performed simultaneously.

FIG. 9(c) shows experimental values of changes in base potential after refresh operation with respect to refresh voltage VRH. As a parameter, the value of Cox is set from 5 pF to 10 OpF. The circles are experimental values, and the solid lines are more calculated values.

At this time, V = 0.52V, and Cbc + Cbe = 4p
It is F. However, the probe capacity of the observation oscilloscope is 1
3pF is connected in parallel to Cbc+Cbe. In this way, the calculated values and experimental values are in complete agreement, and the refresh operation has been experimentally confirmed.

In the above refresh operation, an example has been described in which the collector is grounded as shown in FIG. 5, but it is also possible to perform the refresh operation with the collector at a positive potential. At this time, the base-collector junction diode Dbc1
8, even if a refresh pulse is applied, if the positive potential applied to the collector is greater than the potential applied to the base by this refresh pulse, the current remains non-conducting, so the current flows between the base and emitter. It flows only through the coupling diode Dbe 16. For this reason, the base potential drops relatively more slowly than when the collector is grounded, but basically the same high-speed refresh operation as described above is performed.

In other words, the relationship between the base potential and the refresh time in FIG. 9(a) is such that the diagonal straight line when the base potential decreases in FIG. 9(a) shifts to the right, that is, in the direction that requires more time. Become. Therefore, if you use the same refresh voltage vlI14 as when the collector is grounded, it will take time to refresh, but if you slightly increase the refresh voltage V□, you can perform a high-speed refresh operation just like when the collector is grounded. It is.

The above is an explanation of the basic operation of the photosensor cell according to the above configuration, which consists of a charge accumulation operation, a readout operation, and a refresh operation by light incidence.

As explained above, the basic structure of the optical sensor cell according to the above configuration is disclosed in the previously mentioned Japanese Patent Application Laid-Open No. 56-150878, Japanese Patent Application Laid-Open No. 56-157073, and Japanese Patent Application Laid-Open No. 56-1
Compared to Publication No. 65473, it has an extremely simple structure and is fully compatible with future higher resolutions, as well as its excellent characteristics of low noise, high output, wide dynamic range, and non-destructive amplification function. It is saved as is, which has the advantage of being readable.

Next, a configuration example of the photoelectric conversion device of the present invention, which is configured by two-dimensionally arranging the optical sensor cells according to the configuration described above, will be described with reference to the drawings.

FIG. 3 shows a circuit configuration diagram of a photoelectric conversion device in which basic optical sensor cell structures are two-dimensionally arranged in a 3×3 arrangement.

The basic photosensor cell 30 (
At this time, the collector of the bipolar transistor is shown to be connected to the substrate and the substrate electrode. ), a horizontal line 31.31'31'' for applying read pulses and refresh pulses, a vertical shift register 32 for generating read pulses, and a line between the vertical shift register 32 and the horizontal lines 31.31', 31''. buffer MO
Terminal 34 for applying pulses to the gates of S transistors 33, 33' and 33'', and buffer MOS transistors 35, 35 for applying refresh pulses.
', 35'', terminal 36 for applying a pulse to its gate, terminal 37 for applying a refresh pulse.
, vertical lines 38, 38', 38'' for reading out the stored voltage from the elementary photosensor cells 30, horizontal shift registers 39 for generating pulses for selecting each vertical line,
Gate MOS transistors 40, 40', 40'' for opening and closing each vertical line, output line 41 for reading out the accumulated voltage to the amplifier section, and MOS transistor for refreshing the charge accumulated in the output line after reading out. 42, MOS transistor 42, terminal 43 for applying a refresh pulse, transistor 44 such as bipolar, MOS, FET, J-FET, etc. for amplifying the output signal, load resistor 45, for connecting the transistor and the power supply terminals 46, output terminals 47 of transistors, MOS transistors 48° 48', 48'' and MOS transistors 48.48', 48'' for refreshing the charges accumulated in the vertical lines 40.40', 40'' during read operations; This photoelectric conversion device is constituted by a terminal 49 for applying a pulse to the gate of the photoelectric conversion device.

The operation of this photoelectric conversion device will be explained using pulse timing diagrams shown in FIG. 3 and FIG. 10(a).

In FIG. 1O(a), a section 61 corresponds to a refresh operation, a section 62 corresponds to an accumulation operation, and a section 63 corresponds to a read operation.

At time t, the substrate potential, ie, the collector potential 64 of the photosensor cell portion, is kept at the ground potential or positive potential, and FIG. 10(a) shows it kept at the ground potential. Regardless of whether it is a ground potential or a positive potential, as already explained, the only difference is the time required for refreshing, and there is no change in the basic operation. terminal 4
9 is in a high state, the MOS transistors 48, 48', 48'' are kept conductive, and each photosensor cell is grounded through the vertical line 38, 38', 38~. As shown by waveform 66, a voltage is applied that makes the buffer MOS transistor conductive, and the refresh buffer MO3) transistors 35, 35' and 35'' that surround the entire screen are in a conductive state.

In this state, when a pulse is applied to the terminal 37 as shown in the waveform 67, a voltage is applied to the base of each photosensor cell through the horizontal lines 31, 31', 31'', and as already explained, the refresh operation starts and the previous The charges stored in the refresh mode are refreshed according to the complete refresh mode or the transient refresh mode.Whether the mode is the complete refresh mode or the transient refresh mode is determined by the pulse width of the waveform 67.

At time t2, as described above, the base of the transistor of each photosensor cell is reverse biased with respect to the emitter, and the next accumulation period 62 is entered. In this refresh period 61, as shown in the figure, all other applied pulses are kept in a low state.

In the accumulation operation section 62, the substrate voltage, that is, the collector potential waveform 64 of the transistor is set to a positive potential. This allows electrons among electron-hole pairs generated by light irradiation to flow quickly toward the collector side. However, keeping this collector potential at a positive potential is not an essential condition because the base is biased in the reverse direction with respect to the emitter, that is, images are taken with a negative potential.It is also basic to keep the collector potential at ground potential or a slightly negative potential. There is no change in the storage behavior.

In the storage operation state, the MOS transistor 48.4
The potential 65 of the gate terminal 49 of 8', 48'' is kept high, as in the refresh interval, and each MOS transistor is kept conductive.Therefore, the emitter of each photosensor cell is connected to the vertical line 38, 38'. , 38''. When holes are accumulated in the base due to strong light irradiation and become saturated, that is, when the base potential becomes forward biased with respect to the emitter potential (ground potential), the holes form a vertical line 38.38'
, 38'', where the base potential change will stop and be clipped. Therefore, the emitters of vertically adjacent photosensor cells will flow through the vertical line 38., 38''.
Even if they are commonly connected by 38'38'', if you ground the vertical lines 38.38' and 38'' like this,
No blooming phenomenon occurs.

To avoid this blooming phenomenon, even if the MOS transistors 48, 48' and 48'' are made non-conductive and the vertical lines 38, 38' and 38'' are left in a floating state, the substrate potential, that is, the collector potential 64, is slightly reduced. This can also be achieved by setting the potential to be negative, and when the base potential changes to a positive potential due to accumulation of holes, it flows toward the collector side before the emitter.

Following the accumulation section 62, a readout section 63 begins at time t. At this time ts, the MOS transistor 48
．． 48', 48'', the potential 65 of the gate terminal 49 is lo
w, and the potential 68 of the gate terminals of the buffer MOS transistors 33.33', 33" of the horizontal lines 31.31', 31" is set to high, thereby making each MOS transistor conductive. However, this gate terminal 3
The timing for setting the potential 68 of No. 4 to high is at time ts.
It is not a necessary condition that the time is earlier than that.

At time t4, among the outputs of the vertical shift register 32,
The waveform 69 connected to the horizontal line 31 is <h
At this time, since the MOS transistor 33 is in a conductive state, the MOS transistor 33 connected to this horizontal line 31
The reading of each optical sensor cell is performed. This readout operation is as described above, and the signal voltage generated by the signal charge accumulated in the base region of each photosensor cell appears as it is on the vertical line 38.38'38''.The vertical shift at this time As shown in FIG. 8, the pulse width of the pulse voltage from the register 32 is set to a pulse width that maintains a sufficient linearity between the read voltage and the accumulated voltage. Similarly, the emitter is adjusted to be forward biased by V□1°.

Next, at time t@, among the outputs of the horizontal shift register 39, only the output to the gate of the MOS transistor 40 connected to the vertical line 38 has a waveform 70 (h
high, the MOS transistor 40 becomes conductive, and the output signal passes through the output line 41 and enters the output transistor 44, where the current is amplified and output from the output terminal 47. After the signal is read out in this way, the output line 41
Since there remains signal charge due to the wiring capacitance, at time ta, a pulse as shown in the pulse waveform 71 is applied to the gate terminal 43 of the MOS transistor 42, and the MOS
) The remaining signal charge is refreshed by turning on the transistor 42 and grounding the output line 41. Similarly, the switching MOS transistors 40, 40', 40'' are sequentially turned on to read the signal outputs of the vertical lines 38, 38', 38''. After reading the signals from each of the horizontally lined photosensor cells in this way, the vertical lines 38, 38', 38
'', similar to the output line 41, there remains signal charge due to its wiring capacitance, so each vertical line 38.
MOS transistor 48 connected to 38' and 38''
．． 48'48'' is brought to its gate terminal 49 high and conductive as shown by waveform 65 to refresh this residual signal charge.

Next, at time ta, among the outputs of the vertical shift register 32, the output connected to the horizontal line 31' becomes <high at the end of the waveform 69', and the accumulated voltage of each photosensor cell connected to the horizontal line 31' becomes each vertical line 3
8.38'38''. Thereafter, signals are sequentially read out from the output terminal 47 by the same operations as before.

In the above explanation, the storage section 62 and the readout section 63 are
The explanation has been given of an application field in which there are clear divisions, such as still video, for which research and development has been actively conducted recently. The present invention can also be applied to fields of application in which the operations in FIG. 10 are performed simultaneously by changing the pulse timing shown in FIG. However, the refresh at this time requires a line-by-line refresh function rather than a full-screen refresh. For example, after the signals of each photosensor cell connected to the horizontal line 31 are read out, the MOS transistors 48°48' and 48'' are turned on at time t7 to erase the charge remaining on each vertical line. In other words, by using a vertical shift register configured to generate pulses with different pulse voltages and pulse widths at time t in the waveform 69 as well as at time t. In addition to this double-pulse operation, instead of the device that applies the batch refresh pulse installed on the right side of Figure 3, a second vertical shift register similar to the one on the left side is also installed on the right side. It is also possible to achieve this by providing a vertical register and operating the register with timing shifted from that of the vertical register provided on the left side.

At this time, in the accumulation state as described above, the degree of freedom in controlling blooming by controlling the potentials of the emitter and collector of each photosensor cell is reduced. However, as explained in the basic operation section, in the read state, the base voltage is V□1. Since the structure is such that high-speed reading is possible when applying a bias voltage of
', 28'' is extremely small, and the blooming phenomenon is not a problem at all.

Moreover, the photoelectric conversion device according to this configuration example can obtain extremely excellent characteristics with respect to the smear phenomenon. The smear phenomenon is an operational and structural problem that occurs in CCD type imaging devices, especially frame transfer type, in which charge is transferred to the area irradiated with light. This problem occurs because carriers generated deep in the semiconductor due to light are accumulated in the charge transfer section.

Furthermore, in a MOS type imaging device, this problem arises because carriers generated deep in the semiconductor due to long wavelength light are accumulated on the drain side of the switching MOS transistor grounded in each photosensor cell.

On the other hand, in the photoelectric conversion device according to this configuration example, there is no smear phenomenon that occurs due to its operation and structure, and there is no phenomenon that carriers generated deep in the semiconductor are accumulated due to long wavelength light. However, of the electrons and holes generated relatively near the surface of the emitter of the photosensor cell, there is a concern that the electrons will be accumulated. Since it is grounded, electrons are not accumulated and no smear phenomenon occurs. In addition, during the line refresh operation applied to ordinary television cameras, during the horizontal blanking period, the vertical line is grounded and refreshed before reading out the accumulated voltage on the vertical line, so at the same time the emitter is The electrons accumulated during one horizontal scanning period flow out, and therefore almost no smear phenomenon occurs. In this way, in the photoelectric conversion device according to this example,
Due to its structure and operation, smear development occurs to an essentially negligible extent, which is one of the major advantages of the photoelectric conversion device according to this configuration example.

Further, although the operation of suppressing the blooming phenomenon by manipulating the emitter and collector potentials in the storage operation state has been described above, it is also possible to use this to control the γ characteristics.

In other words, during the storage operation, the potential of the emitter or collector is temporarily set to a certain negative potential, and of the carriers accumulated in the base, the number of holes accumulated in the emitter is greater than the number of carriers that give this negative potential. Alternatively, the data may be flowed to the collector side. As a result, the relationship between the accumulated voltage and the amount of incident light exhibits the γ=1 characteristic of silicon crystal when the amount of incident light is small.
In areas where the amount of incident light is large, it exhibits a characteristic in which γ is smaller than 1, that is, it is possible to provide a characteristic of γ=0.45, which is normally required for a television camera, using a polygonal approximation. If the above operation is performed once during the storage operation, it becomes a one-fold line approximation, and by appropriately changing the negative potential applied to the emitter or collector, it is also possible to have a two-fold line type γ characteristic.

Further, in the above configuration example, the silicon substrate is used as a common collector, but a buried n0 region may be provided like a normal bipolar transistor, and the collector may be divided for each line.

Note that for actual operation, a clock pulse for driving the vertical shift register 32 and the horizontal shift register 39 is required in addition to the pulse timing shown in FIG. 10(a).

FIG. 11 shows an equivalent circuit related to the output signal.

The capacitance CV80 is the wiring capacitance of the vertical line 38.38'38'', and the capacitance 0881 is the wiring capacitance of the output line 41.The equivalent circuit on the right side of FIG. 9 is in the read state, and the switching MOS transistors 40, 40' and 40'' are in a conductive state,
Its resistance value in the conductive state is shown by resistor R282. Further, the amplifying transistor 44 is connected to a resistor r.

An equivalent circuit using a current source 83 and a current source 84 is shown.

The MOS transistor 42 for refreshing the charge accumulation caused by the wiring capacitance of the output line 41 is non-conductive in the read state and has high impedance.
It is omitted in the equivalent circuit on the right.

Each parameter of the equivalent circuit is determined by the size of the photoelectric conversion device actually constructed. For example, the capacitance CV80 is about 4 pF, the capacitance C,8t is about 4 pF,
FIG. 12 shows an example of calculating the output signal waveform observed at the output terminal 47, assuming that the resistor R 82 in the conducting state of the transistor (MOS) is about 3Ω, and the current amplification factor β of the bipolar transistor 44 is about 100. Shown below.

In FIG. 12, the horizontal axis represents the time from the moment when the switching MOS transistors 40, 40', 40'' conduct
μS], and the vertical axis is the output voltage [[μS] appearing at the output terminal 47 when a signal charge is read out from each photosensor cell and a voltage of 1 volt is applied to the wiring capacitance Cv80 of the vertical line 38°38', 38''. V] respectively.

The output signal waveform 85 is the load resistance R, 45 is 10Ω, 86
The load resistance R845 is 5Ω, and the load resistance R87 is 45Ω.
is 2Ω, and the peak value in both cases is about 0.5V due to the capacitance division between Cv80 and CH31. Naturally, the load resistance R245
The larger the value, the smaller the attenuation amount and the more desirable the output waveform. The rise time is as fast as about 20 nsec when the above parameter values are used. switching MOS
By reducing the resistance R4 in the conductive state of the transistor 40.40'40'', and by reducing the wiring capacitance Cv
, C,4, even faster reading is possible.

In a photoelectric conversion device using optical sensor cells having the above configuration, the voltage appearing at the output is large due to the amplification function of each optical sensor cell, so the amplification amplifier at the final stage is also a MOS
The above example uses a single-stage bipolar transistor type, but it is natural to use other systems such as a two-stage type imaging device. However, it is possible. When bipolar transistors are used as in this example, the problem of 1/f noise that is easily noticeable on images generated from the MOS transistor of the final stage amplifier in a CCD imaging device does not occur in the photoelectric conversion device of this configuration example. , it is possible to obtain image quality with an extremely good S/N ratio.

Next, embodiments of the photoelectric conversion device of the present invention will be described.

In this embodiment, as shown in FIGS. 1 and 2, a transistor is provided as the second switch means, which improves the inconvenience caused by transient refresh, and allows the switch to be used even when any amount of light is irradiated. , afterimages, noise, and variations in output from cell to cell are hardly a problem, and it is possible to refresh at a higher speed than the photoelectric conversion device of the above configuration example.

FIG. 10(b) shows potential levels at the emitter, base, and collector portions during a cycle of transient refresh operation, storage operation, read operation, and transient refresh operation. The voltage level at each location is the potential seen externally, and there are some locations that do not match the internal potential level.

To simplify the explanation, the emitter-base diffusion potential is excluded. Therefore, when the emitter and base are shown at the same level in FIG. 10(b), there is actually a diffusion potential applied between the emitter and base.

In FIG. 10(b), states (2) and (2) indicate a refresh operation, state (2) an accumulation operation, states (2) and (2) a read operation, and state (2) an operating state when the emitter is grounded. Further, the potential level indicates a negative potential on the upper side and a positive potential on the lower side with O volt as the boundary. It is assumed that the base potential before state (2) is zero volts, and that the collector potential is biased to positive potential in all states (2) to (4).

The above series of operations will be explained with reference to the timing diagram of FIG. 10(a).

When a positive potential, that is, a refresh voltage VRH is applied to the terminal 37 at time tl as shown by the waveform 67 in FIG. As explained, a partial pressure of . This potential gradually decreases toward zero potential from time tl to t2, and at time t2 reaches the potential 201 shown by the dotted line in FIG. 10(b). As explained earlier, this potential is the potential 8 that remains at the base in the transient refresh mode. At time tl, as shown in waveform 67, at the moment when the refresh voltage VRH returns to zero voltage, the voltage that becomes the base is generated by capacitance division as before, so the base is connected to the remaining voltage vK and a newly generated voltage. The potential is the sum of the voltage and the voltage. That is, the base potential 202 shown in state (2) is given by:

When light enters such an emitter in a reverse bias state, holes generated by this light are accumulated in the base region, so as shown in state (2), depending on the intensity of the incident light, Base potential 202 is base potential 203
, 203', 203''. The voltage generated by this light is assumed to be .

Next, as shown in waveform 69, when a voltage, that is, readout voltage (8) is applied to the horizontal line from the vertical shift register, the voltage that becomes the base is added, so the base potential 204 when no light is irradiated is Become. As explained earlier, the potential 204 at this time is
It is set so that the emitter is forward biased by about 0.5 to 0.6 V. Also, the base potential 20
5.205' and 205'' are given respectively.

When the base potential is biased in the forward direction with respect to the emitter in this manner, electron injection occurs from the emitter side, and the emitter potential gradually moves in the positive potential direction. Base potential 204 when no light is irradiated
The emitter potential 206 for the forward bias is set to 0.
When set to 5-0.6V, read pulse width is 1-2μs
When the voltage is approximately 50 to 100mV, if this voltage is V, then the emitter potential is 207.207' 2
07'', as in the previous example, linearity is sufficiently ensured if the pulse width is 0.1jLs or more, so each Vp +V
a, Vp'+Va, and Vp+V.

After a certain readout time, when the readout voltage VII reaches zero potential as shown in waveform 69, a voltage is added to the base, so the base potential becomes the same as before the readout pulse is applied, as shown in state (2). state, that is, a reverse bias state, and the emitter potential stops changing. That is, the base potential 208 at this time is given by the base potentials 209.209' and 209'', respectively.

This is the state before reading begins■ is exactly the same.

In this state (2), the optical information signal on the emitter side is read out to the outside. After this readout, each switching MOS transistor 48.48'48''
becomes conductive, the emitter is grounded, and the emitter becomes zero potential as in state (2). This completes the cycle of refresh operation, storage operation, and read operation, and then returns to state ①. At this time, before entering the refresh operation for the first time, the base potential started from zero potential, whereas After the − cycle, the base potential becomes and,
The potentials have changed to the sum of vP, vP, and VP'', respectively. Therefore, in this state, even if the refresh voltage VRH is applied, the base potentials are VK, Vm +Vp %Vx +Vp', respectively.
VK + VP”, and in this case, sufficient forward bias is not applied to the base, and the amount of forward bias is large in areas that are strongly hit by light, so the optical information disappears, but the information in the areas where the light is weak is lost. It is clear from the example calculation of the refresh operation shown in FIG.

Such a phenomenon is unique to the transient refresh mode, and such a problem does not occur in the complete refresh mode because it takes a long refresh time until the base potential always reaches zero potential.

A method that uses a transient refresh mode that allows high-speed refresh and that does not cause such inconvenience will be described below.

One way to solve this problem is that in state (2), the base potential 210 is too negative, that is, in the reverse bias direction with respect to the emitter, and in the next state (2), before the refresh pulse is applied. All that is required is to bring the base potential 210 to zero potential or to a slightly positive potential by some method.

FIG. 1(a) shows a cross-sectional view of an optical sensor cell for achieving this, FIG. 1(b) shows its equivalent circuit diagram, and FIG. 1(C) shows an internal potential diagram.

FIG. 1(a) differs from the sensor cell shown in FIG. 6 only in the presence of a buried p9 region 220. Figure 1 (
The equivalent circuit diagram of b) shows a pnp transistor 221 in which the base region 6 of the sensor cell is the collector, the buried p0 region 220 is the emitter, and a part of the high resistance n-region 5 between the base region 6 and the collector region 1 is the base. is added.

The base region of the pnp transistor is loosely coupled to the collector region l of the sensor cell, and is shown by a dotted line in the equivalent circuit. Also, this embedded p
The region 220 is connected like a wiring 222 inside the crystal, and has a structure that allows voltage to be applied from outside the sensor area.

As is clear from FIG. 1(b), the p° embedded region 220
forms one line in the horizontal line direction as shown at 222, so in reality, the line shown in Fig. 1(a)
In this case, it should be shown as a p0 embedded region that continues from left to right.

In FIG. 1(a), a part of the p0 region is schematically shown for clarity.

The potential for internal electrons is shown in Figure 1 (c
), and the potential distribution in the vertical section not including the buried p0 region 220 is no different from that shown in FIG. 10(b), but including the buried p0 region 220.
The potential distribution in the vertical section has a potential distribution as shown by a dotted line 223. However, this figure shows a potential distribution when the buried p1 region 220 is biased to a slightly positive potential. In this state, when the buried p0 region 220 is further biased toward a positive potential, the n- region existing therebetween becomes completely bunch-through, and the p'
Holes flow into the base area 6 of the sensor cell from the ``area, and the holes flow into the base area 6 of the sensor cell.
The potential moves in the positive potential direction.

To make the n- region into a punch-through state and allow holes to flow from the p0 region 220 into the p base region, the thickness d of the n- region, the impurity density N, and the voltage applied to the p'' region 220 are set as follows.
1, it is designed as follows. vl is the diffusion potential of the p"n-junction.

Therefore, in state ■ of FIG. 10(b), the embedded p
Applying a positive voltage to the 0 region 220 through the wiring 222,
By injecting holes into the p-base region, it is possible to solve the undesirable phenomena in the transient refresh mode by bringing the base potential 210 to a zero potential or a slightly positive potential, as explained above. At this time, the voltage applied to the buried p0 region 220 is a voltage slightly smaller than the voltage applied to the sensor cell collector 1, that is, the voltage applied to the buried p+ region 220 and the n region l of the collector.
It is possible to sufficiently pass holes into the base region 6 in such a state that no forward bias occurs.

The impurity (usually boron) that forms the p0 region generally has a large diffusion constant, which causes autodoping and diffusion problems when forming the high resistance n-region 5 using epitaxial technology. , measures are taken to suppress autodoping and diffusion from the buried p0 region as much as possible.

The above-mentioned embodiment differs only in that a buried p3 region is added by diffusion or ion implantation to the basic photosensor cell described above, and the manufacturing method for the subsequent portions may be exactly the same.

FIG. 2 shows a sectional view of an optical sensor cell for explaining another embodiment. In the cross-sectional view shown in FIG. 2, instead of the buried P region 220 shown in FIG. . A pnph transistor is constructed in which the P region 224 is used as an emitter, the low impurity n- region 5 is used as a base, and the base 6 of the photosensor cell is used as a collector. This is because the structure shown in FIG. 1 previously formed a vertically structured pnp transistor, whereas a horizontally structured pnp transistor is formed. Therefore, in the embodiment of FIG. 2, voltage is supplied to the P region 224 via the wiring 225 on the front side.

The equivalent circuit of the embodiment shown in FIG. 2 is exactly the same as the equivalent circuit shown in FIG. 1(b), although the pnp transistor has a vertical structure and a horizontal structure.
Its operation is exactly the same as that already described.

In the cross-sectional view shown in FIG. 2, the p" region 224 and its wiring 225 are all drawn in the same cross section as the MOS capacitor electrode 9, emitter region 7, and wiring 8 for convenience of explanation, but they are the same. It is also possible to arrange it in other parts of the optical sensor cell, and this will be determined by design factors such as the shape of the window through which light enters and the wiring.

As already mentioned, in a photoelectric conversion device using a photosensor cell having the above-mentioned configuration, the amplification amplifier in the final stage can be extremely simple, so the configuration shown in Fig. 3 in which only one amplification amplifier in the final stage is provided Instead of the type of configuration example shown, it is also possible to install a plurality of amplifiers so that one screen is divided into a plurality of parts and read out.

FIG. 13 shows an example of a divided readout system. In the configuration example shown in FIG. 13, the horizontal direction is divided into three, and the final stage amplifier is
This is an example of installing one. The basic operation is almost the same as that explained using the configuration example in FIG. 3 and the timing diagram in FIG. 10, but in the configuration example in FIG. .102 and a terminal 103 for applying these starting pulses.
When a starting pulse is applied to the 1st column, (n+1) column, and (2
The outputs of the sensor cells connected to the (n+1)th column (n is an integer, and in this configuration example, the number of picture elements in the horizontal direction is 3n) are read out simultaneously. At the next point,
The second column, (n+2) column, and (2n+2) column will be read. According to this embodiment, when the time to read out - horizontal lines is fixed, the scanning frequency in the horizontal direction is 1/3 that of the system with one final stage amplifier. A high-speed analog-to-digital converter is unnecessary for applications where the frequency is sufficient, the horizontal shift range sensor is simple, and the output signal from a photoelectric conversion device is converted into analog-to-digital for signal processing.
This is a major advantage of the divided readout method.

In the configuration example shown in FIG. 13, three equivalent horizontal shift registers are provided, but the same function can be provided with only one horizontal shift register.

An example of the configuration in this case is shown in FIG.

The configuration example in FIG. 14 depicts only the horizontal switching MOS transistor and the middle part of the final stage amplifier of the configuration example shown in FIG. 13, and the other parts are the configuration shown in FIG. It is omitted because it is the same as the example.

In this embodiment, the output from one horizontal shift register 104 is connected to the gates of the switching MOS transistors in the 1st column, (n+1) column, and (2n+1) column, and these lines are read out simultaneously. There is. At the next time, the second column, (n+2) column, and (2n+2) column are read out.

According to this configuration example, although the number of wirings to the gates of each switching MOS transistor increases, it is possible to operate with only one horizontal shift register.

In the examples shown in FIGS. 13 and 14, three output amplifiers are provided, but it goes without saying that this number may be increased depending on the purpose.

In both the configuration examples shown in Figures 13 and 14, the starting pulses and clock pulses for the horizontal shift register and vertical shift register are omitted, but like other refresh pulses, they are provided within the same chip. It is supplied from a clock pulse generator or a clock pulse generator provided on another chip.

In this split readout method, horizontal lines - all or the entire screen -
When a batch refresh is performed, the accumulation time is slightly different between the photosensor cells in the n-th and (n+1) columns, which causes a slight discontinuity in the dark current component and the signal component, causing the upper part of the image to change. Although it is possible that
This amount is small and poses no practical problem. Furthermore, even if this exceeds the allowable limit, correcting it using an external circuit will generate a square wave, subtracting this from the dark current component, and multiplying and dividing this by the signal component. This is easily possible using conventional correction techniques.

When capturing a color image using such a photoelectric conversion device, a stripe filter, a mosaic filter, etc. is installed on-chip on the photoelectric conversion device, or
It is possible to obtain a color signal by pasting together separately manufactured color filters.

As an example, when R, G, and H strip filters are used, in a photoelectric conversion device using the photosensor cell according to the above configuration, the R signal and
It is possible to obtain a G signal and a B signal. An example of this configuration is shown in FIG. This figure 15 is similar to figure 14,
Only the area around the horizontal shift register is shown. The rest is the same as Fig. 3 and Fig. 13, except that the first column is an R color filter, the second column is a G color filter, and the third column is a G color filter.
It is assumed that color filters are attached, such as the B color filter for the eyes and the R color filter for the fourth column. As shown in FIG. 15, each vertical line of the first, fourth, seventh column, etc. is connected to an output line 110, which is R
Take out the signal.

Further, each vertical line of the second column, fifth column, eighth column, etc. is connected to an output line 111, which takes out the G signal. Similarly, each vertical line in the third, sixth, ninth column, etc. takes out the B signal connected to the output line 112. The output lines 110, 111 and 112 are respectively connected to an on-chip refresh MOS transistor and a final stage amplifier, for example, an emitter follower type bipolar transistor, and each color signal is output separately.

6 A diagram for explaining the basic structure and operation of another example of a photosensor cell constituting a photoelectric conversion device according to another modification of the present invention is shown in FIG. Further, its equivalent circuit and overall circuit configuration diagram are shown in FIG. 17(a).

The photosensor cell shown in FIG. 16 is an photosensor cell that can simultaneously perform a read operation and a line refresh using the same horizontal scan pulse. No. 1,
16, the difference from the configuration already shown in FIG. 6 is that in the case of FIG. 6, the MO connected to the horizontal line wiring lO
Although there was only one S capacitor electrode 9, there were also MOS capacitor electrodes 12 on the sides of the vertically adjacent optical sensor cells.
0 is connected, and when viewed from one photosensor cell, it is a double capacitor type. In the figure, the emitters 7.7゛ of the vertically adjacent photosensor cells are 2
Layered wiring■8. and wiring ■121, (first
In Fig. 6, the vertical line appears to be one, but two lines are arranged through the insulating layer). In other words, the emitter 7 is connected to the wiring through the contact hole 19.
8, the difference is that the emitters 7' are respectively connected to the wirings 121 through contact holes 19'.

This becomes clearer when looking at the equivalent circuit shown in FIG. 17(a). That is, the MOS capacitor 150 connected to the base of the photosensor cell 152 is connected to the horizontal line 31, and the MOS capacitor 151 is connected to the horizontal line 31'.

Further, in the diagram of the optical sensor cell 152, the MOS capacitors 150' of the adjacent optical sensor cells 152' below are connected to a common horizontal line 31'.

The emitter of photosensor cell 152 is placed in vertical line 38, the emitter of photosensor cell 152' is placed in vertical line 138,
The emitters of the photosensor cells 152'' are connected alternately in vertical lines 38.

In the equivalent circuit of FIG. 17(a), other than the basic photosensor cell section described above, the only difference from the imaging device of FIG. 3 is the switching M for refreshing the vertical line 38.
Switching MOS transistor 1 for refreshing the vertical line 138 of the OS transistor 48
48, and a switching M selecting vertical line 38.
In addition to the OS transistor 40, a switching MOS transistor 140 for selecting the vertical line 138 is added, and one output amplifier system is added. The configuration of this output system is as shown in FIG. 17(b), in which switching MOS transistors 48 and 148 are connected for refreshing each line, and a switching MOS transistor for horizontal scanning is used. A configuration with only one output amplifier is also possible. FIG. 17(b) shows only the vertical line selection and output amplifier system portions of FIG. 17(a).

According to the optical sensor cell shown in FIG. 16 and the configuration example shown in FIG. 17(a), the following operations are possible. That is, when the readout operation of each optical sensor cell connected to all the horizontal lines 31 is completed and it is in the horizontal blanking period in the television operation, the output pulse from the vertical shift register 32 is outputted to the horizontal line 31'. 151, the optical sensor cell 152 that has been read out
refresh. At this time, the switching MOS transistor 48 is rendered conductive, and the vertical line 38 is grounded.

Further, the output of the photosensor cell 152' is read out to the vertical line 138 through the MOS capacitor 150' connected to the horizontal line 31'. At this time, the switching MOS transistor 148 is naturally rendered non-conductive, and the vertical line 138 is in a floating state. In this way, with one vertical scan pulse, it is possible to simultaneously refresh the photosensor cells that have already been read out and read out the photosensor cells of the next line using the same pulse. At this time, as already explained, the voltage at the time of refreshing and the voltage at the time of reading are
At the time of readout, the bias voltage is applied due to the necessity of high-speed readout, so the difference is different, but as shown in FIG. 16, the same voltage can be applied to each electrode by changing the area of the MOS capacitor electrode 9 and the MOS capacitor electrode 120. This is achieved by adopting a configuration in which different voltages are applied to the base of each photosensor cell even when applied.

In other words, the area of the refresh MOS capacitor is
The area is smaller than that of the read MOS capacitor. As in this example, when refreshing the sensor cells line by line instead of refreshing all the sensor cells at once, the collector is
Although it may be constructed using a type or n-type substrate, it may be desirable to provide separate collectors for each horizontal line. When the collector is a substrate, the collectors of all the photosensor cells are a common area, so that a constant bias voltage is applied to the collectors in the storage and light reception/readout states. Of course, as already explained, floating base refresh can be performed between the emitters even with a bias voltage applied to the collector. However, in this case, there is a drawback that at the same time that the base region is refreshed, a wasteful current flows between the emitter and collector of the cell to which the refresh pulse is applied, increasing power consumption. In order to overcome these drawbacks, instead of making the collectors of all the sensor cells a common area, the collectors of the sensor cells arranged in each horizontal line are common, but the collectors of each horizontal line are structured to be separated from each other. That is, in connection with the structure shown in FIG. 6, the substrate is of a p-type, and the p-type substrate has a structure in which n buried regions separated from each other are provided for each horizontal line of the collector. The n buried regions of adjacent horizontal lines may be separated by a p region interposed therebetween. Dielectric isolation is better for reducing buried collector capacitors along horizontal lines. In Figure 6,
Since the collector consists of a substrate, all isolation regions surrounding the sensor cell are provided to approximately the same depth. On the other hand, in order to separate the collectors of each horizontal line from each other, the separation area in the horizontal line direction is made deeper than the separation area in the vertical line direction by a necessary value.

If the collector is separated for each horizontal line, if the voltage of the collector of that horizontal line is grounded when reading is finished and the refresh operation starts, the emitter-collector current as described above will not flow, and the power consumption will be reduced. does not result in an increase in When refreshing is completed and a charge storage operation based on an optical signal begins, a predetermined bias voltage is applied to the collector region again.

According to the equivalent circuit shown in FIG. 17(a), outputs are alternately output to the output terminals 47 and 147 for each horizontal line. As already explained, this is the first
It is also possible to take out the output from one amplifier by using a configuration as shown in FIG. 7(b).

As explained above, according to this configuration example, line refreshing is possible with a relatively simple configuration, and it can be applied to ordinary application fields such as television cameras.

Other configuration examples of the present invention include a type in which a plurality of outputs are extracted from one photosensor cell by a structure in which the photosensor cell is provided with a plurality of emitters, or a structure in which one emitter is provided with a plurality of contacts.

This is because each optical sensor cell of the photoelectric conversion device according to the present invention has an amplification function, so even if multiple wiring capacitors are connected to each optical sensor cell in order to extract multiple outputs from one optical sensor cell, the optical sensor cell This is due to the fact that the internally generated accumulated voltage Vp can be read out to each output without attenuating at all.

In this way, by having a configuration in which multiple outputs can be taken out from each optical sensor cell, many advantages can be added to the photoelectric conversion device formed by arranging a large number of each optical sensor cell in terms of signal processing, noise countermeasures, etc. is possible.

Next, an example of a method for manufacturing a photoelectric conversion device according to the present invention will be described. Figure 18 shows selective epitaxial growth (N,
Endo et al, ”Novel devi
ce 1solatton technology w
ith 5elected epitaxial gr
owth” Tech, Dig, of 1982
An example of its production method using IE DM, pp, 241-244 is shown below. l~10X 10”
An n+ region 11 for contact is provided on the back side of an n-type Si substrate 1 with an impurity concentration of about 1.5 cm-cm by diffusion of As or P. It is not shown in the figure to prevent autodoping of the n+ region. However, an oxide film and a nitride film are usually provided on the back surface.

The substrate 1 used has impurity concentration and oxygen concentration controlled to be uniform. That is, a crystal wafer having a sufficiently long and uniform carrier line time is used. For example, a crystal produced by the MCZ method is suitable as such a material. An oxide film approximately 1 μm thick is formed on the surface of the substrate 1 by wet oxidation. That is, it is oxidized in a HaO atmosphere or a (Ha + Oa ) atmosphere. High-pressure oxidation at a temperature of about 900° C. is suitable for obtaining a good oxide film without producing stacking faults or the like.

On top of that, SiO with a thickness of, for example, about 2 to 4 μm is applied.
Deposit the z film by CVD. (Ni”5LH4+02
) A 5iOa film of desired thickness is deposited in a gas system at a temperature of about 300 to 500°C. 0. The molar ratio of /S i H4 is set to about 4 to 40, although it depends on the temperature. Through the photolithography process, the oxide film in the other regions is (CF4 +82), leaving only the oxide film in the area that will become the isolation region between cells.
, Cm F4.

For example, remove by using a gas such as CHaFa or by active ion etching (step (a) in FIG.
When one pixel is provided in 010×10u, the SiOz film is left in a mesh shape with a pitch of 10 μm. The width of the 5iO- film is selected to be, for example, about 2 μm. The damaged and contaminated layers on the surface are removed by reactive ion etching.
After removal by A r / Cl□ gas-based plasma etching or wet etching, evaporation in an ultra-high vacuum, sputtering with a sufficiently clean atmosphere in a load-lock format, or CO to SiH4 gas is performed.
Amorphous silicon 301 is deposited by low pressure CVD using two laser beams (step (b)' in FIG. 18).
, CBrF*, CC1t pg, C1□, etc., or by anisotropic etching using active ion etching to remove amorphous silicon other than those deposited on the side surfaces of the SiOm layer (step (c) in FIG. 18). )
, As before, after sufficiently removing the damaged layer and the contamination layer, the silicon substrate surface was thoroughly cleaned, and (H2+5i
Ha.

C1, +HC1) A silicon layer is selectively grown using a gas system. Growth is performed under reduced pressure of several tens of Torr, and the substrate temperature is set to 900 to 1000 molar ratio of HCl to a certain high value. If the amount of HCI is too small, selective growth will not occur. There is no silicon on the silicon substrate. A crystal layer grows, but the silicon on the S i 02 layer is H
Because it is etched by CI, Sing!
No silicon is deposited thereon (FIG. 18(d)).

The thickness of n-j15 is, for example, about 3 to 5 μm.

The impurity concentration is preferably set to about IQ 12 to 10"cm-". Of course, it is possible to deviate from this range, but p
It is desirable to select an impurity concentration and thickness such that at least the n- region is completely depleted at the diffusion potential of the n=junction, or at least the n- region is completely depleted when an operating voltage is applied to the collector.

(Usually available) (Cl gas contains a large amount of water, so an oxide film is constantly formed on the silicon substrate surface, making it impossible to expect high-quality epitaxial growth. When HCI is in a cylinder, it reacts with the cylinder material and contains a large amount of heavy metals, mainly iron, which tends to result in an epitaxial layer with a lot of heavy metal contamination.The epitaxial layer used in the optical sensor cell is Since it is desirable to have a low dark current component, it is necessary to suppress contamination by heavy metals to the utmost limit.Of course, ultra-high purity materials are used for SiH, C1, and HCI is particularly low in moisture. , preferably one with a water content of at least 0.5 ppm or less.Of course, the lower the water content, the better.In order to further improve the quality of the epitaxial growth layer, the substrate is first treated at a high temperature of about 1150 to 1250°C. It is also extremely effective to remove oxygen from near the surface and then generate a large number of micro-defects inside the substrate by heat treatment at about 800°C for a long time to create a substrate that has a denuded zone and is capable of indolithic gettering. Since epitaxial growth is performed in the presence of the SiO□ layer 4 as an isolation region, the lower the growth temperature is, the better, in order to reduce the incorporation of oxygen from SiO2. However, there is a lot of contamination from the carbon susceptor, making it difficult to lower the temperature further.Direct heating of the wafer using lamp heating without bringing the carbon susceptor into the reaction chamber provides the cleanest growth atmosphere, allowing high-quality epitaxial layers to be grown at low temperatures. be made to grow.

Ultra-high purity fused sapphire, which has a lower vapor pressure, is suitable for the wafer support in the reaction chamber. The wafer direct heating method using lamp heating allows for easy preheating of the raw material gas and makes it easy to equalize the temperature within the wafer surface even when a large flow rate of gas is flowing.In other words, the wafer direct heating method using lamp heating generates almost no thermal stress, and is capable of producing high-quality epitaxial layers. suitable for getting. UV irradiation of the wafer surface during growth further improves the quality of the epitaxial layer.

Amorphous silicon is deposited on the sidewalls of the Si0g layer that will become the isolation region 4 (step (C) in FIG. 18). Since amorphous silicon easily becomes a single crystal through solid-phase growth, S
The crystals near the interface with the ing isolation region 4 become very good. After forming a high resistance n''M5 by selective epitaxial growth (step (d) in FIG. 18), a P region 6 with a surface concentration of about 1 to 20 x 10 ``cm'' is formed by diffusion from doped oxide or It is formed to a predetermined depth by diffusion using a low-dose ion-implanted layer as a source.The d-pattern of p region 6 is, for example, about 0.6 to 1 μm.

The thickness and impurity concentration of p region 6 are determined based on the following considerations. In order to increase the sensitivity, it is desirable to lower the impurity concentration in the p region 6 to reduce Cbe. Cbe is given approximately as follows.

However, Vbi is the emitter-base diffusion potential and is given by: Here, ε is the dielectric constant of silicon crystal, N
fl is the impurity concentration of the emitter, NA is the impurity density of the portion of the base adjacent to the emitter, and n is the direct carrier concentration. The smaller the NA, the smaller the Cbe,
Although the sensitivity increases, if the NA is made too small, the base region will be completely depleted in the operating state, resulting in a punch-through state, so it cannot be made too low. It is set to such an extent that the base region is not completely depleted and a punch-through state occurs.

Thereafter, a thermal oxide film 3 having a thickness of about 10 to 100 layers is formed on the surface of the silicon substrate by (H2+O,) gas-based steam oxidation at a temperature of about 800 to 900.degree.

A nitride film (SiaN-) 302 is formed thereon to a thickness of about 500 to 1,500 layers by CVD using (siH4+NH3)-based gas. The formation temperature is about 700 to 900°C.

NH and gas, as well as HCI gas, are commonly available products that contain a large amount of water. If NH or gas with a high moisture content is used as a raw material, the resulting film will be a nitride film with a high oxygen concentration, resulting in poor reproducibility and the subsequent selective etching with the 5iOa film resulting in an inability to obtain a selectivity. NH,
The gas should also have a moisture content of at least 0.5 ppm or less. It goes without saying that a lower water content is more desirable, and a PSG film 300 is further deposited on the nitride film 302 by CVD. For gas systems, for example, (N2
+S i H4+O* +PH3) from 300 to
A PSG film with a thickness of about 200 to 3000 layers is deposited by CVD at a temperature of about 450°C (step shown in Fig. 18).
e)). By a photolithography process including two mask alignment processes, an As-doped polysilicon film 304 is deposited on the n4 region 7 and on the refresh and read pulse application electrodes. In this case, a p-doped polysilicon film may be used. For example, by two photolithography steps, a PSG film, 5L3N4
Membrane, S l O! The film is completely removed, and the underlying sinusoids are placed in the areas where the refresh and readout pulse application electrodes are to be provided.
, only the PSG film and the 5isN4 film are etched, leaving the film intact. After that, As-doped polysilicon (N2+
S i H4+AsHa ) or (Ha+SiH4
Deposited by CVD method using AsHa) gas.

Deposition temperature is about 550℃~700'C, film thickness is 1000℃
~2000 Å. CV of non-doped polysilicon
Of course, it is also possible to deposit by method D and then diffuse As or P. After the mask alignment photolithography process, the polysilicon film in other parts except on the emitter and on the refresh and read pulse applying electrodes is removed by etching. Furthermore, when the PSG film is etched, the polysilicon deposited on the PSG film is removed in a self-aligned manner due to lift-off (step (f) in Figure 18).
)). Etching of polysilicon film is ca C1,F,
, (CBrFs +c 12) or the like, and the 5isN4 film is etched with a gas such as CH2F2.

Next, a PSG film 305 is deposited by the gas-based CVD method as described above, and then a contact hole is formed on the polysilicon film for the refresh pulse and read pulse electrodes by a mask alignment process and an etching process. In this state, metals such as AI, Al-5i, Al-Cu-5i, etc. are deposited by vacuum evaporation or sputtering.
A by a plasma CVD method using lg as a raw material gas, or by a light irradiation CVD method in which the At-C bond or Al-Cl bond of the above raw material gas is cut by direct light irradiation.
Deposit I. (CHI) Al or A I Cl s
When carrying out the above-mentioned CVD method using hydrogen as a raw material gas, a large excess of hydrogen is allowed to flow. To deposit Al into a narrow and steep contact hole, a thickness of 300 to 400" is required in a clean atmosphere with no moisture or oxygen contamination.
The CVD method, which increases the substrate temperature to a C film thickness, is superior. 6th
After finishing the patterning of the metal wiring 10 shown in the figure,
A glabellar insulating film 306 is deposited by CVD.

306 is the above-mentioned PSG film or CVD method Si
An O* film or a 5tsN+ film formed by a (S i H4+NHs ) gas-based plasma CVD method is used if water resistance or the like needs to be considered. 5is
In order to keep the hydrogen content in the Ni film low, (S
r H4+N2 ) A plasma CVD method in a gas system is used.

In order to increase the electrical withstand voltage of the 5iaN4 film formed by reducing the damage caused by the plasma CVD method and to reduce the leakage current, S 1 s N 4 by the photo-CVD method is used.
The membrane is excellent. There are two types of photo-CVD methods. (S i H4 + NH3 + 8g) A method of externally irradiating 2537 ultraviolet rays from a mercury lamp in a gas system, and (S i H4 + NH3 + 8g)
I H4+ N H) 18 of a mercury lamp in the a gas system
This is a method of irradiating UV rays with 49 liters of UV light. In both cases, the substrate temperature is about 150 to 350°C.

After forming contact holes through reactive ion etching in the polysilicon on the emitter 7 through the insulating films 305 and 306 through a mask alignment process and an etching process, AI, Al-5i, Al-Cu-
Deposit metal such as 5i. In this case, since the aspect ratio of the contact hole is large, deposition by CVD is superior. After patterning the metal wiring 8 shown in FIG. 1, a 5isN4 film or a PSG film 2 as a final passivation film is deposited by CVD (FIG. 18(g)).

In this case as well, the film produced by the photo-CVD method is superior. 12
is a metal electrode made of Al, Al-8i, etc. on the back surface.

The method for manufacturing the photoelectric conversion device of the present invention involves a wide variety of steps, and FIG. 18 shows only one example.

An important point of the photoelectric conversion device of the present invention is how to suppress the leakage current between p region 6 and n- region 5 and between p region 6 and n3 region 7 to a minimum.

It goes without saying that dark current can be reduced by improving the quality of n-region 5, but the problem lies in the interface between isolation region 4 and n-region 5, which is made of an oxide film or the like. In FIG. 18, for this purpose, a method has been described in which amorphous Si is deposited on the side wall of the isolation region 4 in advance and epitaxial growth is performed.

In this case, amorphous Si is made into a single crystal by solid phase growth from the Si substrate during epitaxial growth. Epitaxial growth is performed at a relatively high temperature of about 850°C to 1000°C. Therefore, microcrystals often begin to grow in the amorphous Si before the amorphous Si is made into a single crystal by solid-phase growth from the Si substrate, which causes poor crystallinity. At lower temperatures, the rate of solid-phase growth is relatively much higher than the rate at which microcrystals begin to grow in amorphous Si.
If amorphous Si is made into a single crystal by a low-temperature process of about 700° C., the characteristics of the interface will be improved. At this time, the board S
If there is a layer such as an oxide film between i and amorphous Si, the start of solid phase growth will be delayed, so an ultra-high cleanliness process is required so that such a layer is not included at the boundary between the two.

In addition to the above-mentioned furnace growth, for solid-phase growth of amorphous Si, it is also effective to keep the substrate at a certain temperature and use a rapid annealing technique using flash lamp heating or an infrared lamp for a period of several seconds to several tens of seconds. . When using these techniques, S i O2Jl
The SL deposited on the sidewalls may be polycrystalline. However, the polycrystalline SL needs to be deposited using a very clean process and do not contain oxygen, carbon, etc. in the grain boundaries of the polycrystalline material.

After the Si on the side of S i Ow is single crystallized,
Selective growth of SL will be carried out.

If leakage current at the interface between the S i O* isolation region 4 and the high resistance n-region 5 becomes a problem, the high resistance n-region 5
This problem of leakage current can be avoided by increasing the n-type impurity concentration only in the portion adjacent to the Sing isolation region 4. For example, n contacting the isolated S i Oz region 4
- The n-type impurity concentration is increased only in a region with a thickness of about 0.3 to 1 μm in region 5, for example, to about 1 to 10×I O18 cm. This structure can be formed relatively easily.Substrate 1 After forming a thermal oxide film of about 1 μm on top, it is deposited on top of it by CVD method. sio2m is first made into a SiOs film containing a predetermined amount of P to a required thickness. Sin on top.

Isolation region 4 is created by depositing by CVD method. In the subsequent high-temperature process, the phosphorus contained in the sandwiched form in the separation region 4 was removed, and the interface was found to have the highest impurity concentration. Create good impurity distribution.

In other words, the structure is as shown in FIG. 19. The isolation region 4 has a three-layer structure, where 308 is a thermal oxide film SiO*, and 309 is a 5-inch CVD film containing phosphorus.
s film, 301 is a CVD Sin film. Separation area 4
An n region 307 is formed adjacent to and between the n region 5 by diffusion from the SiO2 film 309 containing phosphorus.

307 is formed all around the cell. This structure increases the base-collector capacitance Cbc, but
Base-collector leakage current is drastically reduced.

In FIG. 18, an example was explained in which the isolation insulating region 4 is formed in advance and selective epitaxial growth is performed. U group separation technology (A, H
ayasakaet al, U-groove 1s
olation technique forhigh
5peed bipolar VLSI'S
“ ,Tech,Dig,ofIEDM,P,62
．． 1982. This can also be done using (see).

The photoelectric conversion device according to the present invention forms a bipolar transistor in which a base region, most of which is adjacent to the semiconductor wafer surface, is in a floating state in a region surrounded by an isolation region made of an insulator, This is a device that photoelectrically converts optical information by controlling the potential of a floating base region with an electrode provided on a part of the base region via a thin insulating layer. An emitter region made of a high impurity concentration region is provided in a part of the base region, and this emitter is connected to a MOS transistor operated by a horizontal scan pulse. The aforementioned electrode provided on a portion of the floating base region via a thin insulating layer is connected to a horizontal line. The collector provided inside the wafer may be composed of a substrate, or depending on the purpose, it may be composed of high-concentration impurity physical regions separated for each horizontal line on a high-resistance substrate of the opposite conductivity type. be. The pulse voltage applied when reading out a signal is substantially larger than the pulse voltage when refreshing the floating base region using the electrode provided through the insulating layer.

In fact, a pulse train that waits for two types of voltages may be used, or as explained in the double capacitor structure, the capacitance Cox of the readout MOS capacitor electrode may be made larger than the capacitance C08 of the refresh MOS capacitor electrode. You can stay there. By applying a refresh pulse, optically excited carriers are accumulated in the floating base region, which is brought into a reverse bias state, to store a signal based on an optical signal, and when reading out the signal, the base-emitter region is deeply biased in the forward direction. The feature is that the signal can be read out at high speed by applying a reading pulse voltage as shown in FIG. The photoelectric conversion device of the present invention may have any structure as long as it has these characteristics, and it is needless to say that it is not limited to the structure described in the above embodiments.

For example, the structure is similar even if the conductivity type is completely reversed from that described in the above embodiment. however,
At this time, it is necessary to completely reverse the polarity of the applied voltage. In a structure where the conductivity types are completely reversed, the region would be n-type. That is, the impurities constituting the base are As and P. When the surface of a region containing As and P is oxidized, As and P
piles up on the SL side of the S i /S i O* interface. That is, a strong drift electric field is generated inside the base from the surface to the inside, and the optically excited holes immediately escape from the base to the collector side, and electrons are efficiently accumulated in the base.

If the base is p-type, the commonly used impurity is boron. When the p-region surface containing boron is thermally oxidized, boron is incorporated into the oxide film, so S i / S i
The boron concentration in the Si near the Oa interface is slightly lower than the boron concentration inside.

This depth depends on the oxide film thickness, but is usually several hundred. A reverse drift electric field for electrons is generated near this interface, and electrons photoexcited in this region tend to be collected on the surface. If this continues, the region where this reverse drift electric field is generated will become a dead region, but since the photoelectric conversion device of the present invention has an n0 region along a part of the surface, the S i / of the p region SiO
*Electrons gathered at the interface flow into this n0 region before being recombined. Therefore, even if there is a region where, for example, boron has reduced S i /S i O near the interface and a reverse drift electric field occurs, it will hardly become a dead region. Rather, these areas
When present at the i/S i O* interface, the effect of holes disappearing at the interface is eliminated, and the base of the nine layers The hole accumulation effect is good, which is very desirable.

In addition to the above-mentioned solid-state imaging device, the photoelectric conversion device according to the present invention can be applied to, for example, an image input device, a facsimile,
Workstations, digital copying machines, image input devices such as word processors, OCR, barcode reading devices, cameras,
It can also be applied to photoelectric conversion object detection devices for autofocus of video cameras, 8mm cameras, etc.

As described above, the photoelectric conversion device of the present invention accumulates carriers excited by light in the base region, which is the control electrode region in a floating state. That is, Ba5e StoreImage 5ensor
This is a device that should be called ``BASIS'' for short.

The photoelectric conversion device of the present invention can be configured with one pixel using one transistor, so it is extremely easy to increase the density.At the same time, its structure reduces blooming and smearing, has high sensitivity, and has a wide dynamic range. Since it has an internal amplification function, it generates a large signal voltage regardless of wiring capacitance, so it has the characteristics of low recording and easy peripheral circuitry. For example, its industrial value as a future high-quality solid-state imaging device is extremely high.

[Effects of the Invention] According to the present invention, the potential of the main electrode region and the potential of the control electrode region are independently controlled to bias the junction between the control electrode region and the main electrode region in the forward direction to eliminate accumulated charges. Since the image disappears, afterimages and fixed pattern noise can be extremely reduced with high-speed operation.

Furthermore, no matter what amount of light is irradiated, afterimages, noise, and variations in output from cell to cell are hardly a problem, and even better high-speed refresh is possible.

[Brief explanation of drawings]

FIG. 1 shows an optical sensor cell according to an embodiment of the present invention, (
(a) is a sectional view, (b) is its equivalent circuit diagram, and (C) is a potential distribution diagram. FIG. 2 is a sectional view showing the main structure of another modification of the optical sensor cell. FIG. 3 is a circuit diagram of a configuration example of a photoelectric conversion device according to the present invention. 4 to 9 are diagrams for explaining the main structure and basic operation of the optical sensor cell according to the present invention. Fourth
The figure is an equivalent circuit diagram during a read operation, FIG. 5 is an equivalent circuit diagram during a refresh operation, FIG. 6(a) is a plan view, FIG. Figure 7 is a graph showing the relationship between readout time and readout voltage, Figure 8(a) is a graph showing the relationship between storage voltage and readout time, and Figure 8(b) is a graph showing the relationship between bias voltage and readout time. graph,
FIGS. 9(a') to 9(C) are graphs showing the relationship between refresh time and base potential. 10 to 12 are explanatory diagrams of the photoelectric conversion device of FIG. 3, and FIG. 10(a) is a pulse timing diagram,
FIG. 10(b) is a graph showing the potential distribution during each operation. Figure 11 is an equivalent circuit diagram related to the output signal, and Figure 12 is an equivalent circuit diagram related to the output signal.
The figure is a graph showing the output voltage from the moment of conduction in relation to time. 13, 14 and 15 are circuit diagrams showing other photoelectric conversion devices. FIG. 16 is a plan view for explaining the main structure of a modified example of the present invention. FIG. 17 is a circuit diagram of a photoelectric conversion device constituted by the optical sensor cell shown in FIG. 16. FIGS. 18 and 19 are cross-sectional views showing an example of a method for manufacturing a photoelectric conversion device of the present invention. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... PSG film, 3... Insulating oxide film, 4... Element isolation region, 5... N- region (
collector region), 6... p region (base region), 7.
7'...n region emitter region), 8... wiring,
9... Electrode, 10... Wiring, 11... n0 region,
12... Electrode, 13... Capacitor, 14... Bipolar transistor, 15.17... Junction capacitance, 1
6.18...Diode, 19.19'...Contact part, 20...Light, 28...Vertical line, 30
... Optical sensor cell, 31 ... Horizontal line, 32 ...
・Vertical shift register, 33.35...MOS transistor, 36.37...terminal, 38...vertical line, 39...horizontal shift register, 40...MOS transistor, 41...output line , 42...MOS
Transistor, 43...Terminal, 44...Transistor, 45...Load resistance, 46...Terminal, 47...
Terminal, 48...MOS) transistor, 49...terminal, 61, 62.63...section, 64...collector potential, 67...waveform, 80.81...capacitance, 82.8
3...Resistance, 84...Current source, 100°101.1
02...Horizontal shift register, 111°112...
Output line, 138...Vertical line, 140...M
OS transistor, 148...MO3I-transistor, 150, 150'...MOS capacitor, 152
．． 152'... Optical sensor cell, 202°203.2
05... Base potential, 220... Buried p0 region, 2
22, 225... Wiring, 251... p'' region, 25
2...n'' region, 253... Wiring, 300... Amorphous silicon, 302... Nitride film, 303...
・PSG film, 304... Polysilicon, 305...
PSG film, 306... interlayer insulating film.

Claims (2)

[Claims] (1) It has a control electrode region made of a semiconductor of a first conductivity type, and first and second main electrode regions made of a semiconductor of a second conductivity type different from the first conductivity type, and the first main electrode region is electrically connected to a first reference voltage source and the carriers are accumulated in the control electrode region; A photoelectric conversion device comprising: a first switch means for removing the control electrode region; and a second switch means for electrically connecting the control electrode region to a second reference voltage source. (2) The voltage applied to the control electrode region using the second reference voltage as a power source is higher than the voltage applied to the first main electrode region using the first reference voltage source as a power source. A photoelectric conversion device according to claim 1.