JPH0340687A - Moving vector detector - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a motion vector detection device that detects motion vectors at high speed in motion compensation for highly efficient encoding of image signals.

Conventional technology Image data has a large amount of information, which increases the cost of transmission lines in image transmission. Therefore, as a method for reducing the information amount of an image signal, there are techniques such as motion compensated interframe coding and motion interpolation in which thinned frames are interpolated using a motion vector. To achieve these goals, devices have been developed that detect motion vectors at high speed.

FIG. 2 is a block diagram of a conventional motion vector detection device. In FIG. 2, 201 is a signal input terminal, 202
is an address counter, 203 is a count up circuit, 2
04 is the first count latch, 205 is the first adder, 20
6 is the second power 11 calculator, 20'7 is the frame memory, 20
8 is a distortion calculation circuit, 209 is a minimum distortion detection circuit, 210 is a second count launch, 211 is an address launch, and 212 is a signal output terminal.

The operation will be explained below using FIG. 2. When a signal obtained by dividing an l frame of an image signal into a plurality of blocks is input to the signal input terminal 201, the address counter 202 adds an address value corresponding to the input signal to the second adder 20.
Output to 6. The count up circuit 203 counts up 3 times in the horizontal direction and in the vertical direction by 4 counts, then similarly counts up 3 times in each direction by 2 counts, and then counts up 3 times in each direction by 1 count. are performed and output to the first adder 205 as count-up values.

The first count latch 204 outputs a predetermined first count launch (direct) when a signal is input to the signal input terminal 201, and captures the second count launch value from the second count launch 210. The first adder 2 uses the second count latch value as the first count launch value.
Output to 05. The first adder 205 adds the count up value from the count up circuit 203 and the first count latch value from the first count latch 204, and sends the result to the second adder 206 and the second count latch 210 as a count address value. Output. The second adder 206 adds the count address value from the first adder 205 and the address value from the address counter 202 and outputs the result to the frame memory 207 and address latch 211 as an absolute address value. The frame memory 207 includes the second adder 206
The image signal corresponding to the absolute address value from the distortion calculation circuit 2
Output on 08. The distortion calculation circuit 208 has a signal input terminal 2
The absolute value of the difference for each pixel value between the input signal from 01 and the image signal from the frame memory 207 is calculated, and the sum thereof is determined. The minimum distortion detection circuit 209 sequentially compares the sums and outputs a minimum distortion recognition signal to the second count latch 210 and address latch 211 when the minimum distortion is given. When the second count latch 210 receives the minimum distortion recognition signal from the minimum distortion detection circuit 209, it reads the count address value from the first adder 205, and the count address value becomes equal to a predetermined count number. The count address value read when the count address value is reached is outputted to the first count launch 204 as the second count latch value.

When the minimum distortion recognition signal from the minimum distortion detection circuit 209 is input, the address la edge 211 reads the absolute address value from the second adder 206, and when the absolute address value is sent 27 times, it is read. The absolute address value is outputted to the signal output terminal 212 as a motion vector.

(For example, Chapter 5 of High-Efficiency Coding Technology in Single-Image Transmission, published by Trikebbs) Problems to be Solved by the Invention However, in the above method, the initial motion vector is incorrectly determined because the entire motion vector search range is not searched. Once detected, the true motion vector cannot be reached. Furthermore, there is a need for a motion vector detection device with even higher speed.

In view of the above-mentioned problems, the present invention aims to speed up the processing by reducing distortion calculation processing by roughly searching the entire motion vector search range using comparison calculations that merely compare the magnitudes of pixel values.

Above are the means to solve the problem! In order to solve one problem, the motion vector detection device of the present invention calculates from the at1/s value corresponding to the input signal each time an input signal in which one frame of the image signal is already divided into a plurality of blocks is added. a first address counter that outputs address values that are sequentially counted up; a frame memory that stores the previous frame and outputs an image signal according to the address value from the first address counter; a comparison calculation circuit that compares the input signals each time an image signal is sent, calculates the sum of values according to the comparison, and outputs the comparison sum; and a comparison sum from the comparison calculation circuit that determines in advance. a comparison minimum detection circuit which sequentially compares the comparison sum with the comparison sum obtained and outputs a comparison approximation recognition signal when the most approximate comparison sum is given; a first address latch that outputs the read address value as an address latch value when the read address value becomes equal to a predetermined count number; and the first address latch outputs the address latch value. Then, a second address counter sequentially outputs predetermined count values, and a signal obtained by adding the address latch value output from the first address latch and the counter value output from the second address counter is used as an address. an adder that outputs a counter value; and the frame 1. When the memory outputs an image signal corresponding to the address counter value from the adder, a distortion calculation circuit calculates the absolute value of the difference/min for each pixel of the input signal in the current frame and calculates the total distortion; A minimum distortion detection circuit that sequentially compares the total distortion and outputs a minimum distortion recognition signal when the minimum distortion is given; and when the minimum distortion recognition signal is input, an address counter value from the adder is read, and the address counter value is determined in advance. The second address latch outputs the read address counter value as a motion vector when the predetermined count number has been counted up.

According to the above-described configuration, the present invention performs a rough search within the motion hector search range by performing a comparison operation that merely compares the size during block matching, detects a temporary motion vector, and then performs distortion calculation for each pixel. By doing this, it is possible to detect the true motion vector, thereby reducing distortion calculation processing and increasing speed.

Embodiment Hereinafter, a motion vector detection apparatus according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a motion vector detection device of the present invention. In FIG. 1, 101 is a signal input terminal, 102 is a first address counter, 103 is a frame memory, 104 is a comparison calculation circuit, 105 is a comparison minimum detection circuit, 106 is a first address launch, and 107 is a second address counter.
108 is an adder, 109 is a distortion calculation circuit, 110 is a minimum distortion detection circuit, 111 is a second address latch, and 112 is a motion vector output terminal.

The operation of the motion vector detection device configured as described above will be explained below with reference to FIG.

The signal S input from the signal input terminal 101 is divided into blocks with a block size of 3×3 as shown below.

When the input signal S is sent to the comparison calculation circuit 104, the first address counter 102 counts up the address values that are sequentially counted up from the address value corresponding to the input signal S by 1.
Send it out six times. Every time the frame memory 103 reads the address value, it sequentially sends the following signals from A1 to A to the comparison calculation circuit 104 regarding the signals arranged as shown in FIG. 3 of the previous frame.

The signal A1 N=1.2.3... is sent to the comparison calculation circuit 104.
..., 16) is sent, it is replaced with signal B as shown below.

Therefore, a comparison sum is obtained for each pixel using the signal B and the signal S from the signal input terminal 101 as follows.

The obtained comparison total C is sent to the comparison minimum detection circuit 105. The comparison minimum detection circuit 105 calculates the comparison sum C using the same signal S.
If a value closer to 0 than before is sent,
The comparison total C is read and the first address latch 106
It sends a comparative approximation recognition signal to , and does nothing else. The first address launch 106 reads the address value from the first address counter 102 when the comparison approximation recognition signal is sent, and when the address value becomes equal to a predetermined count number, the read address ( tl!(3,3) is sent to the adder lO8 as an address latch value. When the address latch value is sent to the adder 10, the second address counter 107 outputs nine types of predetermined count values. Adder 108
adds the address latch value sent from the first address latch 106 and the count value sequentially sent from the second address counter 107 and sends the result as an address counter value. The frame memory 103 includes an adder 10B
Every time the address counter value sent from the address counter is read, the following signals from A, 1 to A, 1 are output to the distortion calculation circuit 109 in order.

The signal A is input to the distortion calculation circuit 109. (i=1 3゜ 9〉 is sent, Signal B as below to replace.

Then signal B and, From signal input terminal 101 Determine the distortion d using the signal S.

The determined distortion d is sent to the minimum distortion detection circuit 110.

The minimum distortion detection circuit 110 reads the distortion d when a distortion d smaller than the previous one is sent with the same signal S, and sends a minimum distortion recognition signal to the second address lamination 111, and otherwise do nothing. The second address latch 111 reads the address counter value from the adder 108 when the minimum distortion recognition signal is sent, and when the address counter (direction) becomes equal to a predetermined count number, the second address latch 111 reads the address counter value from the adder 108. The counter value is sent as a motion vector to the motion vector output terminal 112.To simplify the explanation, the signal input from the signal input terminal 101 is divided into 3×3 blocks.
When the comparison operation circuit 104 performs a comparison, O is inserted in advance into the comparison minimum detection circuit 105, so that +1 is assumed when the value is greater than the input signal, O1 is assumed when the value is equal, and -■ is assumed when the value is smaller. Furthermore, the first address counter 102 sends out the address value 16 times, and the second address counter 102 sends out the address value 16 times.
07 outputs nine types of counter values, but the invention is not limited to this.

Effects of the Invention As described above, the present invention does not calculate distortion for each pixel from the beginning during block matching, but searches only by comparing magnitudes, so that the vector search range can be quickly narrowed down. Then, by performing distortion calculations for each pixel, motion vectors can be detected accurately.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the bottom of a motion vector detection device according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a conventional motion vector detection device, and the third section is for explaining the embodiment. FIG. 102...First address counter, 103...
... Frame memory, i04 ... Comparison calculation circuit, 105 ... Comparison minimum detection circuit, 106.
...First address latch, 107...Second address counter, 108...Adder, 10
9...Distortion calculation circuit, 110...Minimum distortion detection circuit, 111...Second address latch, 1
12...Motion vector output terminal, 202...
... Address counter, 203 ... Count up circuit, 204 ... First count launch,
205...First adder, 206...Second adder, 207...Frame memory, 20th...Distortion calculation circuit, 209... ...Minimum distortion detection circuit, 210...Second count launch, 21
1...Address latch.

Claims (1)

[Claims] a first address counter that outputs an address value that is sequentially counted up from an address value corresponding to the input signal each time an input signal in which one frame of the image signal is already divided into a plurality of blocks is added; a frame memory that stores an image signal corresponding to the address value from the first address counter, and compares the image signal with the input signal every time the image signal from the frame memory is sent; A comparison calculation circuit that calculates the sum of values according to the value of When the comparison minimum detection circuit outputs a recognition signal and the comparison approximate recognition signal is input, the address value from the first address counter is read, and when the address value becomes equal to a predetermined count number, a first address latch that outputs a read address value as an address latch value; and a second address counter that sequentially outputs a predetermined count value when the first address latch outputs the address latch value. , an adder that outputs a signal obtained by adding the address latch value outputted from the first address latch and the counter value outputted from the second address counter as an address counter value; and the frame memory includes an address counter output from the adder. When an image signal corresponding to the value is output, a distortion calculation circuit calculates the absolute value of the difference for each pixel of the input signal in the current frame and obtains the total distortion, and a distortion calculation circuit that sequentially compares the distortion total and gives the minimum distortion. a minimum distortion detection circuit that outputs a minimum distortion recognition signal; when the minimum distortion recognition signal is input, an address counter value from the adder is read; and when the address counter value has counted up a predetermined count number; A motion vector detection device comprising: a second address latch that outputs a read address counter value as a motion vector.