JPH0340967B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a differential amplifier, and sometimes a field effect transistor (hereinafter referred to as a field effect transistor).
This relates to a differential amplifier that uses a FET (simply referred to as FET) as an input means.

[Background of the Invention] Improvements in the performance of semiconductor circuits continue to progress year by year. Operational amplifiers and comparators are commonly used circuits, and it goes without saying that there is a strong desire to improve the performance of these types of circuits. Since operational amplifiers and comparators require high input impedance, differential amplifiers using FETs as input means are often used in input circuits. In this case, since the performance of the differential amplifier directly affects the input characteristics of the operational amplifier, ie, the input offset voltage and frequency characteristics, improvements are increasingly desired.

FIG. 1 shows an example of a circuit of a conventional differential amplifier applied to an operational amplifier or the like. In this figure, the differential amplifier can be roughly rewritten as shown in FIG.
Here, Q ₁ and Q ₂ are differential amplifiers using FETs,
Q ₃ and Q ₄ are active transistors as FET load means.
In the load circuit, Q ₅ is a voltage amplifier, and Q ₆ and Q ₇ are output amplifiers.

In such a configuration, the input offset voltage is determined by the FET differential amplifier circuit. That is, if N stages of amplifiers are connected in cascade, the input offset voltages of each stage are set to V ₀₁ , V ₀₂ , ...V _ON in order from the input side, and the voltage gains are set to A ₁ , A ₂ , ...A _N , the overall The offset voltage V ₀ of is V ₀ =V ₀₁ +V ₀₂ /A ₁ +V ₀₃ /A ₁・
It will be expressed as A ₂ ... Here, if the gain at each stage, especially the gain at the first stage, is sufficiently high,
V ₀ ≈V ₀₁ , and if V ₀₁ is smaller, V ₀ , that is, the input offset voltage of the entire circuit, can be made smaller. Therefore, it is desirable that the FET input differential amplifier circuit used in the first stage has a small input offset voltage and a high gain.

In the circuit shown in Figure 2, a monolithic FET is used in the FET differential amplifier circuit to reduce the offset voltage, and an active load using a current mirror, that is, a high impedance load, is used to obtain high gain. ing.

In order to increase the speed of operational amplifiers and the like, it is necessary that the frequency characteristics of the first stage amplifier be good. Generally, the corner frequency of the cascaded amplifiers, ie, the frequency at which the frequency characteristic becomes -3 dB, is determined by the amplifier with the worst frequency characteristic among the amplifiers used in each stage. Therefore, in order to increase the speed of operational amplifiers and the like, it is first necessary that the frequency characteristics of the FET input differential amplifier used in the input stage be good. Furthermore, when used with negative feedback such as an operational amplifier, oscillation occurs when the phase rotation of the amplifier reaches 180 degrees within a frequency band where the loop gain in the negative feedback path is 1 or more. For this reason, it is not preferable that the corner frequencies, ie, the poles, of the amplifiers that are cascade-connected in multiple stages to constitute an operational amplifier are in a frequency relationship that is close to each other, but it is preferable that they be far apart from each other.

In the circuit shown in Figure 2, the transistor
_Q5 becomes the amplifier that generates the main part of the gain of an operational amplifier, etc. Generally, the corner frequencies of other amplifiers are designed to be much higher than this corner frequency to eliminate the possibility of oscillation. The frequency characteristics of the circuit shown in Figure 1 are as shown in Figure 3, and the characteristics above the corner frequency are approximately -6 dB/
oct, it can be seen that the corner frequency is determined by one voltage amplifier. For the above reasons as well, the frequency characteristics of the FET input differential amplifier need to be good.

In the FET differential amplifier shown in Figure 2, methods for improving the corner frequency include the so-called improvement method using elements, which uses FETs with good frequency characteristics, and the so-called circuit improvement method, which reduces the load resistance. Examples include the above method. FET
The upper operating frequency of can be evaluated using the input capacitance Ciss and mutual conductance gm using the time constant of Ciss/gm as an index, and using an element with a small index is a way to improve the characteristics of the former element. . On the other hand, in the latter circuit improvement method, a time constant R _L ·Coss is formed by the load impedance R _L and the output capacitance Coss of the FET, and this operates as a low-pass filter. Therefore, by reducing the load impedance R _L , the corner frequency can be increased to the characteristic limit of the FET element. To achieve this, the relationship between the input and output time constants should be R _L・Coss≦Ciss/gm, but since the input and output capacitances of FETs are generally about the same, this condition is _L ≦1. Here, since the voltage gain A _V of the FET amplifier is A _V = gm・R _L , A _V
≦1, and if the frequency characteristics are to be made the best, the voltage gain will be about 1 or less, that is, it will be in an attenuated state. Note that the input capacitance of the circuit is
It is known that the gate-drain capacitance Cgs of the FET is amplified by the voltage gain A _V times due to the Miller effect and is added as A _V Cgs.
When the voltage gain A _V is 1 or more, the above-mentioned Ciss increases and the operating speed of the circuit further deteriorates. Incidentally, the Miller effect is a phenomenon observed in an amplifier where signals between input and output terminals have opposite polarities.

As described above, according to the prior art, in order to realize an operational amplifier with good characteristics, that is, an operational amplifier with low input offset voltage and good frequency characteristics, it is necessary to have high gain and good frequency characteristics.
A differential amplifier with FET input is required. However, in order to improve the gain, it is necessary to increase the load impedance, but in order to improve the frequency characteristics, it is necessary to decrease it, and these two requirements are contradictory.

One way to simultaneously improve both of these problems is to increase the mutual conductance gm of the FET used in the differential amplifier, but due to the nature of semiconductors, this means that the input and output capacitance of the FET increases. Ultimately, this results in a decrease in input impedance, making it unsuitable for operational amplifiers and the like that require high input impedance.

Therefore, aiming for high input impedance,
According to the conventional technology of the FET input differential amplifier mentioned above,
2. High gain and high corner frequency.
The problem is that it is not possible to satisfy two characteristics at the same time.

[Object of the Invention] An object of the present invention is to provide a differential amplifier that has high gain and frequency characteristics, and also has high input impedance.

[Summary of the Invention] In order to achieve the above object, a pair of bipolar transistors are combined in a predetermined manner with a pair of FETs each having a gate electrode supplied with an input signal. That is, more specifically,
The source electrodes of the pair of FETs control the base electrodes of the bipolar transistors via resistors, and the drain electrodes of the FETs and the collector electrodes of the bipolar transistors are cross-connected. With this kind of circuit configuration, a differential amplifier with high input impedance and high voltage gain or operating speed can be realized by combining FETs and bipolar transistors, and mirroring can be realized by cross-connecting. This can prevent an increase in input capacitance due to this effect and, therefore, a decrease in operating speed.

[Embodiment of the Invention] An embodiment of the present invention will be described above with reference to the drawings.

FIG. 4 shows an example of a circuit in which the differential amplifier according to the present invention is applied to a comparator.
As shown, this circuit attempts to realize a high-speed comparator with high input impedance by providing a FET input preamplifier (indicated by a dashed line in the figure) to a bipolar transistor comparator.

That is, the power supply +Vcc has resistors 9 and 10, respectively.
The drain electrodes of FETQ ₁ and Q ₂ are connected through the transistor, and the collector electrodes of bipolar transistors Q ₃ and Q ₄ are also connected. The source electrodes of these FETQ ₁ and Q ₂ are bipolar transistors, respectively.
connected to the base electrodes of Q ₃ and Q ₄ , and resistors 5,
6, it is connected to a constant current source 7 as a bias means for commonly supplying current to the two FETs. In addition, the emitter electrodes of bipolar transistors Q ₃ and Q ₄ are connected to each other, and a constant current source 8 is connected as a bias circuit to provide a common current.
connected to. Bipolar transistor Q ₃ ,
A resistor is connected to each collector electrode of _Q4 as a load means. Further, the drain electrodes of FETQ ₁ and Q ₂ and the collector electrodes of bipolar transistors Q ₃ and Q ₄ are connected in a staggered manner. In such a configuration, the gate electrode of each of FETQ ₁ and Q ₂ becomes an input terminal to which an input signal is applied, and the drain electrode of each of FETQ ₁ and Q ₂ becomes an output terminal. In cross-connection, the output signal of bipolar transistor Q ₄ is connected to FETQ ₁
A signal that is in phase with the signal of the connected input terminal,
That is, the signals have the same polarity. Therefore, the aforementioned Miller effect is eliminated, and a situation such as a deterioration in circuit operating speed due to an increase in input capacitance does not occur. In other words, even if the voltage gain A _V is 1 or more, deterioration in operating speed can be prevented. In addition, in this example, FETQ ₁ , Q ₂ pair,
Although a constant current source was used in both cases as a bias circuit that commonly supplies current to each pair of bipolar transistors _Q 3 and Q ₄ , it is possible to use a pair of FETs Q ₁ and Q ₂ or a pair of bipolar transistors Q ₃ and Q ₄ . Other circuits can be used without particular limitation as long as they can supply current for sufficient operation.

The output of the differential amplifier indicated by a dash-dotted line, i.e.
The drain electrodes of FETQ ₁ and Q ₂ are connected to the input of IC comparator 11, for example. Thus, the output of the IC comparator 11 is guided to the output terminal via a level shift circuit for an output interface constituted by transistors Q ₅ and Q ₆ .

If the frequency characteristics of a differential amplifier configured in this way are optimized, the corner frequency will be approximately
At 160 MHz, the voltage gain was approximately twice that, or +6 dB, and compared to the conventional circuit, the gain could be increased to 6.4 times with almost no reduction in the corner frequency. Note that both FET and bipolar transistor are monolithic dual transistors.
using the device.

The frequency characteristics of both circuits are shown in FIG. In this figure, the characteristic according to this embodiment is indicated by a, and the characteristic according to the conventional technique is indicated by b. By using the FET input differential amplifier according to this embodiment, first, the input offset voltage of the entire comparator circuit could be reduced to about 1/2. This is due to the improved voltage gain.
This is because the influence of the subsequent circuit has disappeared.

Next, the overdrive characteristics of the entire comparator circuit could be improved as shown in FIG. In this figure, a shows the characteristics according to this embodiment, and b shows the characteristics according to the prior art. That is, this characteristic means that the inflection part is steeper, the horizontal part on the right side is horizontal, and the vertical part on the left side is closer to vertical, the better, and a high-speed voltage comparison operation of the input waveform is possible. As shown in figure a, by using the circuit of this embodiment, the characteristics of the comparator can be improved. This is because the gain has improved with almost no decrease in the corner frequency of the input section.
That is, this is due to an increase in the gain-bandwidth product.

The FET input differential amplifier according to this embodiment is
A resistor is inserted into the source electrode of the FET pair, a voltage is supplied from the source electrode to the bipolar transistor pair, and the drain and collector are connected in common to form one differential amplifier. Since the voltage gain of the source output of this FET is close to 1, a voltage approximately equal to the input signal voltage is input to the bipolar transistor pair. The voltage amplification factor of the transistor is FET
, the gain of this circuit is high.
Since a FET is used for the input, the input impedance is large. As shown in FIG. 7, this input/output characteristic is the sum of the characteristics of the bipolar transistor and FET. In a conventional circuit using only FETs, the voltage gain A _V is A _V = gm・R _L ;
In the circuit according to this embodiment, considering the input impedance of the bipolar transistor, A _V =gm·R _L {1+hfe/(1 +0.026hfe·gm/I _E )}. where I _E is the emitter current of the two bipolar transistors. Here, 0.026hfe・
Since it is easy to make the term gm/I _E smaller than hfe, the gain of the circuit increases by that amount.
In this case, since the collector output capacitance of the bipolar transistor is small, the capacitance connected to the load resistor to form a low-pass filter is determined only by the FET, and it is not possible to use the same value as the load resistor when using only the FET. can. Therefore, regarding the gain, the above considerations can be realized and a high corner frequency can be maintained.

Note that the circuit according to this embodiment has properties suitable for a comparator, and the voltage applied to the input terminal can be tolerated up to the withstand voltage of the FET, and like a bipolar transistor differential amplifier, the voltage applied to the input terminal can be applied to the base-emitter reverse withstand voltage of 3. It is not limited to ~6V. This is due to the fact that the FETs are operated differentially through resistors. In addition, if you want to achieve improved limiter characteristics with the circuit according to this example, use the FET
Connect the drain of the bipolar
Output can be taken out only from the collector of the transistor. In this case, the input/output characteristics become hard clips. Furthermore, in this case, since the collector capacitance of the transistor is small, the load resistance value can be increased to obtain the same corner frequency, and the voltage gain can be further increased.

By the way, in the above embodiment, the main focus is placed on the conditions where the frequency characteristics are most improved, but it is also possible to focus on the conditions for obtaining a high gain and approach the improvement of the frequency characteristics. Of course. Additionally, in some cases, FETs can be replaced with bipolar transistors.
When replacing in this way, high input impedance cannot be expected, but high-speed operation and high voltage gain can be expected.

[Effect of the invention] As explained above, according to the present invention,
A differential amplifier with high gain and frequency characteristics as well as high input impedance can be obtained.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram showing an application example of a differential amplifier according to the prior art, Fig. 2 is a circuit diagram showing the main parts for explaining the operating principle of the circuit, and Fig. 3 is a circuit diagram showing an example of application of a differential amplifier according to the prior art. FIG. 4 is a circuit diagram showing an application example of the differential amplifier according to the present invention, and FIG. 5 is a diagram showing the frequency characteristics of the differential amplifier according to the present invention and that of the prior art. FIG. 6 is a diagram showing the overdrive characteristics of a comparator including the differential amplifier according to the present invention, and FIG. 7 is a diagram showing the input/output characteristics of the differential amplifier according to the present invention. . Q ₁ , Q ₂ ... FET, Q ₃ , Q ₄ ... Bipolar transistor.

Claims (1)

[Claims] 1 A differential amplifier including a pair of FETs, and has two input terminals, a first and a second input terminal.The first input terminal is connected to the gate electrode of the first FET, and the second input terminal is connected to the gate electrode of the first FET. A first bias circuit is connected to the gate electrodes of the FETs, and the source electrodes of the first and second FETs are connected to each other to commonly supply current to the source electrodes through a resistor for generating a differential signal voltage. and the source electrode of the first FET is connected to the base electrode of the first bipolar transistor that amplifies the signal, and the source electrode of the second FET is connected to the base electrode of the second bipolar transistor that amplifies the signal. The first bipolar
The collector electrode of the transistor is connected to the drain electrode of the second FET, the collector electrode of the second bipolar transistor is connected to the drain electrode of the first FET, and the emitter electrodes of the first and second bipolar transistors are connected to the drain electrode of the second FET. The two bipolar transistors are connected to each other and are also connected to a second bias circuit that commonly supplies current to the emitter electrodes, and for generating a signal voltage to the collector electrode of at least one of the first and second bipolar transistors. A differential amplifier characterized by a configuration in which a load means is connected to the collector electrode and an output signal is taken out from the collector electrode.