JPH0341694A - Word line drive circuit - Google Patents

Abstract

PURPOSE:To boost a drive potential sufficiently and to prevent destruction of a storage data by providing a boosting capacitor between a gate and a source of a P-channel MOS transistor (TR) and a MOS TR turned on/off in a prescribed timing between the gate of the P-channel MOS TR and an output gate of a row decoder. CONSTITUTION:Boosting capacitors 55-1b, 55-2b are provided between the gate and source of P-channel MOS TRs 55-1a, 55-2a and a MOS TRs 55-1d, 55-2d turned on/off in a prescribed timing are provided between the gate of the P- channel MOS TRs 55-1a, 55-2a and the output of a row decoder 56. Thus, the boosting capacitors 55-1b, 55-2b boost the gate level of the PMOS when a drive potential is increased to a prescribed high level and the MOS TR acts like to keep the gate charge of the boosted PMOS. Thus, the PMOS in the non- selection word line drive circuit is not turned on to prevent destruction of a storage data.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides complementary MO8? -Ran resistor (hereinafter referred to as CMO
The present invention relates to a word line drive circuit in a semiconductor memory device such as a dynamic RAM (random access memory) having a configuration (referred to as 8).

(Prior Art) Conventionally, such fields include the following, for example. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram of a conventional l-transistor type dynamic memory cell.

This dynamic memory cell 1 is an N-channel type MOS
It is composed of a transistor (hereinafter referred to as NMO8) 1a and a capacitor 2b. The gate of the NMO 3la is connected to the word line 2-1, the drain to the bit line 3-1, and the source to the fixed potential CP via the capacitor Lb.

Next, the operation will be explained.

This memory cell 1. is “1” “OI” on capacitor 1b.
In order to store the information of I as 41HII level and "L°" level charges, it is desirable that the amount of charge is as large as possible.Here, when writing information "1°" to memory cell 1, word line 2- 1 becomes "H level," NM
O81a turns on. Next, the bit line 3-1 selected by the column decoder (not shown) becomes H" level. At this time, the "H" level is transmitted to the capacitor lb via the NMO 8la, and the parasitic capacitance of the bit line 3-1 increases. The charge is redistributed between the capacitor 1b and the NMO
The source potential of 81a rises. Therefore, the gate-source potential difference VGS is the threshold voltage VT of NMO3.
N (approximately 0.7 V), the NMO 31a will be turned off. Therefore, in order to transfer sufficient charge from the bit line 3-1 to the capacitor 1b, the potential of the word line 2-1 must be It is necessary to make the potential higher than the Hp+ level of the line 3-1 by the threshold voltage VTN.

Therefore, in order to increase the potential of the word line, a dynamic RAM using a word line drive circuit as shown in FIG. 3 has been proposed.

FIG. 3 shows a conventional dynamic RAM configured using the one-transistor type dynamic memory cell l shown in FIG.
FIG. 2 is a schematic block diagram of the configuration of FIG.

This dynamic RAM has multiple word lines 2-1.2.
-2... and a plurality of bit line pairs 3-1.3-2... selected by a column decoder (not shown), and these word lines 2-1.2-2. . . . A memory cell is connected to each intersection of the song and the bit line 3-1, 3-2, and the song. Word line 2-1
．． 2-2... are connected to the row decoder 5, and a sense amplifier 6 is connected to one end of the bit lines 3-1, 3-2... Furthermore, word line 2-1.
2-2... and the row selection signal S1. which is the output of the row decoder 5. A word line drive circuit group 7 is connected between S2, . . .

The word line drive circuit group 7 includes word lines 2-1, 2-2...
Word line drive port #17-1゜7 provided for each...
-2..., for example, the word line drive circuit 7
~1 is a P-channel MOS transistor (hereinafter referred to as P) connected in series between the drive potential vpw and the ground potential vSS
It is composed of MO8>7-1a and NMO87-1b. Similarly, word line drive port #I7-2...
... has PMO87-2a... song and NMO87-2b
. . . are each configured similarly to the drive port 87-1. Note that the drive potential Vpw is equal to the power supply potential VCC.
Therefore, the threshold voltage Vt of NMO 81a in FIG.
This is a potential that has been boosted to a level higher than that required.

Next, the operation will be explained.

For example, when writing information “1°” to memory cell 1,
Row selection signal St which is the output of row decoder 5.

When one of S2..., for example, the row selection signal SL, is selected, the row selection signal S1 becomes the "Lll level. As a result, the PMO 87-1a is turned on, and the NMO 87-1a is turned on.
1b turns off. Then, word line 2-1 becomes PMO8
7-1a to the same potential as the drive potential vpw,
“°H°° level, and NMO91 in memory cell 1
a turns on. Furthermore, the bit line 3-1 selected by a column decoder (not shown) goes to "H" level. At this time, the "H" level is transmitted to the capacitor 1b via the NMO 81a, and the parasitic capacitance of the bit line 3-1 and the capacitor 1
Charge redistribution occurs between the In this way, information "111" is written into the memory cell 1.

In addition, the unselected row selection signal S2 maintains the "HIT level" and the NMO 87-2b continues to be turned on, so the word line 2-2 is at the "L" level, and the capacitor 1b and the bit line 3-2 are electrically connected. are not connected, and no charge redistribution occurs.

(Problems to be Solved by the Invention) However, the word line drive circuit having the above configuration has the following problems.

When the row selection signal S2 in the non-selected state maintains the ``゛H'°H'° level potential VCC>, the drive potential vpw is boosted, and the gate-source potential VGS of PMO3?-2a is When the threshold voltage VTR (approximately 0.8v) is exceeded, PMO87-2a turns on.
Drive potential VPW leaks to ground potential VSS through O87-2a and NMO87-2b. therefore,
The drive potential vpw is set from the power supply potential VCC to PMO37-2a.
It is not possible to boost the voltage above the threshold voltage. This poses a problem in that the word line cannot be maintained at a high potential and sufficient charge cannot be transmitted from the bit line 3-1 to the capacitor 1b in the memory cell 1.

Furthermore, since a current flows from the PMO 87-2a to the NMO 37-'2b, the potential of the unselected word line 2-2 increases. As a result, there was a possibility that the N-MO 81a in the memory cell 1 connected to the word line 2-2 would be turned on, and the stored data would be destroyed.

The present invention provides a word line drive circuit that solves the problems of the prior art, such as the inability to sufficiently boost the drive potential and the destruction of data stored in memory cells.

(Means for Solving the Problem) A P-channel MoS transistor whose on/off control is controlled by the output of a row decoder for address decoding, and whose source is connected to a drive potential and whose drain is connected to a word line,
Word line driving in a semiconductor memory device having a complementary MOS transistor configuration, which is controlled on/off by the output of the row decoder, and includes an N-channel MOS transistor whose drain is connected to the word line and whose source is connected to a constant potential. The following measures were taken in the circuit.

A boosting capacitor is connected between the gate and source of the P-channel MOS transistor, and is connected between the output side of the row decoder and the gate of the P-channel MOS transistor, and is turned on and off at a predetermined timing. MOS transistors are provided.

<Function> According to the present invention, since the word line drive circuit is configured as described above, the boosting capacitor boosts the gate potential of the PMO 8 when the drive potential is increased to a predetermined high potential,
The MOS transistor functions to hold the boosted gate charge of PMO8. This prevents the PMO 8 in unselected word line drive circuits from being turned on.

Therefore, the above problem can be solved.

(Embodiment) FIG. 1 is a schematic block diagram of a dynamic RAM using a word line drive circuit according to an embodiment of the present invention.

This dynamic RAM includes memory cells 50 for storing data. The memory cell 50 includes a plurality of word lines 51-1, 51-2... and a plurality of bit lines 5.
2-1, 52-2..., and their word lines 51-1... and bit lines 52-1...
A memory cell 53 is connected to each intersection.

For example, a one-transistor type memory cell 53 includes an NMO 853a for data transfer and a capacitor 53 for data retention.
b, and the gate of the NMO 353a is connected to the word line 5.
1-4..., the drain is connected to the bit line 52-■.
. . . and the source are respectively connected to a fixed potential vcp (for example, power supply potential VCC/2) via a capacitor 53b. A sense amplifier 54 is connected to the bit lines 52-1..., and the word lines 51-1...
. . are connected to a word line drive circuit group 55 that boosts the word lines 51-1 . . . to a predetermined potential.

The word line drive circuit group 55 includes a plurality of word line drive circuits 55-1, 55-2, . . . having a CMO8 configuration. For example, the word line drive circuit 55-1 includes a PMO855-1a whose drain is connected to the word line 51-1.
The source of the PMO 855-1a is at the driving potential V
PW, and a boosting capacitor 551b is connected between its source and gate. Furthermore, PMO3
The drain of NMO 855-1c is connected to the drain of 55-1a, and the source of NMO 855-1,c is connected to ground potential VSS. Furthermore, PMO35
The gate of NMO 5-1a is connected to node Nl via NMO 855-1d, and the node Nl is connected to the gate of NMO 855-1c and row selection signal 856-1. Then, the row selection signal 556-1 is sent to the row decoder 56.
It is connected to the. The row decoder 56 decodes the row address and outputs a plurality of row selection signals 556-1, 56-2...
Similarly, the word line drive circuit 55-2 has a PMO 855-2a whose drain is connected to the word line 51-2; The source of 2a is connected to the drive potential ■PW, and a boosting capacitor 5 is connected between the source and gate.
5-2b is connected. Furthermore, PMO855-2
The drain of NMO855-2c is connected to the train a, and the source of NMO855-2c is connected to the ground potential V.
Connected to SS. Moreover, the gate of PMOS55-2a is connected to node N2 via NMO855-2d,
The node N2 is connected to the gate of NMO 855-2c and row selection signal 556-2, respectively. moreover,
A row select signal 856-2 is connected to row decoder 56.

In this way, a plurality of word line drive circuits 55-1゜55-2
. . . is each row selection signal 556-1.356-2
...and each word line 51-1, 51-2...
...Which ones are connected?

On the other hand, the gates of the NMOs 855-1d, 55-2d, . . . are commonly connected to the gate control circuit 57.

The gate control circuit 57 has an input terminal 57 for the input signal VI.
a, and its input terminal 57a is connected to the input side of an inverter 57b. Output side BT of inverter 57b
is connected to the NMO 855-1d in the word line drive circuit group 55 at the node n1 via the boosting capacitor 57c.
It is commonly connected to each gate of 55-2d. Furthermore, between the node n1 and the power supply potential ■CC, an NMO 357d whose gate is connected to the power supply potential VCC is connected.
and NMO857e are connected in parallel. Further, the input terminal 57a is connected to the gate of the NMO 857e at a node n2 via a boosting capacitor 57f, and an NMO 857g whose gate is connected to the power supply potential VCC is connected between the node n2 and the power supply potential VCC. .

Note that the input signal VI is a signal that is at the "L11 level" when the dynamic RAM is in the standby state, and is at the "H°" level when the dynamic RAM is in the operating state, and the drive potential vpw is the ground potential vSS when the dynamic RAM is in the standby state. , which is a potential that is boosted to a predetermined potential in the operating state.

FIG. 4 is an operational waveform diagram of FIG. 1, and the operation of FIG. 1 will be explained with reference to this diagram. Note that for the sake of simplicity, a plurality of word line drive circuits 55-1, 55-2
. . . The illustrated circuit 55-1.55-2
I will explain about it.

(a> The operation input signal VI before time t1 is "L" level (standby state), and NM
Since O357g is in the on state, the potential V of node n2
n2 is Vn2=VCC-VTN However, VTN is the threshold voltage of NMO8. Since the output side BT of the inverter reaches the H°'' level, the potential Vnl of the node n1 is boosted by the capacitor 57c, and is expressed by the following equation.

Vn 1 =VCC+VTN+<2 Therefore, NIVIO855-1, d, and 55-2d are both turned on, and row selection signals 556-1 and 856-2 are both at II HIT level, so PMO355-1a.

Each gate of 55-2a is at power supply potential VCC.

Therefore, PMOs 855-1a and 55-2a are in an off state, and word lines 51-1 and 51-2 are not activated.

(b) When the operating input voltage VI at time tl-S-t2 reaches the "H°" level, the capacitor 5
7f boosts the potential Vn2 of the node n2 to Vn2=VCC+VTN+α. In addition, since the potential BT on the output side of the inverter 57b becomes "°L" level, the potential Vnl of the node nl decreases due to the coupling function of the capacitor 57c. However, since the potential Vn2 of the node n2 has increased, Potential Vnl becomes power supply potential VCC.

Thereafter, the row decoder 56 outputs a row selection signal 55, for example.
6-1 is selected, the row selection signal S-56-1
becomes I L l" level. At this time, NMO855-
Since the gate of 1d is at the "l Hl" level, it is already in the on state. As a result, the gate of P-MO 855-1a becomes L'' level, and P-MO 855-1a is turned on.

(C) Operation after time t2 to t3 When the driving potential vpw rises from the "L" level to vcc+vTN+α, the gate potential VGI of the 9MO 855-1a is boosted by the boosting operation of the capacitor 55-1b. However, since N-MO855-1d is on,
The gate potential of the P-MO 355-1a maintains the "L" level.

Therefore, the 9MO 855-1a is in an on state, and the potential of the word line 51-l rises to the same potential as the drive potential vpw. That is, the potential of the word line 51-1 becomes ``H1l level'', and the NMO 853a in the memory cell 53 is turned on.

Here, when writing information 11 I 11 to the memory cell 53, for example, the bit line 52-■ selected by a column decoder (not shown) becomes "H" level.

At this time, “
H" level is transmitted, and charges are redistributed between the parasitic capacitance of the bit line 52-1 and the capacitor 53b. As a result, information "1" is written into the memory cell 53.

On the other hand, since the row selection signal 556-2 is in a non-selected state at this time, it maintains the "H°° level and 9MO855-2
The gate potential VG2 of a is at the 11 HII level. However, the driving potential VPW increases and the capacitor 5
By the boosting operation of 5-2b, the gate potential VG2 of the 9MO855-2a is boosted to VG2=VCC+VTN+β and then VO2>VCC+VT'N+α.

At this time, NMO855-2d is 41.9MO855-2
The gate side of a serves as a drain, and the node N2 side serves as a source. Therefore, since the potential Vnl of the node nl, which is the gate potential, and the row selection signal 556-2 are both the power supply voltage VCC, the gate-source potential VGS becomes equal to or lower than the threshold voltage VTN. As a result, N.M.O.
855-2d is turned off, and the gate potential VG2 of 9MO 855-2a is maintained at the boosted level. Therefore, P.M.O.
355-2a remains off, word line 51-
2 remains inactive.

(d) Operation after time t3 When the input potential VI reaches the II L II level (standby state) again, the potential Vn2 of the node n2 changes to the capacitor 5.
It is reduced by the coupling function of 7f. However, N.M.
Due to the action of O357g, the following equation is obtained.

Vn2=VCC-VTN Further, the output side BT of the inverter 57b becomes "H" level, and the potential Vnl of the node n1 is boosted to Vn1=VCC+V'l'N+α by the boosting operation of the capacitor 57c.

Here, the row selection signal 556 which is the output of the row decoder 56
-1,356-2 both reach "H'° level,"
NMO855-1c and 55-2c are each turned on. As a result, word lines 51-1 and 51-2 both become the ground potential VSS and become inactive. Also, 9MO
855-1a.

Each gate voltage VGI, VG2 of 55-2a is at time t2.
In order to obtain a high potential when boosting the drive potential vpw at ~t3, it is necessary to maintain the potential at a high potential even after time t3. The voltages VGI and VG2 are the row selection signal 556-1.8 because the potential Vnl of the node n1 is boosted.
The power supply potential VCC is the same as the potential of 56-2.

In this embodiment, from time t2 to t3, the gate potential of the PMO 855-2a is boosted by the source potential with the gate potential VG2 being higher than the source potential, so the gate potential is always high and the PMO 8552a is turned on. . Never. Therefore, there are the following advantages.

(1) Drive potential vpw is PMO855-2a and NMO
855-2c, it is possible to prevent the ground potential VSS from leaking.

(2> PMO355-2a to NMO855-2C
Since no current flows through the unselected word line 51-
The potential of 2 is not increased. Therefore, the NMO 853 in the memory cell 53 connected to the word line 5■-2
A can be prevented from turning on, and data in the memory cell 53 can be prevented from being destroyed.

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. For example:

(A> In the above embodiment, an 1-transistor type memory cell is used as the memory cell 53, but other transistor configurations such as a 3-transistor type configuration may be used, for example.

(B) NMO855-1d, 55-2d...
・is configured with PMO8, and the gate control circuit 5 is configured accordingly.
Even if 7 is replaced with a different circuit configuration, almost the same effect as in the above embodiment can be obtained.

(Effects of the Invention) As explained in detail above, in the present invention, the PMOS gate potential in the word line drive circuit is boosted by the drive potential,
Since NMO8 is provided between PMO8 and the row decoder to maintain the boosted gate charge, the gate potential of PMO8 in the unselected word line drive circuit is always higher than the source potential, and PMO8 is It never turns on.

Therefore, the charge of the drive potential is not leaked by unselected word line drive circuits, and can be efficiently transmitted to the selected word line.

Moreover, it is possible to prevent the storage data in the memory cells from being destroyed due to the rise in the potential of unselected word lines.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a dynamic RAM showing an embodiment of the present invention, FIG. 2 is a circuit diagram of a conventional l-transistor type dynamic RAM cell, FIG. 3 is a block diagram of the configuration of a conventional dynamic RAM, and FIG. is an operating waveform diagram of FIG. 1. 50... Memory cell array, 51-1.512
・・・・・・Word line, 52-1.52-2・・・・・・
・Bit line, 53...Memory cell, 54...
...Sense amplifier, 55...Word line drive circuit group, 55-1.55-2...Word line drive circuit, 55-1a, 55-55-2a---- --P, 5
5-1b, 55-2b・, Boosting capacitor, 5
5-1d, 55-2d...NMO5,56...
... Row decoder, 57 ... Gate control circuit, 556-1, 556-2 ... Row selection signal, V
CC...Power supply voltage, VSS...Ground potential, VPW...Drive potential, vcp...
Fixed potential.

Claims (1)

[Scope of Claims] A P-channel MOS transistor whose on/off control is controlled by the output of a row decoder for address decoding, and whose source is connected to a drive potential and whose drain is connected to a word line, and which is turned on by the output of the row decoder. - In a word line drive circuit in a semiconductor memory device having a complementary MOS transistor configuration, the word line drive circuit includes an N-channel MOS transistor which is turned off and whose drain is connected to the word line and whose source is connected to a constant potential. a boosting capacitor connected between the gate and source of the MOS transistor; and a MOS transistor connected between the output side of the row decoder and the gate of the P-channel MOS transistor and turned on and off at a predetermined timing. A word line drive circuit comprising: