JPH0341914B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a synchronization signal protection circuit in a PCM recording and reproducing apparatus.

Conventionally, analog signals have been recorded and reproduced using a method in which the analog signals are recorded as they are on a magnetic tape or magnetic disk, and then reproduced. However, in the above-mentioned conventional system, there are limits to the frequency characteristics and dynamic range due to the characteristics of the recording medium and conversion system. In response to this problem, the PCM method has been adopted as a method for performing high-quality recording, playback, or transmission regardless of the characteristics of the recording medium or conversion system. According to this PCM method, the frequency band depends on the sampling period and the dynamic range depends on the number of quantization bits, so it is possible to expand the frequency band or dynamic range as long as the recording medium and conversion system band allow. can. but,
In this case, a wideband recording and reproducing device is required. Generally, a video tape recorder (hereinafter referred to as VTR) is a wideband recording/playback device.
A block diagram of a PCM recording and reproducing apparatus using a two-head helical scan type VTR as a recording medium is shown in FIG. 1, and its operation will be outlined below.

In Figure 1, analog input signal 1 is an A/D
The signal is converted into a digital signal 3 by an (analog-digital) converter 2 . The digital signal 3 is sequentially recorded in a recording system memory 4, and the digital signal is read from there. Here, time compression is performed by making the read cycle shorter than the recording cycle. The time-compressed data 5 is input to a data generation circuit 6, to which error correction data and error detection data are added and output as recording digital data 7. This recording digital data 7
In addition, horizontal and vertical synchronization signals are added in the video waveform generation circuit 8, and the video signal 9 is output to the VTR.
It is recorded in 10. A reproduced video signal 11 reproduced from the VTR 10 is checked for error data in an error check circuit 12, and is outputted as an error check circuit output signal 13 which is digital data plus an error check signal. The error check circuit output signal 13 is sequentially recorded in the reproduction system memory 14. Signal 15 recorded in playback memory 14
Time expansion is performed by setting the read cycle when reading out to be longer than the recording cycle. An error processing circuit 16 corrects erroneous data from the time-expanded data using an error check signal to obtain a corrected signal 17. The corrected signal 17 is converted into an analog signal 19 by a D/A (digital to analog) converter 18 and output.

In such a PCM recording/playback device,
Since the horizontal and vertical synchronization signals are the origin of timing, a loss of synchronization signals will cause malfunctions. A synchronous signal protection circuit is essential to prevent this malfunction. In particular, there is a problem of skew with respect to the horizontal synchronization signal, and the protection circuit needs to be devised.

Figure 2 shows a conventional protection circuit, that is, a replenishment circuit that supplements when the horizontal synchronization signal is missing.
The figure shows a waveform diagram from detection to output of the horizontal synchronization signal. In FIG. 2, 20 is a horizontal synchronizing signal detection circuit, and 21 is a supplementary circuit. Horizontal synchronization signal circuit 2
0, the gate is closed for an appropriate time (for example, 62 μs) after detecting the horizontal synchronizing signal _H1 from the composite signal Sc as shown in Fig.
Avoid taking in 1H (63.5μs, equivalent to 168 clocks in 26MHz clock units) noise as a synchronization signal. Next, open the gate, wait for about 10 clocks for the horizontal synchronization signal to be input, and if there is an input signal, output it and repeat the above operation. If the horizontal synchronizing signal is not input here, the replenishment circuit 21 is operated to replenish the horizontal synchronizing signal H ₂ ' as shown in FIG. 3.
FIG. 34 shows the output signals, in which in the above case the correct horizontal synchronization signal output H ₁ '' is followed by the supplementary output H ₂ ''.

However, if this circuit configuration remains as it is, there is a risk that the skew portion of the VTR will malfunction. In the case of a helical scan VTR, the horizontal synchronization signal time width becomes extremely short or long when switching heads (this is called skew, and is approximately ±20 μs at most). If the distance between the horizontal synchronization signals is now shorter than usual, the above circuit will work, but the circuit shown in Fig. 3
If the length is increased due to skew as shown in H ₂ , the supplementary signal H ₂ ' will be output before the correct horizontal sync signal H ₂ is detected, and then the correct horizontal sync signal H ₂ will be detected, resulting in Therefore, the number of synchronization signals increases by one. To prevent this, the gate G must be applied for an appropriate time (for example, about 40 μs) as shown in FIG. 3 after the supplementary signal H ₂ ' is issued to prevent the synchronization signal from increasing.

It is possible to operate the device almost normally by using the above number of times, but this circuit cannot wait until the next horizontal synchronizing signal is detected after one horizontal synchronizing signal H ₂ ' is added. If two consecutive horizontal synchronization signals are lost due to this condition, or if the horizontal synchronization signal is lost for several tens of hours due to dropout, there is a possibility of malfunction. In FIG. 3, H ₃ is a missing horizontal sync signal that is good for dropouts,
In this case, the replenishment circuit 21 does not issue a replenishment signal.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronization signal replenishment circuit that eliminates the drawbacks of the prior art described above and replenishes a synchronization signal at a normal position even if the synchronization signal is missing for a long time.

In the present invention, when one synchronization signal is missing or when it is not in the correct position due to skew, it is replenished by the conventional replenishment circuit, and when the next correct horizontal synchronization signal does not arrive, it is automatically refilled. It is characterized in that the synchronizing signal is replenished by the second replenishment circuit running.

Hereinafter, the present invention will be explained with reference to an embodiment shown in the drawings. FIG. 4 is a block diagram showing one embodiment of the present invention. In FIG. 4, 20 is a horizontal synchronizing signal detection circuit, 21 is a supplementary circuit (hereinafter referred to as a first supplementary circuit), 22 is a second supplementary circuit, and 23 is an output switching circuit.

Horizontal synchronization signal detection circuit 20 and first supplementary circuit 21
The operation is similar to that described in the conventional example. That is, when one horizontal synchronizing signal is missing or deviates from the normal position due to skew, the first replenishing circuit 21 replenishes one horizontal synchronizing signal. In the present invention, if a correct horizontal synchronizing signal cannot be detected thereafter, the output switching circuit 23 is switched to supplement the synchronizing signal from the second replenishing circuit 22, and the steady state is restored when the correct horizontal synchronizing signal is detected.

Now, to explain the second supplementary circuit 22,
Generally, the horizontal synchronization signal has 168 clocks per cycle.
Since the signal has a width of 13 clocks, the horizontal synchronizing signal can be outputted at all times by keeping the 168-decimal counter in operation and used as the output pulse of the second supplementary circuit 22. If this counter is reset each time a correct horizontal synchronizing signal is detected, it becomes possible to replenish the synchronizing signal at almost the normal position. FIG. 5 shows an embodiment of the second supplementary circuit. 24 in Figure 5
is an 8-bit counter, 25 is a 13, 168 decoder,
26 is a reset circuit, and Hd is a detected horizontal synchronizing signal.

Next, the output switching circuit 23 will be explained. The output switching circuit 23 switches between a detection signal and a supplementary signal, and can be easily configured with a gate. FIG. 6 shows a timing chart of the horizontal synchronizing signal replenishment circuit of the present invention. In the figure, 1 is the detection signal of the horizontal synchronization signal detection circuit 20, 2 is the output signal of the first supplementary circuit 21, 3 is the first supplementary circuit output gate, 4 is the output signal of the second supplementary circuit 22, and 5 is the output signal of the second supplementary circuit 22. 2
Replenishment circuit output gate, 6 is an output signal. Second supplementary circuit output a″(a), b″(a), C″(a) in Figure 4
. . . The symbol in parentheses indicates that the 168-decimal counter (8-bit counter 24) is reset by the horizontal synchronization detection signal 1 with the same symbol and becomes the output of the second supplementary circuit 22. ing. This reset triggers the detection signal 1 as shown in output e″(e).
When input twice in succession (d, e), it is regarded as a correct detection signal and reset is performed. In addition, the output 2 of the first replenishment circuit 21 and the second replenishment circuit 22
To switch the output 4, as shown in FIGS. 3 and 5, the gate of the first replenishment circuit 21 is opened after a predetermined time after the output 2 is output, and the gate of the second replenishment circuit 22 is closed at the same time. As a result, the output signal shown in FIG. 6 can be obtained.

Here, as described in the prior art, as a countermeasure when the time interval of the horizontal synchronizing signal becomes longer due to skew, the gate width of the second supplementary circuit 22 is changed as shown in FIG. 7. The gate signal 5 is set to be shorter than the one in FIG. A pulse width generation circuit is provided separately from the counter 24) and is operated by the output of the second replenishment circuit, so that once the output of the second replenishment circuit is output as shown in FIG. After the circuit operates, as shown in FIG.
20 μs) The output of the second supplementary circuit may not be generated. Note that waveforms 1, 2, 3, 4, and 7 in FIG. 7 correspond to waveforms 1, 2, 3, 4, and 6 in FIG. 6, respectively.
It is the same kind of thing.

As explained above, according to the present invention, the VTR
When the horizontal synchronization signal is lost for a long time due to dropout, etc., or when the horizontal synchronization signal shifts due to skew, the horizontal synchronization signal can always be replenished at almost the correct position. This makes it possible to further stabilize the operation of the recording/reproducing device.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a PCM recording/playback device.
FIG. 2 is a block diagram of a conventional horizontal synchronization signal protection circuit, FIG. 3 is a time chart showing the operation of the conventional circuit shown in FIG. 2, and FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 is a block diagram of one embodiment of the counter used in the present invention, and FIGS. 6 and 7 are time charts showing the circuit operation of the present invention. 20: horizontal synchronization signal detection circuit, 21: first supplementary circuit, 22: second supplementary circuit, 23: output switching circuit.

Claims (1)

[Claims] 1. A synchronization signal detection circuit that detects a synchronization signal from a reproduced signal, and a first circuit that is controlled by the output of the detection circuit and derives a supplementary signal when there is no output of the detection circuit.
a second replenishment circuit configured with a self-running counter and derives a replenishment signal in relation to the output timing of the detection circuit; and an output switch for selecting the outputs of the first and second replenishment circuits. In the circuit, if there is one synchronization signal missing based on the detection result of the detection circuit, the output of the first supplementary circuit is derived, and if there are consecutive omissions, the output of the second supplementary circuit is derived. A synchronous signal protection circuit comprising at least an output switching circuit for deriving output.